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Title:
METHOD FOR PREPARING SHIELD-GATE TRENCH FIELD-EFFECT TRANSISTOR
Document Type and Number:
WIPO Patent Application WO/2023/201887
Kind Code:
A1
Abstract:
Provided in the present invention is a method for preparing a shield-gate trench field-effect transistor, comprising: forming a barrier stack on a substrate, comprising a first barrier layer, a second barrier layer, and a third barrier layer that are stacked in sequence; forming a graphical window in the barrier stack, etching first trenches, and retaining the first barrier layer, the second barrier layer, and a part of the third barrier layer; forming field plates on the bottom and side wall of the first trenches; depositing a polycrystalline silicon layer, the first trenches being filled with the polycrystalline silicon layer; removing the polycrystalline silicon layer on the top surface of the third barrier layer and a part of the polycrystalline silicon layer in the first trenches to form second trenches; performing ion implantation to achieve ion doping of the polycrystalline silicon layer in the trenches, so as to increase IPO thickness, thereby optimizing G-S leakage performance. According to the present invention, the process can be effectively simplified, a process window for ion implantation is increased, process difficulty is reduced, and process costs are saved. In addition, the optimization process does not interfere with a front-end design simulation effect and basically has no influence on electrical parameters.

Inventors:
GU GUANGUAN (CN)
YAN YILIN (CN)
LIU LONGPING (CN)
Application Number:
PCT/CN2022/102331
Publication Date:
October 26, 2023
Filing Date:
June 29, 2022
Export Citation:
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Assignee:
GTA SEMICONDUCTOR CO LTD (CN)
International Classes:
H01L29/423; H01L21/336; H01L29/78
Foreign References:
CN114050109A2022-02-15
CN108831859A2018-11-16
CN114284149A2022-04-05
CN104037082A2014-09-10
CN112864237A2021-05-28
US9761695B12017-09-12
Attorney, Agent or Firm:
J.Z.M.C. PATENT AND TRADEMARK LAW OFFICE (GENERAL PARTNERSHIP) (CN)
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