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Title:
METHOD FOR REALIZING NETWORK NODE TIME SYNCHRONIZATION BASED ON FPGA
Document Type and Number:
WIPO Patent Application WO/2023/213080
Kind Code:
A1
Abstract:
The present invention particularly relates to a method for realizing network node time synchronization based on an FPGA, comprising the following steps: constructing a local clock module; designing a pulse synchronization module on the basis of constructing the local clock module; on the basis of designing the pulse synchronization module, encapsulating Ethernet message frames in a path delay measurement process and a time synchronization process; on the basis of encapsulating the Ethernet message frames in the path delay measurement process and the time synchronization process, recording a timestamp value of a moment when a message is sent at node i and a timestamp value of a moment when the message is received at node i+1; on the basis of recording the timestamp value of the moment when the message is sent at node i and the timestamp value of the moment when the message is received at node i+1, calculating the obtained timestamp values to obtain a path delay measurement result; and on the basis of calculating the obtained timestamp values to obtain the path delay measurement result, sending a time synchronization message. Provided is a time synchronization method having low cost, high precision and stability, which meets accurate scheduling and various communication requirements.

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Inventors:
XU YANLI (CN)
SHANG JIAN (CN)
LIN HAIJIAO (CN)
MA GUIYANG (CN)
ZHU HUALI (CN)
Application Number:
PCT/CN2022/139566
Publication Date:
November 09, 2023
Filing Date:
December 16, 2022
Export Citation:
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Assignee:
UNIV SHANGHAI MARITIME (CN)
International Classes:
H04J3/06
Foreign References:
CN109818702A2019-05-28
CN111262796A2020-06-09
CN113055116A2021-06-29
CN114884605A2022-08-09
Attorney, Agent or Firm:
SHANGHAI NUOYI INTELLECTUAL PROPERTY AGENCY (CN)
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