METHOD FOR REDUCING SENSITIVITY MODULATION AND LAG IN

ELECTRONIC IMAGERS

TECHNICAL FIELD

[0001] This invention relates to the field of an imaging system and, in particular, to solid state detectors.

BACKGROUND

[0002] A Computed Tomography system may collect data by using a large flat panel digital x-ray device, imager, or detector, having a plurality of pixels arranged in rows and columns. Large flat panel imagers function by accumulating charge on capacitors generated by the pixels of photodiodes (amorphous silicon or organic semiconductor) with scintillators or by pixels of photoconductors. Typically, many pixels are arranged over a surface of the imager where TFTs (or single and/or double diodes) at each pixel connect the charged capacitor to a read-out amplifier at the appropriate time. A pixel is composed of the scintillator/photodiode/capacitor/TFT or switching-diode combination or by the photoconductor/capacitor/TFT or switching-diode combination. Often the photodiode intrinsically has enough capacitance that no separate charge storage capacitor is required. Radiation (e.g., alpha, beta, gamma, X-ray, neutrons, protons, heavy ions, etc.) strikes the scintillator and causes the scintillator to generate visible light. The visible light strikes a photodiode and generates an electric current. Alternatively, an imager may be configured such that the radiation strikes a biased photoconductor to generate the electric current. The current charges a capacitor and leaves a charge on the capacitor. The integrated charge on the capacitor is proportional to the integrated light intensity striking the respective photoconductor for a given integration time. At an appropriate time, a switch (e.g., a TFT or switching diode(s)) activates and reads out the charge from the capacitor. [0003] However, such flat panel imagers suffer from detector lag. The detector lag causes a significant portion of the signals from previous samples to incorrectly bias subsequent samples. A significant cause of the lag is related to the electron de-trapping resulting from the high density electronic defects in the energy band gap. De-trapping times range from a few milliseconds to as long as 100 seconds, days, weeks, or even months. As a result of the non-uniformity of the lag, artifacts, such as rings and bands, occur in the reconstructed images.

[0004] Prior correction methods have been implemented to estimate offset correction.

One prior background correction method discussed in U.S. Patent No. 5,249,123 applies a filter function to the output signal. Another prior background correct method discussed in U.S. Patent No. 6,701,000 energizes each detector pixel to reduce residual signal in-between data acquisitions when the x-ray emission is stopped. LEDs that are built into the panel saturate the traps in the detector, which minimize the temporal artifacts. However, exposing each detector pixel to an evenly distributed light complicates the mechanical construction of flat panel imagers and increases their manufacturing costs. Furthermore, the LEDs and the light distribution can interfere with x-ray beams that need to be imaged.

BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings.

[0006] FIG. IA is a schematic diagram illustrating one embodiment of a detector.

[0007] FIG. IB is a schematic diagram of a classification of the artifacts and their sources.

[0008] FIG. 2 is a schematic diagram illustrating one embodiment of an imaging system.

[0009] FIG. 3 A is a schematic circuit diagram illustrating one embodiment of a detector.

[0010] FIG. 3B is a schematic circuit diagram illustrating one embodiment of a detector.

[0011] FIG. 4 is a flow diagram illustrating one embodiment of a method for operating the detector of FIG. 3.

[0012] FIG. 5 is a schematic timing diagram illustrating one embodiment of readout of the detector of FIG. 3.

[0013] FIG. 6 is a graph diagram illustrating a relative gain as a function of frame number.

[0014] FIG. 7 is a graph diagram illustrating a relative lag as a function of frame number.

[0015] FIG. 8 is a schematic circuit diagram illustrating another embodiment of a detector.

[0016] FIG. 9 is a schematic timing diagram illustrating one embodiment of readout of the detector of FIG. 8.

[0017] FIG. 10 is a schematic circuit diagram illustrating another embodiment of a detector.

[0018] FIG. 1 1 is a schematic timing diagram illustrating one embodiment of readout of the detector of FIG. 10.

[0019] FIG. 12 is a schematic circuit diagram illustrating another embodiment of a detector.

[0020] FIG. 13 is a schematic timing diagram illustrating one embodiment of readout of the detector of FIG. 12.

[0021] FIG. 14 is a flow diagram illustrating a method for correcting an output of a detector in accordance with one embodiment.

DETAILED DESCRIPTION

[0022] The following description sets forth numerous specific details such as examples of specific systems, components, methods, and so forth, in order to provide a good understanding of several embodiments of the present invention. It will be apparent to one skilled in the art, however, that at least some embodiments of the present invention may be practiced without these specific details. In other instances, well-known components or methods are not described in detail or are presented in simple block diagram format in order to avoid unnecessarily obscuring the present invention. Thus, the specific details set forth are merely exemplary. Particular implementations may vary from these exemplary details and still be contemplated to be within the spirit and scope of the present invention. [0023] Embodiments of the present invention include various operations, which will be described below. These operations may be performed by hardware components, software, firmware, or a combination thereof. As used herein, the term "coupled to" may mean coupled directly or indirectly through one or more intervening components. Any of the signals provided over various buses described herein may be time multiplexed with other signals and provided over one or more common buses. Additionally, the interconnection between circuit components or blocks may be shown as buses or as single signal lines. Each of the buses may alternatively be one or more single signal lines and each of the single signal lines may alternatively be buses.

[0024] Certain embodiments may be implemented as a computer program product that may include instructions stored on a machine-readable medium. These instructions may

be used to program a general-purpose or special-purpose processor to perform the described operations. A machine-readable medium includes any mechanism for storing or transmitting information in a form (e.g., software, processing application) readable by a machine (e.g., a computer). The machine-readable medium may include, but is not limited to, magnetic storage medium (e.g., floppy diskette); optical storage medium (e.g., CD-ROM); magneto- optical storage medium; read-only memory (ROM); random-access memory (RAM); erasable programmable memory (e.g., EPROM and EEPROM); flash memory; electrical, optical, acoustical, or other form of propagated signal (e.g., carrier waves, infrared signals, digital signals, etc.); or another type of medium suitable for storing electronic instructions. [0025] Additionally, some embodiments may be practiced in distributed computing environments where the machine-readable medium is stored on and/or executed by more than one computer system. In addition, the information transferred between computer systems may either be pulled or pushed across the communication medium connecting the computer systems.

[0026] FIG. IA is a schematic diagram illustrating one embodiment of a detector 100.

The detector 100 may be a solid-state detector or radiation imager in a large flat panel configuration having a photosensor array 104 disposed on a substrate 102 and a scintillator 106 disposed on the photosensor array 104. Scintillator 106 is disposed so as to receive and absorb incident radiation, e.g., x-ray beam 108. Scintillator 106 is optically coupled to photosensor array 104 so that optical photons generated in scintillator 106 pass into photosensor array 104. Photosensor array 104 may include a plurality of photosensors (not shown), such as photodiodes, and an addressable thin film transistor (TFT) array (not shown) electrically coupled to each photosensor. In one embodiment, each photosensor includes an amorphous silicon (a-Si) photodiode (not shown).

[0027] FIG. IB is a schematic diagram of a classification of the artifacts and their sources. Artifacts 110 may include residual signals 112 of a detector and gain effects 114 from the traps already filled in the detector. The residual signals 112 may be caused by the photodiode (PD) lag effect 116. The gain effects 114 may be caused by the PD gain effect 118.

[0028] FIG. 2 is a schematic diagram illustrating one embodiment of an imaging system. Imaging system 200 includes a computing device 206 coupled to detector 100. The detector 100, may be also, for example, an amorphous silicon organic semiconductor TFT or diode-switched array imager. As previously discussed in FIG. 1, detector 100 functions by accumulating charge on capacitors generated by pixels of photodiodes (amorphous silicon or

organic semiconductor) with scintillators or by pixels of biased photoconductors. Typically, many pixels are arranged over a surface of the detector 100 where, for example, TFTs (or single and/or double diodes) at each pixel connect a charged capacitor to charge sensitive amplifier 202 at the appropriate time. Charge sensitive amplifiers 202 drive analog to digital (AJO) converter 204 that, in turn, converts the analog signals received from amplifiers 202 into digital signals for processing by computing device 206. A/D converter 204 may be coupled to computing device 206 using, for example, I/O device 210 or interconnect 216. A/D converter 204 and charge sensitive amplifiers 202 may reside within computing device 206 or detector 100 or external to either device.

[0029] Computing device 206 implements the methods for correction of imaging sensors due to the traps from the detector 100. The methods that may be performed by computing device 206 constitute computer programs made up of computer-executable instructions illustrated as steps in the following examples of the methods illustrated in the following figures. In one embodiment, computing device 206 includes a processor 208, storage device 212, input/output (IO) device 210, and memory 214 that are all coupled together with interconnect 216, such as a bus or other data path. In another embodiment, the computing device may be implemented using Programmable Logic Devices (PLD) or Field Programmable Gate Arrays (FPGA), in which the mathematical operations are performed by physical devices like adders, multipliers, etc. In another embodiment, the computing device may be implemented using specialized integrated circuits for data processing like adders, multipliers, bus switches, registers, RAM, ROM logic gates, etc.

[0030] Processor 208 represents a central processing unit of any type of architecture

(e.g., Intel architecture or Sun Microsystems architecture), or hybrid architecture. In addition, processor 208 could be implemented in one or more semiconductor chips. In an alternative embodiment, for example, the processor 208 may be a network processor having multiple processors including a core unit and multiple microengines. Additionally, processor 208 may include any combination of general-purpose processing device(s) and special-purpose processing device(s).

[0031] Storage device 212 represents one or more mechanisms for storing data and/or instructions such as the method steps of the invention. Storage device 212 represents readonly memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, and/or other machine-readable media. Interconnect 216 represents one or more buses (e.g., accelerated graphics port bus, peripheral component interconnect bus, industry standard architecture bus, X-Bus, video electronics standards

association related buses, etc.) and bridges (also termed bus controllers). I/O device 216 represents any of a set of conventional computer input and/or output devices including, for example, a keyboard, mouse, trackball or other pointing device, serial or parallel input device, display monitor, plasma screen, or similar conventional computer I/O devices.

[0032] Memory 214 represents a high-speed memory device for retaining data and processor instructions for processor 208 according to the method steps of the invention.

Memory 214 can be implemented using any of the memory devices described above for storage device 212. In addition, memory 214 can be used as a data cache for processor 208.

While this embodiment is described in relation to a single processor computer system, in another embodiment, the invention may be implemented in a multi-processor computer system.

[0033] To keep the amorphous Silicon traps in the detector in a steady state, a forward bias current is periodically applied to the diodes, or photodiodes. This forward bias current provides the free carries necessary to keep a majority of the trap states occupied. The time interval between applying the forward bias current can be selected depending on the application.

[0034] In accordance with one embodiment, a forward bias current pulse is applied for each frame. As such, photodiode gain and lag effects are reduced significantly and uniformly for all exposures.

[0035] In accordance with another embodiment, a forward bias current cycle may be used to fill the amorphous Silicon trap states before the start of an image acquisition sequence. This effectively "erases" the exposure history of the detector by filling all traps uniformly, effectively setting the imaging system into a known state.

[0036] In accordance with other embodiments, if pixels with open TFT's can be assumed "floating", one could switch all pixels from a negative to a positive bias voltage without changing the voltage across these diodes but by just shifting their potential in reference to the ground. Pixels with open TFTs would therefore still integrate charge generated by light photons and only pixels with closed TFTs would see a forward bias current. This embodiment allows an implementation of the forward bias current method which is compatible with continuous x-ray exposure.

[0037] FIGS. 3 A and 3B are schematic circuit diagrams illustrating one embodiment of a detector. A switch 302 switches a connection between a negative bias voltage source

304, as illustrated in FIG. 3A, and a positive bias voltage 306, as illustrated in FIG. 3B. A photodiode 308 is connected in parallel with a capacitor 310. The capacitor may be, for

example, an intrinsic capacitor of about 2pF. However, other types of capacitors of different capacitances may also be used.

[0038] Both the capacitor 310 and the cathode end of the photodiode 308 are connected to a switch, such as a pixel Thin Film Transistor (TFT) 311. Other types of switches may also be used. An amplifier, such as a Charge Integration Amplifier 312, may be connected to an end of the pixel TFT 311. The amplifier may also include an integration capacitor 314 and another switch, such as a reset TFT 316.

[0039] FIG. 3A illustrates a photodiode and its associated TFT and charge integration amplifier configured for a normal reversed bias photodiode operation. The negative voltage source may generate a negative voltage of, for example, about -4.5 V. The anode end of the photodiode 308 is connected to the switch 302. As such, the anode potential of the photodiode 308 can be switched from the normal negative bias voltage from the negative voltage source 304 to a positive voltage from the positive voltage source 306. The control of the switch 302 may be implemented into the software or hardware of the imaging system 200. [0040] The forward bias cycle is initialized by applying a positive voltage to the photodiode anode, e.g. switching the switch to connect to the positive voltage source 306. Then, both the pixel TFT 311 and the reset TFT 316 of the charge integration amplifier 312 are closed to allow the current to flow. A forward current (indicated by the arrows in FIG. 3B) flows through the photodiode 308, providing free carriers to fill available amorphous Silicon traps. The forward bias cycle is terminated by opening the two TFT's 311, 316 and then reapplying a negative bias voltage to the anode of the photodiode 308 such that the photodiode 308 is reversed bias.

[0041] In accordance with one embodiment, prior to an x-ray exposure, the photodiodes may be reset to their reversed bias state. This is accomplished by closing both TFT 31 1 , 316 for an appropriate duration. Optionally, this reset cycle may be repeated a second time after several milliseconds to ensure that potential disturbances created by the forward bias cycle would not affect the reset state of the photodiode 308. Once reset, the system is ready for the next x-ray exposure and signal readout after which the next forward bias cycle is started.

[0042] FIG. 3B illustrates how the current forward bias flows through the circuit when switch 302 is connected to the positive voltage source. Both TFT 31 1 , and 316 are shown closed allowing the current to freely flow through. When the forward bias current flows through photodiode 308, a majority of the trap states in the photodiode 308 is occupied.

[0043] FIG. 4 is a flow diagram of a frame-by-frame forward bias method. At 402, an x-ray beam is projected onto a detector of an imaging system as previously described in FIG. 2 to start a frame. At 404, the detector read signal from the previous x-ray exposure in 402. At 406, a forward bias cycle is applied to the detector to "flood" the photodiodes with free carriers to fill the available trap states. At 408, the photodiodes are reset back to their reversed bias state. At 410, a second reset cycle may be optionally applied. The imaging system is now ready for the next x-ray exposure at 412.

[0044] FIG. 5 is a schematic timing diagram of the method of FIG. 4. The frame start line 502 illustrates a period of time when the detector is exposed with x-ray. The imager readout line 504 illustrates a period of time when the detector detects the x-ray from the x-ray beams. The forward bias switch line 506 illustrates a period of time when the switch 302 is connected to the positive voltage source 306. The scan line 508 illustrates a period of time when resets are being applied to the detector. The forward bias switch is enabled as illustrated in 506 upon the detector finishing with the readout as illustrated in 504. [0045] FIG. 6 is a graph diagram illustrating a relative gain as a function of frame number. The gain effects with forward bias current and without forward bias current are shown. Without forward bias, there is approximately a 2.3% gain change from frame 1 to frame 20. With a forward bias cycle of 100nA*40us per diode, this gain change is reduced to approximately 0.2%.

[0046] FIG. 7 is a graph diagram illustrating a relative lag as a function of frame number. The graph shows similar improvement between a relative lag without forward bias current and with forward bias current.

[0047] FIG. 8 is a schematic circuit diagram illustrating another embodiment of a detector with one transistor. The anode end of a photodiode 802 is connected to a voltage source VBl . The cathode end of the photodiode 802 is connected to a transistor 804 (e.g. a TFT Tl). The transistor 804 may be connected to a voltage line VG 806 and a voltage line VD 808 of an amplifier 810.

[0048] FIG. 9 is a schematic timing diagram illustrating one embodiment of readout of the detector of FIG. 8. A forward bias current can be applied across the photodiode 802 when voltage source VBl is greater than voltage line VD.

[0049] FIG. 10 is a schematic circuit diagram illustrating another embodiment of a detector with two transistors. The anode end of a photodiode 1002 is connected to a voltage source VBl . The cathode end of the photodiode 1002 is connected to a first transistor Tl 1004, and a second transistor T2 1006. Transistor Tl 1004 is connected to a voltage line VD

of an amplifier 1008 and a voltage line VG. Transistor T2 1006 is connected to a voltage line VB2 and a voltage line VF.

[0050] FIG. 11 is a schematic timing diagram illustrating one embodiment of readout of the detector of FIG. 10. In accordance with a first embodiment, a forward bias current can be applied to the photodiode 1002 when VB2 is less than VBl, and VB2 is substantially equal to VD. In accordance with a second embodiment, a forward bias current can be applied to the photodiode 1002 when VB2 is greater than VBl, and VB2 is substantially equal to VD. [0051] FIG. 12 is a schematic circuit diagram illustrating another embodiment of a detector with three transistors. The anode end of a photodiode 1202 is connected to a voltage source VBl . The cathode end of the photodiode 1202 is connected to a first transistor Tl 1204, a second transistor T2 1206, and a third transistor T3 1208. Transistor Tl 1204 is connected to a voltage line VD of an amplifier 1210 and a voltage line VG. Transistor T2 1206 is connected to a voltage line VB2 and a voltage line VF. Transistor T3 1208 is connected to a voltage line VB3 and a voltage line VI.

[0052] The potential of voltage line VB3 is substantially equal to the potential of voltage line VD. The potential of voltage line VB2 is less than the potential of voltage line VBl .

[0053] FIG. 13 is a schematic timing diagram illustrating one embodiment of readout of the detector of FIG. 12. A forward bias current can be applied across the photodiode 1202 when the potential voltage source VF is relatively increased.

[0054] FIG. 14 is a flow diagram illustrating a method for correcting an output of a detector in accordance with one embodiment. At 1402, data is collected from the detector. At 1404, a forward bias current is temporarily applied to the detector between collecting data. Those of ordinary skills in the art will recognize that there exist many other ways of applying a forward bias current. Other embodiments of the present invention also include any means for applying enough voltage to pass a current to inject carriers into regions to fill the traps in the solid state detector. Some examples were previously described. The voltage lines may be switched so as to apply a forward bias current. The potential of one of the voltage line may be lowered so as to apply a forward bias current.

[0055] Those of ordinary skills in the art will recognize that there are other variations of the presently described embodiments to substantially filling traps in the detector based on the detector circuits illustrated in FIGS. 3A, 3B, 8, 10, 12. For example, all the "anode" and "cathode" along with the voltage polarity in all the illustrated circuits may be reversed to yield the same result.

[0056] Although the operations of the method(s) herein are shown and described in a particular order, the order of the operations of each method may be altered so that certain operations may be performed in an inverse order or so that certain operation may be performed, at least in part, concurrently with other operations. In another embodiment, instructions or sub-operations of distinct operations may be in an intermittent and/or alternating manner.

[0057] In the foregoing specification, the invention has been described with reference to specific exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.