Title:
METHOD FOR REDUCING STACKING FAULTS IN SILICON CARBIDE, AND STRUCTURE CREATED BY MEANS OF SAID METHOD
Document Type and Number:
WIPO Patent Application WO/2023/058491
Kind Code:
A1
Abstract:
The present invention addresses the problem of providing novel technology for reducing stacking faults SF in silicon carbide. The present invention further addresses the problem of providing novel technology capable of reducing stacking faults SF using a small number of growth conditions. The present invention is a method for reducing stacking faults in silicon carbide, the method comprising a growth step S10 in which an epitaxial layer 20 is grown upon a bulk layer 10 of silicon carbide having stacking faults SF in a SiC-C equilibrium vapor pressure environment.
Inventors:
KANEKO TADAAKI (JP)
DOJIMA DAICHI (JP)
TODA KOHEI (JP)
SASAKI JUN (JP)
KOJIMA KIYOSHI (JP)
DOJIMA DAICHI (JP)
TODA KOHEI (JP)
SASAKI JUN (JP)
KOJIMA KIYOSHI (JP)
Application Number:
PCT/JP2022/035760
Publication Date:
April 13, 2023
Filing Date:
September 26, 2022
Export Citation:
Assignee:
KWANSEI GAKUIN EDUCATIONAL FOUND (JP)
TOYOTA TSUSHO CORP (JP)
TOYOTA TSUSHO CORP (JP)
International Classes:
H01L21/20; C30B29/36; H01L21/205; H01L21/336; H01L29/12; H01L29/78
Domestic Patent References:
| WO2020095872A1 | 2020-05-14 | |||
| WO2020095872A1 | 2020-05-14 |
Foreign References:
| JP2019160916A | 2019-09-19 | |||
| JP2020150181A | 2020-09-17 | |||
| JP2018162178A | 2018-10-18 |
Attorney, Agent or Firm:
TSUJITA, Tomoko et al. (JP)
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