A METHOD OF STACKING LAYERS CONTAINING ENCAPSULATED INTEGRATED CIRCUIT CHIPS WITH ONE OR MORE OVERLYING INTERCONNECT LAYERS

Title:

A METHOD OF STACKING LAYERS CONTAINING ENCAPSULATED INTEGRATED CIRCUIT CHIPS WITH ONE OR MORE OVERLYING INTERCONNECT LAYERS

Document Type and Number:

WIPO Patent Application WO2003038861

Kind Code:

A3

Abstract:

A pre-formed integrated circuit chip (50) is encapsulated into an electronic package, by forming an interconnect assembly (48) separately from the pre-formed integrated circuit chip (50). If the interconnect assembly (48) tests good it is bonded to the prepared integrated circuit chip (50). The interconnect assembly (48) is flip bonded to the chip (50). The interconnect assembly (48) and chip (50) are passivated or potted into an integral structure to provide the electronic package. At least one test pad (14, 18) is defined in an interconnect layer (74), which test pad (14, 18) can be accessed and electrically connected on opposing sides of the test pad. The chip is underfilled with an insulating material (54) to remove all voids between the chip (50) and the interconnect assembly (48). The integrated circuit chip is then thinned. The test pad (14, 18) is accessed to test the chip (50). A plurality of interconnect assemblies (48) and chips (50) are bonded together to form a corresponding plurality of electronic packages.

Inventors:

PEPE ANGEL ANTONIO (US)
YAMAGUCHI JAMES SATSUO (US)

Application Number:

PCT/US2002/034339

Publication Date:

December 29, 2005

Filing Date:

October 25, 2002

Export Citation:

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Assignee:

IRVINE SENSORS CORP (US)
PEPE ANGEL ANTONIO (US)
YAMAGUCHI JAMES SATSUO (US)

International Classes:

H01L21/68; H01L23/31; H01L23/538; H01L23/58; (IPC1-7): H01L21/44; H01L23/48

Foreign References:

US6235552B1	2001-05-22
US6184060B1	2001-02-06

Other References: