PROVIDING SIGNALS TO A VOLTAGE REGULATOR

Technical Field

Examples of the present disclosure relate to methods and apparatus for providing signals to a voltage regulator, for example to counteract an anticipated change in output voltage of the voltage regulator due to a change in load state of a component on the output of the voltage regulator.

Background

In many modern wireless communication applications, transmitters and receivers may be switched on and off rapidly. One reason for this could be that both transmitting and receiving is done on the same frequency, according to time division duplex (TDD), and that resources (like transmitters) are disabled when the resource is not needed to save power. A voltage regulator may be used to provide a substantially constant power supply voltage to a component such as a transmitter, receiver or other resource. When a voltage regulator experiences a change in load (referred to in some examples as a load step), the output voltage of that regulator will have a transient that depends on the size of the load step and regulation performance.

Voltage transients can be reduced using certain techniques such as speeding up regulator loop (increasing regulator bandwidth) or adding capacitors on the regulator output.

Speeding up the regulator loop can lead to instability, and may not mitigate much of the transient. Adding extra capacitance on the regulator output will slow down the regulator and will increase the cost of the design. Another technique of feed-forward or pre-charge has been used to mitigate transients in a cost- and size-efficient way, and may also shorten the transient in time compared to other techniques, but due to trimming with passive components the technique may mitigate only one size of a load step. The technique of precharge may inject a square pulse of current into the voltage regulator feedback loop. The square pulse current in this case can be adjusted in duration, but the square shape is not well adapted for controlling the regulation.

Summary Advantages provided by embodiments of this disclosure may for example provide the ability to adapt a feed-forward signal in or to a voltage regulator to many differently sized load steps in an improved manner compared to prior solutions. Example embodiments may mitigate the transient voltage disturbance in a voltage regulator due to a change in the load (load step) at a lower cost and/or size than prior solutions. Example embodiments may even be necessary in some scenarios to keep the regulator output voltage within specification when switching large currents on sensitive loads where the load current can vary, such as for example power amplifiers. Example embodiments may shorten a guard time between when the load is enabled (or changes its power state) and when the load needs to perform within a specification, and may thus lower the average power consumption over time.

One aspect of the present disclosure provides apparatus for providing signals to a voltage regulator. The apparatus is configured to provide a first signal to the voltage regulator to cause the voltage regulator to counteract a first anticipated change in output voltage at an output of the voltage regulator due to a first change in load state of a component on the output of the voltage regulator from a first load state to a second load state, wherein the amplitude and/or length of the first signal is based on a magnitude of the first change in the load state of the component. The apparatus is also configured to provide a second signal to the voltage regulator to counteract a second anticipated change in the output voltage at the output of the voltage regulator due to a second change in the load state of the component on the output of the voltage regulator from the second load state to a third load state, wherein the amplitude and/or length of the second signal is based on a magnitude of the second change in the load state of the component.

Another aspect of the present disclosure provides a circuit comprising a voltage regulator, a component and apparatus for providing a signal to the voltage regulator according to the above aspect.

A further aspect of the present disclosure provides a method of providing signals to a voltage regulator. The method comprises providing a first signal to the voltage regulator to cause the voltage regulator to counteract a first anticipated change in output voltage at an output of the voltage regulator due to a first change in load state of a component on the output of the voltage regulator from a first load state to a second load state, wherein the amplitude and/or length of the first signal is based on a magnitude of the first change in the load state of the component. The method also comprises providing a second signal to the voltage regulator to counteract a second anticipated change in the output voltage at the output of the voltage regulator due to a second change in the load state of the component on the output of the voltage regulator from the second load state to a third load state, wherein the amplitude and/or length of the second signal is based on a magnitude of the second change in the load state of the component.

Brief Description of the Drawings

For a better understanding of examples of the present disclosure, and to show more clearly how the examples may be carried into effect, reference will now be made, by way of example only, to the following drawings in which:

Figure 1 illustrates an example of a circuit comprising a voltage regulator, a component and apparatus for providing a signal to the voltage regulator;

Figure 2 shows an example of apparatus for providing signals to a voltage regulator;

Figure 3 illustrates examples of signals associated with the apparatus shown in Figure 2;

Figure 4 illustrates another example of a circuit comprising a voltage regulator, a component and apparatus for providing a signal to the voltage regulator; and

Figure 5 is a flow chart of an example of a method of providing signals to a voltage regulator.

Detailed Description

The following sets forth specific details, such as particular embodiments or examples for purposes of explanation and not limitation. It will be appreciated by one skilled in the art that other examples may be employed apart from these specific details. In some instances, detailed descriptions of well-known methods, nodes, interfaces, circuits, and devices are omitted so as not obscure the description with unnecessary detail. Those skilled in the art will appreciate that the functions described may be implemented in one or more nodes using hardware circuitry (e.g. analog and/or discrete logic gates interconnected to perform a specialized function, Application Specific Integrated Circuits (ASICs), Programmable Logic Arrays (PLAs), etc.) and/or using software programs and data in conjunction with one or more digital microprocessors or general purpose computers. Nodes that communicate using the air interface also have suitable radio communications circuitry. Moreover, where appropriate the technology can additionally be considered to be embodied entirely within any form of computer-readable memory, such as solid-state memory, magnetic disk, or optical disk containing an appropriate set of computer instructions that would cause a processor to carry out the techniques described herein.

Hardware implementation may include or encompass, without limitation, digital signal processor (DSP) hardware, a reduced instruction set processor, hardware (e.g. digital or analogue) circuitry including but not limited to application specific integrated circuit(s) (ASIC) and/or field programmable gate array(s) (FPGA(s)), and (where appropriate) state machines capable of performing such functions.

In some examples, prior knowledge of when a change in load state of a component (e.g. a load step) and the size of the step may be available, and this information can be used in some examples to compensate a voltage regulator and thus reduce or minimize the voltage transient in the output voltage of the regulator.

Example embodiments of this disclosure may provide apparatus and methods in which the transient response of a voltage regulator may be reduced or minimized when a load step occurs in a component to which the voltage regulator provides a regulated voltage. Example embodiments may be able to compensate for many differently sized load steps. Reasons for the load steps may include for example the enabling or disabling of components such as a power amplifier (PA), low noise amplifier (LNA), and/or parts of application specific integrated circuits (ASICs) to save energy consumption when the components (or parts of the components) are not being used, such as for example in a TDD cycle.

Examples embodiments may for example vary the length of a generated pulse to determine the amount of feed-forward for the voltage regulator. Since the time constant of a regulator may in some examples change very little with the size of the load step, passive components may be used to mitigate the voltage change, and the length of the pulse (which may be for example a feed-forward pulse for the voltage regulator) may be set to inject a different amount of charge into the voltage regulator feedback and compensate for different amplitudes of the load step.

As indicated above, advantages provided by embodiments of this disclosure may for example provide the ability to adapt a feed-forward signal in or to a voltage regulator to many differently sized load steps in an improved manner compared to prior solutions. Example embodiments may mitigate the transient voltage disturbance in a voltage regulator due to a change in the load (load step) at a lower cost and/or size than prior solutions. Example embodiments may even be necessary in some scenarios to keep the regulator output voltage within specification when switching large currents on sensitive loads where the load current can vary, such as for example power amplifiers. Example embodiments may shorten a guard time between when the load is enabled (or changes its power state) and when the load needs to perform within a specification, and may thus lower the average power consumption over time.

Figure 1 illustrates an example of a circuit comprising a voltage regulator 102, a component 104, and apparatus 106 for providing a signal to the voltage regulator. In some examples, the component 104 may be for example a deterministic load, signal processor, analog to digital converter (ADC), digital to analog converter (DAC), application specific integrated circuit (ASIC), field programmable grid array (FPGA), low noise amplifier (LNA), power amplifier (PA), transmitter circuit, receiver circuit and/or transceiver circuit. More generally, the component 104 may be for example any component or circuit that may exhibit a change in load state, or a load step. The voltage regulator 102 may for example provide an output voltage 108 at an output 110 of the voltage regulator 102 that provides a regulated voltage, e.g. a power supply voltage, to component 104.

The apparatus 106 is configured to counteract or compensate for any changes in the output voltage 108 of the voltage regulator 102 that may occur as a result of a change in load state of the component 104. More specifically, The apparatus 106 is configured to provide a first signal 112 to the voltage regulator 102 to cause the voltage regulator 102 to counteract a first anticipated change in output voltage 108 at the output 110 of the voltage regulator 102 due to a first change in load state of the component 104 on the output 110 of the voltage regulator 102 from a first load state to a second load state. The amplitude and/or length of the first signal 112 is based on a magnitude of the first change in the load state of the component 104.

Similarly, the apparatus 106 is configured to provide a second signal 112 to the voltage regulator 102 to counteract a second anticipated change in the output voltage 108 at the output 110 of the voltage regulator 102 due to a second change in the load state of the component 104 on the output 110 of the voltage regulator 102 from the second load state to a third load state. The amplitude and/or length of the second signal 112 is based on a magnitude of the second change in the load state of the component 104. Thus, for example, the apparatus 106 may compensate the voltage regulator 102 for different changes in load state (e.g. different load steps) of the component 104, and the different changes in load state may be different in terms of magnitude and/or polarity, because the amplitude and/or length of the first and/or second signal 112 is based on a magnitude of a change in the load state of the component 104. In some examples, the polarity of the first and/or second signal 112 (e.g. relative to a reference voltage or current, or relative to OV/ground) may be based on the polarity/direction of the change in load state. In some examples, the length of the first square pulse is based on the magnitude of the first change in the load state of the component, and/or the length of the second square pulse is based on the magnitude of the second change in the load state of the component. Thus, for example, different pulse lengths can compensate for different anticipated changes in output voltage of the voltage regulator 102 due to different magnitudes in load step of the component 104.

For example, a change in load state may result in the component 104 drawing more or less power from the voltage regulator 102, and thus would cause a change in the output voltage of the voltage regulator (at least temporarily) if not compensated by the apparatus 106. In some examples, prior knowledge of when an upcoming load state change will occur, and its magnitude or the magnitude of the effect on the voltage regulator output, may be used to provide the first and second signals at the appropriate times to counteract the effect on the voltage regulator output.

Figure 2 shows an example of apparatus 200 for providing signals to a voltage regulator. The apparatus 200 may be for example the apparatus 106 shown in Figure 1 . The apparatus 200 comprises switch 202 (in this example, a transistor switch), resistor 204, resistor 206 and switch 208 (in this example, a transistor switch) arranged in series between a voltage Discharge_Voltage and 0V or ground. A node 210 between resistors 204 and 206 is connected via a capacitor 212 to ground, and also via a resistor 214 to a feedback node 216. In the example shown, the feedback node 216 is a node that is used by the voltage regulator to provide feedback regarding the regulator output voltage (Vout) and hence regulate the output voltage. Thus, the node 216 is also a node between resistors 218 and 220 that are arranged in series between Vout and ground. The resistors and node 216 may in some examples be part of the voltage regulator, and hence in some examples may not be included in the apparatus 200 for providing signals to a voltage regulator. Thus, the apparatus 200 may provide a signal to the feedback node 216 of the voltage regulator through resistor 214. In the example shown, the apparatus comprises a resistor-capacitor (RC) network configured to generate the first signal and/or the second signal, as well as the switches 202 and 208.

Switch 202 is controlled by a signal GPIO_NEG, whereas switch 208 is controlled by a signal GPIO_POS. Switch 202 may be controlled by the GPIO_NEG signal to charge the RC network including capacitor 212 towards Discharge_Voltage, and may be switched off to discharge the RC network. Similarly, switch 208 may be controlled by the GPIO_NEG signal to charge the RC network including capacitor 212 towards 0V or ground, and may be switched off to discharge the RC network. These actions provide the first and second signals to the node 216 and hence to the voltage regulator.

Figure 3 illustrates examples of signals 300 associated with the apparatus 200 shown in Figure 2. The signals 300 include signals 302 (e.g. voltage signals) that control the switches 202 and 208 shown in Figure 2. In particular, the signals 302 include a first square pulse 304 for GPIO_POS controlling switch 208, and a second square pulse 306 for GPIO_NEG controlling switch 202. In each case, several pulses of different lengths are illustrated, though in the example shown the pulse amplitude is substantially the same for different pulse lengths. Also shown in Figure 3 are signals 308 that may be for example the first and second signals 112 provided to a voltage regulator to compensate for a change in load state of a component. The signals 308 show examples of the first and second signals provided by the apparatus (e.g. apparatus 106 or 200) as a result of the pulses 304 and 306.

More specifically, in the example shown, the signals 308 include first signals or pulses 310, which are generated by the apparatus 200 as a result of pulse 304 controlling switch 208 and increase in amplitude and length for a longer pulse 304. For example, the first square pulse 304 controls the first switch 202 to charge the RC network to cause the RC network to generate the first signal 310. This may occur for example by the first square pulse 304 controlling the first switch 202 to charge the RC network by connecting the RC network to a first voltage (Discharge_Voltage in this example).

Similarly, the signals 308 include second signals or pulses 312, which are generated by the apparatus 200 as a result of pulse 306 controlling switch 202 and increase in amplitude and length for a longer pulse 306. For example, the second square pulse 306 controls the second switch 208 to discharge the RC network to cause the RC network to generate the second signal 312. Each of the signal pulses 310 and 312 exponentially or asymptotically decays to a voltage after the end of each pulse 304 and 306 respectively. This may occur for example by the second square pulse 306 controlling the second switch 208 to discharge the RC network by connecting the RC network to a second voltage or ground.

In this way, a current pulse is provided to the node 216, and hence to a feedback voltage node of the voltage regulator. As a result, the feedback voltage of the voltage regulator may be influenced so as to influence the output voltage of the voltage regulator. For a change in load state of a component, which would otherwise cause an anticipated change in output voltage of the voltage regulator, a pulse length may be selected and timed appropriately so that the signal provided to the voltage regulator by the apparatus at least partially counteracts or compensates for the change in output voltage of the regulator that would otherwise occur without such compensation.

Thus, for example, the apparatus 106 or 200 may be configured to provide a first square pulse to the RC network to cause the RC network to generate the first signal, and to provide a second square pulse to the RC network to cause the RC network to generate the second signal. The length of the first square pulse may be based on the magnitude of the first change in the load state of the component, and/or the length of the second square pulse may be based on the magnitude of the second change in the load state of the component. Thus, the particular impact of the change in load state, which may vary between different changes in load state, may be effectively compensated in some examples.

It is noted that the two pulses 304 and 306 in this example cause the apparatus 106 or 200 to produce signals or pulses 310 and 312 respectively that are opposite in polarity. This is for example to counteract a change in load state in one direction, followed by a change in load state in the opposite direction. However, in other examples, changes in load state may occur in the same direction, and hence may result in pulses that have the same polarity, though they may have different amplitude and/or length depending on the respective magnitudes of the change in load state. Further, in other examples there may be additional pulses controlling either switch 202 and 208, and resulting pulses of either polarity provided to the voltage regulator, in response to additional changes in either direction of the load state.

In the example apparatus 200 shown in Figure 2, the resistances Rneg, Rpos and Rdis of resistors 204, 206 and 214 respectively may be chosen to determine maximum current that can be injected for negative and positive pulses respectively provided to the voltage regulator (and hence for example positive and negative load steps respectively). Where the capacitance of capacitor 212 is Cff, Rdis*Cff may be chosen to set the discharge time and Rpos*Cff and Rneg*Cff to set the charging time for positive and negative pulses respectively. In some examples, Rdis, Rpos, Rneg and Cff may be optimized for each voltage regulator and/or component to counteract the change in output voltage due to a change in load state of the component in an optimum way.

Referring back to the apparatus 106 or 200 shown in Figures 1 and 2, in some examples, the amplitude and/or length of the first signal (e.g. the first pulse 310 shown in Figure 3) is based on a change in power state of the component 104 from a first power state to a second power state, wherein the magnitude of the first change in the load state of the component is based on the change in the power state of the component from the first power state to the second power state. Thus, for example, a change in power state may result in the component 104 drawing more or less power from the voltage regulator 102, and thus would cause a change in the output voltage of the voltage regulator (at least temporarily) if not compensated. Similarly, in some examples, the amplitude and/or length of the second signal is based on a change in the power state of the component from the second power state to a third power state, wherein the magnitude of the second change in the load state of the component is based on the change in the power state of the component from the second power state to the third power state. In some examples, the third power state is the same as the first power state, though in other examples the power states may be any power states.

In some examples, the third load state is the same as the first load state. Thus, for example, the second change in load state may return the component to the initial load state. In such examples, the pulses or signals provided to the voltage regulator may for example appear similar to those shown in Figure 3, e.g. may have similar lengths and magnitudes but opposite polarities.

In some examples, the feedback voltage in the voltage regulator, e.g. at node 216 in Figure 2, may be compared to a reference voltage (e.g. a scaled or voltage divided output voltage of the regulator) to produce an error signal. Thus, in some examples, the first signal and the second signal (e.g. signals 310 and 312 shown in Figure 3) may cause a change in the error signal in the voltage regulator, wherein the error signal represents a difference between a reference voltage and a voltage representing the output voltage of the voltage regulator. Thus, the anticipated change in output voltage of the regulator may be counteracted, for example. Referring specifically to Figure 2 for illustrative purposes, the first signal 310 and the second signal 312 may in some examples be provided to the node 216 between resistors 218 and 220 of a voltage divider in the voltage regulator between the output voltage Vout and ground, wherein the error signal comprises a difference between a voltage at the node and a reference or ideal voltage.

Figure 4 illustrates another example of a circuit 400 comprising a voltage regulator 402, a component 404 and apparatus for providing a signal 408 to the voltage regulator 402. In the example shown in Figure 4, the voltage regulator 402 is a switched mode power supply (SMPS) and the component is a load 404, such as for example any of the example components referred to above. The apparatus for providing a signal 408 to the voltage regulator 402 is implemented within system control 406, which may also control the load or power state of the load 404, for example to increase or decrease its power consumption according to a time division duplex (TDD) transmission and/or reception scheme. Thus, for example, the load may be a transmitter or receiver that is unused and therefore powered down for some of the TDD cycle. As the system control 406 controls the load state of the load 404, it may also have prior knowledge of when the load state changes, and may therefore control the apparatus (e.g. by providing appropriate square pulse signals 304 and 306) to the apparatus to provide first and second signals to the SMPS 402 at appropriate times and of appropriate lengths based on the magnitude of change in load state or the magnitude of anticipated change in output voltage of the SMPS 402 if not compensated.

The SMPS includes a voltage conversion circuit 410 that receives an input voltage Vin and provides a regulated voltage output Vout 412 based on a signal 414 from a controller 416 in the SMPS 402. The controller receives a feedback voltage 418, which may be the output voltage Vout 412 or a voltage based on Vout (e.g. a voltage divided or scaled Vout). The signal 408 from system control 406 affects this feedback signal 418 or otherwise causes the controller to change the signal 414 to the voltage conversion circuit 410 to counteract any anticipated change in output voltage Vout 412 of the SMPS 402 as a result of a change in load state of the load 404.

Figure 5 is a flow chart of an example of a method 500 of providing signals to a voltage regulator, such as for example the voltage regulator 102 or the SMBS 402 referred to above. The method 500 comprises, in step 502, providing a first signal to the voltage regulator to cause the voltage regulator to counteract a first anticipated change in output voltage at an output of the voltage regulator due to a first change in load state of a component (e.g. component 104 or load 404) on the output of the voltage regulator from a first load state to a second load state, wherein the amplitude and/or length of the first signal is based on a magnitude of the first change in the load state of the component. The method 500 also comprises, in step 504, providing a second signal to the voltage regulator to counteract a second anticipated change in the output voltage at the output of the voltage regulator due to a second change in the load state of the component on the output of the voltage regulator from the second load state to a third load state, wherein the amplitude and/or length of the second signal is based on a magnitude of the second change in the load state of the component. In some examples, the method 500 is performed by apparatus, such as the apparatus 106 or 200 or the system control 406 referred to above. The component may be for example a determininstic load, signal processor, analog to digital converter (ADC), digital to analog converter (DAC), application specific integrated circuit (ASIC), field programmable grid array (FPGA), low noise amplifier (LNA), power amplifier, transmitter circuit, receiver circuit and/or transceiver circuit.

In some examples, the amplitude and/or length of the first signal is based on a change in power state of the component from a first power state to a second power state, wherein the magnitude of the first change in the load state of the component is based on the change in the power state of the component from the first power state to the second power state. Additionally or alternatively, in some examples, the amplitude and/or length of the second signal is based on a change in the power state of the component from the second power state to a third power state, wherein the magnitude of the second change in the load state of the component is based on the change in the power state of the component from the second power state to the third power state. The third may in some examples be the same as the first power state, and/or the third load state may be the same as the first load state.

The first signal may for example comprise a first exponentially or asymptotically decaying pulse, and/or the second signal may comprise a second exponentially or asymptotically decaying pulse. For example, a resistor-capacitor (RC) network is used to generate the first signal and/or the second signal, for example as shown in Figure 2. In such examples, the method 500 may comprise providing a first square pulse (e.g. pulse 304 shown in Figure 3) to the RC network to cause the RC network to generate the first signal, and/or providing a second square pulse (e.g. pulse 306 in Figure 3) to the RC network to cause the RC network to generate the second signal. The length of the first square pulse may in some examples be based on the magnitude of the first change in the load state of the component, and/or the length of the second square pulse is based on the magnitude of the second change in the load state of the component. In some examples, the first square pulse controls a first switch (e.g. switch 202) to charge the RC network to cause the RC network to generate the first signal (e.g. pulse signal 310 shown in Figure 3). Additionally or alternatively, in some examples, the second square pulse controls a second switch (e.g. switch 208) to discharge the RC network to cause the RC network to generate the second signal (e.g. pulse 312 shown in Figure 3). For example, the first square pulse controls the first switch to charge the RC network by connecting the RC network to a first voltage, and/or the second square pulse controls the second switch to discharge the RC network by connecting the RC network to a second voltage or ground.

It should be noted that the above-mentioned examples illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative examples without departing from the scope of the appended statements. The word “comprising” does not exclude the presence of elements or steps other than those listed in a claim, “a” or “an” does not exclude a plurality, and a single processor or other unit may fulfil the functions of several units recited in the statements below. Where the terms, “first”, “second” etc. are used they are to be understood merely as labels for the convenient identification of a particular feature. In particular, they are not to be interpreted as describing the first or the second feature of a plurality of such features (i.e. , the first or second of such features to occur in time or space) unless explicitly stated otherwise. Steps in the methods disclosed herein may be carried out in any order unless expressly otherwise stated. Any reference signs in the statements shall not be construed so as to limit their scope.