WITH MEMORY EFFECTS

RELATED APPLICATIONS

This application claims priority from US Provisional Patent App. No. 62/003,338 filed 27

May 2014, which is incorporated herein by reference in its entirety.

TECHNICAL FIELD

The present application generally relates to digital modulation schemes that have memory effects.

BACKGROUND

Bluetooth Low Energy (BLE) is a popular personal area network (PAN) technology thanks to its low cost and low energy consumption. BLE employs GFSK (Gaussian Frequency Shift Keying) modulation, which is a constant envelope modulation, advantageous in terms of power amplifier (PA) efficiency and low energy consumption. Furthermore, in consideration of achieving the low cost objective, no forward error correction (FEC) code is used. The information bits are therefore sent raw, without FEC coding, via the GFSK modulation. This is illustrated in Figure 1 , which shows a BLE device 10 as having a GFSK modulator 12 that receives information bits 14 as input and provides a GFSK signal 16 as output. No FEC coding is applied to these information bits 14. Due to lack of FEC protection, the information bits (also referred to as payload hereafter) may easily be received in error if the signal level drops, due to fading or increased distance between the transmitting device and receiving device. BLE uses cyclic redundancy check (CRC) bits to allow the receiver to check whether errors have occurred during the transmission.

In Bluetooth Special Interest Group (SIG), it is desirable that the range of BLE can be extended to support more use cases. A feature, namely, BLE Long Range is being developed in the SIG. Extending the range of BLE while at the same time achieving the low cost objective of BLE proves challenging, though.

SUMMARY

One or more embodiments herein exploit the memory effects inherent to some digital modulation schemes (independent of any inter-symbol interference) as the inner code of a serially concatenated coding system. Moreover, according to at least some of these

embodiments, the serially concatenated coding system's outer code is memoryless and the system's interleaver is recursively addressed. Such a serially concatenated coding system means that the transmitted information may be recovered via an iterative turbo processing receiver, e.g., that employs a memoryless outer code decoder and recursively addressed interleaver/de-interleaver. With the modulation scheme's memory effect used as the inner code, and especially with the outer code being memoryless and the interleaver/de-interleaver being recursively addressed, the embodiments advantageously improve the transmission reliability of the digital modulation scheme while at the same time achieving low complexity and cost.

That is, one or more embodiments herein include methods for improving the

transmission reliability of digital modulation schemes that exhibit memory effects. One or more embodiments, for example, improve the transmission reliability of GFSK used by BLE. In doing so, the embodiments prove particularly advantageous for extending the range of BLE while at the same time achieving the low cost objective of BLE. Indeed, the modulation memory effect is exploited to form a robust transmission scheme which is resilient to noise, interference, fading, and additional path loss.

One embodiment, for example, includes a transmitting node configured to transmit a sequence of information bits using a serially concatenated coding system. The transmitting node is configured to outer encode information bits in the sequence by encoding any given information bit independently of any other information bits in the sequence. The transmitting node is also configured to interleave the outer coded bits using a recursively addressed interleaver, wherein said interleaving includes computing any given output address of the interleaver from one or more previously computed output addresses. The transmitting node is further configured to digitally modulate the interleaved bits in order to generate modulation symbols, wherein said digitally modulating comprises generating a modulated symbol for a current symbol period in dependence on a modulated symbol for a previous symbol period.

The transmitting node in one or more embodiments for example comprises means adapted to outer encode the information bits in the sequence, interleave the outer coded bits, and digitally modulate the interleaved bits as described above.

In one or more embodiments, the sequence of information bits is transmitted according to Bluetooth Low Energy, BLE.

Additionally or alternatively, the digital modulation in one or more embodiments comprises Gaussian Frequency Shift Keying, GFSK, modulation.

In at least some embodiments, the transmitting node is configured to transmit the sequence without precoding the sequence so as to preserve the memory effects of the digital modulation.

In one or more embodiments, the transmitting node is configured to outer encode the information bits employing a mapping code that maps different information bits to different codewords, each represented by a sequence of encoded bits. In one embodiment, for example, this repetition code is an irregular repetition code that repeats different information bits a different number of times.

In one or more other embodiments, the transmitting node is configured to outer encode the information bits employing a Manchester code.

In still one or more other embodiments, the transmitting node is configured to outer encode the information bits employing a nonbinary code. One or more embodiments herein include a method for transmitting a sequence of information bits using a serially concatenated coding system. The method comprises outer encoding of information bits in the sequence by encoding any given information bit

independently of any other information bits in the sequence. The method further comprises interleaving the outer coded bits using a recursively addressed interleaver. The interleaving includes computing any given output address of the interleaver from one or more previously computed output addresses. The method further comprises digitally modulating the interleaved bits in order to generate modulation symbols. The digitally modulating (130) comprises generating a modulated symbol for a current symbol period in dependence on a modulated symbol for a previous symbol period.

One or more other embodiments herein include a receiving node configured to iteratively process a received sequence of symbols that has been transmitted using a serially

concatenated coding system. The receiving node in this regard is configured, for each of one or more iterations, to demodulate symbols in the sequence in order to generate demodulator output soft values, by demodulating a current symbol in the sequence in dependence on the previous symbol in the sequence and based on any interleaved extrinsic information obtained during a previous iteration of processing the current symbol. The receiving node is also configured to de-interleave the demodulator output soft values using a recursively addressed de-interleaver in order to obtain soft values for outer coded bits represented by the sequence, wherein said de-interleaving includes computing any given output address of the de-interleaver from one or more previously computed output addresses. The receiving node is further configured to outer decode each outer coded bit independently of any other outer coded bit using the soft values for that outer coded bit, in order to generate one or more soft values for a corresponding information bit. The receiving node is moreover configured to generate extrinsic information for each outer coded bit based on the one or more soft values for the corresponding information bit and the soft values for that outer coded bit. Finally, the receiving node is configured to interleave the extrinsic information in order to obtain said interleaved extrinsic information.

The receiving node in one or more embodiments for example comprises means adapted to demodulate the symbols in the sequence, de-interleave the demodulator output soft values, outer decode each outer coded bit, generate extrinsic information, and interleave that extrinsic information as described above.

In one or more embodiments, the receiving node is configured to demodulate the symbols by rotating a current symbol in the sequence to have the same phase as the previous symbol in the sequence.

Additionally or alternatively, the receiving node is configured to demodulate the symbols by generating a reduced-state state transition diagram that has different states for different respective ones of a subset of nominally possible phases according to the modulation scheme, by rotating symbols that have phases excluded from said subset to have phases included in that subset. In one embodiment, for example, the reduced-state state transition diagram comprises a memory-1 trellis. In this or other examples, such rotating comprises effectively converting Gaussian Frequency Shift Keying, GFSK, demodulation to differential Binary Phase Shift Keying, BPSK, demodulation.

In at least some embodiments, the sequence is received according to Bluetooth Low Energy, BLE.

In one or more embodiments, the digital demodulation comprises Gaussian Frequency Shift Keying, GFSK, demodulation.

In still other embodimetns, the sequence is transmitted without precoding the sequence so as to preserve the memory effects of the digital modulation.

Additionally or alternatively, the receiving node is configured to outer decode by employing a mapping code that maps different codewords to different information bits, wherein each codeword is represented by a sequence of encoded bits.

In at least some embodiments, the outer decoding employs a repetition code. In one example, the repetition code is an irregular repetition code that repeats different information bits a different number of times.

In other embodiments, the outer decoding employs a Manchester code. In still other embodiments, the outer decoding employs a nonbinary code.

One or more embodiments herein include a method for iteratively processing a received sequence of symbols that has been transmitted using a serially concatenated coding system. The method is characterized by, for each of one or more iterations, demodulating symbols in the sequence in order to generate demodulator output soft values, by demodulating a current symbol in the sequence in dependence on the previous symbol in the sequence and based on any interleaved extrinsic information obtained during a previous iteration of processing the current symbol. The method is further characterized by, for each of one or more iterations, de- interleaving the demodulator output soft values using a recursively addressed de-interleaver in order to obtain soft values for outer coded bits represented by the sequence. The de- interleaving includes computing any given output address of the de-interleaver from one or more previously computed output addresses. The method is further characterized by, for each of one or more iterations, outer decoding each outer coded bit independently of any other outer coded bit using the soft values for that outer coded bit, in order to generate one or more soft values for a corresponding information bit. The method is further characterized by, for each of one or more iterations, generating extrinsic information for each outer coded bit based on the one or more soft values for the corresponding information bit and the soft values for that outer coded bit, and interleaving the extrinsic information in order to obtain said interleaved extrinsic information .

Embodiments herein also include corresponding methods, computer programs, and computer program products. BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 is a block diagram of a Bluetooth Low Energy (BLE) device according to known approaches.

Figure 2 is a block diagram of a serially concatenated coding system in a transmitting node according to one or more embodiments.

Figure 3 is a block diagram of an iterative processing receiver in a receiving node according to one or more embodiments.

Figure 4 is a block diagram of a BLE transmission scheme according to one or more embodiments.

Figure 5 is a block diagram of a serially concatenated coding system in a transmitting node according to one or more embodiments that employ GFSK modulation as an inner code.

Figure 6 is a block diagram of an iterative turbo processing receiver in a receiving node according to one or more embodiments that employ GFSK modulation as an inner code.

Figure 7 is a block diagram of demodulation operations by the iterative turbo processing receiver of Figure 6 according to one or more embodiments.

Figure 8 is a state transition diagram that is biased by the iterative turbo processing receiver of Figure 6 according to one or more embodiments.

Figure 9 is a block diagram of a serially concatenated coding system in a transmitting node according to one or more embodiments that employs a recursively addressed interleaver and/or a memoryless outer code encoder.

Figure 10 is a block diagram of an iterative processing receiver in a receiving node according to one or more embodiments that employs a recursively addressed de-interleaver and interleaver and/or a memoryless outer code decoder.

Figure 1 1 is a logic flow diagram of a method performed by a transmitting node according to one or more embodiments.

Figure 12 is a logic flow diagram of a method performed by a receiving node according to one or more embodiments.

Figure 13 is a block diagram of a transmitting node according to one or more

embodiments.

Figure 14 is a block diagram of a transmitting node's functional units according to one or more embodiments.

Figure 15 is a block diagram of a computer program according to one or more

embodiments.

Figure 16 is a block diagram of a receiving node according to one or more embodiments.

Figure 17 is a block diagram of a receiving node's functional units according to one or more embodiments. Figure 18 is a block diagram of a computer program according to one or more other embodiments.

DETAILED DESCRIPTION

One or more embodiments herein recognize that the memory effects inherent to some digital modulation schemes (independent of any inter-symbol interference) resemble the memory effects inherent to convolutional codes. Rather than employing convolutional codes as both the outer and inner codes of a serially concatenated coding system before modulation, as is conventional, the one or more embodiments exploit the memory effects inherent to a digital modulation scheme (e.g., GFSK, GMSK, DPSK, etc.) as the inner code of a serially

concatenated coding system. With a modulation scheme's memory effect effectively used as the inner code, the embodiments advantageously improve the transmission reliability of the digital modulation scheme, e.g., in a cost-effective way. Figure 2 illustrates one example of the serially concatenated coding system 20 according to some of these embodiments.

As shown in Figure 2, the serially concatenated coding system 20 implemented by a transmitting node 18 includes an outer code encoder 22, an interleaver 24, and a digital modulator 26 that effectively operates as the system's inner code encoder. The digital modulator 26 implements a digital modulation scheme that exhibits memory effects. As used herein, this means that the digital modulator 26 generates a modulated symbol for the current symbol period in dependence on a modulated symbol for the previous symbol period. That is, the modulated symbol for the previous symbol period has an effect on the modulated symbol for the current symbol period. A digital modulator 26 that implements a digital modulation scheme which exhibits memory effects will be referred to herein as a "memory effect modulator" 26 for convenience.

According to Figure 2, therefore, the transmitting node 18 is configured to transmit a sequence of information bits 28 using the serially concatenated coding system, e.g., according to Bluetooth Low Energy (BLE). The outer code encoder 22 is configured to outer encode information bits 28 in the sequence. The interleaver 24 is configured to interleave the resulting outer coded bits 30. And the memory effect modulator 26 is configured to digitally modulate the interleaved bits 32 in order to generate modulation symbols 34. In doing so, the modulator 26 generates a modulated symbol for a current symbol period in dependence on a modulated symbol for a previous symbol period.

Note that in at least some embodiments the transmitting node 18 transmits the sequence of information bits 28 in this way without precoding the sequence. The transmitting node 18 refrains from such precoding so as to preserve the memory effects of the digital modulation. In contrast to GSM for instance that employs precoding at the transmitter 18 in order to remove the differential nature of the digital modulation (i.e., in order to remove the modulation memory), one or more embodiments herein refrain from such precoding. Regardless, with the transmitting node 18 transmitting information bits 28 with the coding system 20 described above, the corresponding receiving node 36 recovers those information bits via an iterative (i.e., turbo) processing approach. As shown in Figure 3, the receiving node 36 includes an iterative processing receiver 38. This receiver 38 includes a memory effect demodulator 40, a de-interleaver 42, an outer code decoder 44, and an interleaver 46. The memory effect demodulator 40 demodulates the symbols in the received signal 48 according to a digital modulation scheme that exhibits memory effects. The memory effect demodulator 40 is effectively exploited as the inner code decoder of the iterative processing receiver 38.

According to Figure 3, therefore, the receiving node 36 is configured to iteratively process a received sequence of symbols (shown as the "received signal") 48 that has been transmitted using a serially concatenated coding system. The memory effect demodulator 40 is configured to demodulate symbols in the sequence in order to generate demodulator output soft values 50 (i.e., soft values for interleaved bits represented by the sequence). In doing so, the demodulator 40 demodulates a current symbol in the sequence in dependence on the previous symbol in the sequence and based on any interleaved extrinsic information 52 obtained during a previous iteration of processing the current symbol. The de-interleaver 42 is configured to de-interleave the demodulator output soft values 50 in order to obtain soft values 54 for outer coded bits represented by the sequence. The outer code decoder 44 is configured to outer decode each outer coded bit (based on the coded bit soft values) in order to generate one or more soft values 56 for a corresponding information bit. The outer code decoder 44 also generates extrinsic information 58 for each outer coded bit . In at least some embodiments, for example, the outer code decoder 44 does so based on the one or more soft values for the corresponding information bit and the soft values for that outer coded bit. Regardless, the interleaver 46 then interleaves this extrinsic information 58 in order to provide that interleaved extrinsic information 52 to the memory effect demodulator 40 for use in the demodulator's next iteration of processing the current symbol.

In at least some embodiments, the sequence of information bits is modulated in such a way that the phase and/or amplitude in the current symbol period t{k) are determined by (i) data bit (or bits) in the current symbol period; and (ii) phase and/or amplitude in the previous symbol period t{k - 1) . In other words, the phase and/or amplitude changes from the previous symbol period to the current symbol period are determined by (i) data bit (or bits) in the current symbol period; and (ii) phase and/or amplitude in the previous symbol period. Such digital modulation schemes exhibit memory effect since the phase and/or amplitude in the previous symbol period has an effect on the phase and/or amplitude in the current symbol period.

In one or more embodiments, the demodulator 40 undoes or otherwise removes the memory effects (e.g., differential modulation aspect) of the modulation scheme for one or more received symbols during symbol processing. In some embodiments that use a modulation scheme with phase-based memory effects, for example, the demodulator 40 may rotate a current symbol in the sequence to have the same phase as the previous symbol in the sequence (so as to remove the phase change or differential associated with those successive symbols).

In one such embodiment, this rotation is performed as part of a larger process to generate a reduced-state state transition diagram, such as a memory-1 trellis, e.g., for generating soft values. The diagram in this regard has different states for different respective ones of a subset of nominally possible phases according to the modulation scheme. That is, the number of states is reduced as compared to the number of states that are nominally possible according to the modulation scheme. To generate such a reduced-state diagram, the demodulator 40 rotates symbols that have phases excluded from the subset to have phases included in that subset (based on the memory effect of the modulation scheme). The

demodulator 40 thereby effectively reduces the number of states in the diagram by removing the impact that the modulation scheme's memory effect has on at least some symbols.

Consider a simple example in the context of one or more embodiments that employ Gaussian Frequency Shift Keying (GFSK) modulation, e.g., as used in Bluetooth Low Energy (BLE). The transmission scheme according to BLE is illustrated in Figure 1 . Information bits (i.e., information blocks that comprise only a single bit) are converted to modulated symbols using GFSK modulation. The GFSK modulation used in BLE uses a modulation index h=1 /2, which gives a phase change of π 1 2 when the bit input to the modulator has value 0, and a phase change of -π 12 when the bit input to the modulator has value 1 . This is illustrated in

Figure 4. As shown, the phase of the modulated symbol at symbol period k-1 is represented by point A in the l-Q diagram. When the bit input b(k) to the modulator in the next symbol period s(k) has value 0, a phase change of π 1 2 brings the modulated symbol to point B. However, if the bit input b(k) to the modulator in the next symbol period s(k) has value 1 , a phase change of -π 12 brings the modulated symbol to point C. Regardless, the modulated symbol s(k) in symbol period k is determined by the modulated symbol s(k - l) in symbol period k-1 and the bit input b(k) to the modulator in symbol period k. Since the modulated symbol s(k) depends on the symbol s(k - l) in the previous symbol period, a modulation scheme like GFSK is referred to herein as a digital modulation with memory effect.

Figure 5 illustrates one embodiment in which a serially concatenated coding system 60 utilizes the GFSK modulation as the inner code. As shown, the system 60 in this regard includes a GFSK modulator 62 as the memory effect modulator. The GFSK modulator generates modulation symbols 64 from interleaved bits 32 using GFSK modulation.

Such a serially concatenated coding system 60 allows the receiving node 36 to recover the transmitted information bits via an iterative turbo processing receiver 66. A turbo processing receiver 66 for recovering the information bits encoded via a serially concatenated coding system 60 as shown in Fig. 5 is illustrated in Figure 6. The received signal 48 is processed first using a GFSK demodulator 68. According to one or more embodiments, the GFSK demodulator 68 generates demodulated soft values 70 utilizing the memory effect and modulation properties. For example, for GFSK with modulation index h=1 /2, the demodulator 68 may rotate the received symbol by -π 12 to bring the modulated symbol to point A or point D as illustrated in Figure 7. Thus, if b(k) = 0 the received symbol will be rotated to the location of point A, whereas if b(k) = 1 the received symbol will be rotated to the location of point D. According to one or more embodiments, after the -π 12 rotation, the demodulator 68 forms soft values of b(k) according to the state transition diagram shown in Figure 8. As shown, state A (or state D) stays at the same state if b(k) = 0. However, if b(k) = 1 , a change of demodulation internal state occurs. The state transition diagram in Figure 8 is used to capture the modulation memory effect. In this case, GFSK is modeled as a memory-1 state machine or trellis. Effectively, the demodulator's rotations convert GFSK demodulation to differential BPSK demodulation. In general, the number of states needed in the state transition diagram is Q ^A M, where Q is the size of the modulation alphabet size and Q is the memory length. For GFSK, Q=2, since with proper rotation, the received symbols in the absent of noise and impairment can be approximately represented by two points as shown in Figure 7.

The demodulated soft values 70 are deinterleaved before being utilized by the outer code decoder 44. The outer code decoder 44 uses the input soft values 54 to obtain an estimation of each of the information bits 56. According to some embodiments, each of the decoder input soft values 54 corresponds to one encoded bit generated by the outer code encoder. According to the turbo processing principle, the outer code decoder 44 needs to generate a soft value for each of the encoded bits. Such a soft value is often referred to as the extrinsic information 58 in turbo decoding literature. The extrinsic information 58 is fed back to the demodulator 68 after interleaving.

In the subsequent iterations, the demodulator 68 utilizes the interleaved extrinsic information 52 as the a prioi information in the demodulation process. The a prioi information is used to bias the transition in the state transition diagram shown in Figure 8. For example, if the a priori information indicates that b(k) is more likely to be 0 than 1 , the solid line transitions

(corresponding to b(k) = 0 ) in Figure 8 will be weighted higher than the dashed line transitions. Furthermore, in the subsequent iterations, the a prioi information 52 input to the demodulator 68 needs to be subtracted from the a posteriori information about each encoded bit as computed by the GFSK demodulator 68.

In view of the above modifications and variations, therefore, according to one or more embodiments the receiver 66 (i) formulates log-likelihood ratios, or soft values, based on the received signal 48, the memory effect of the modulation, and the a priori information 52 of the encoded bits (ii) deinterleaves the demodulator output soft values 70, (iii) computes a posterior information and extrinsic information 58 for each encoded bit based on the deinterleaved demodulator output soft values 54, and (iv) interleaves the computed extrinsic information 52 of the encoded bits. This completes the first turbo processing iteration. In each of the subsequent iterations, steps (i)-(iv) are exactly the same. In the very first turbo processing iteration, the a priori information for the encoded bits is not available, and as a result the a priori information for each encoded bit can be set to zero, indicating each encoded bit is equal likely to be 0 or 1 . In the subsequent iteration, the a priori information for each encoded bit is taken from the extrinsic information 52 generated in step (iv) in the previous iteration.

In at least some embodiments, any type of outer code and/or any type of interleaver 24 or de-interleaver 42 may be used. In other embodiments, though, such as those shown in Figures 9 and 10, a particular type of outer code and/or a particular type of interleaver/de- interleaver is used that achieves low complexity and cost.

In this regard, Figure 9 shows that the outer code encoder 22 according to some embodiments is memoryless in nature (unlike a convolutional code), so as to constitute a memoryless outer code encoder 74. This means that the encoder 74 encodes any given information bit 28 independently of any other information bit 28 in the sequence, so as to produce out coded information bits 76. Encoding of a current information bit b(k) , for instance, does not depend in any way on one or more previous information bits b(k - l), b(k - 2), ... in the sequence. In fact, in some embodiments, the encoder 74 encodes a current information bit b(k) independently of any other information bits. The outer code in this regard can also be described as a mapping code, whereby different information bits 28 are simply mapped to different codewords, each represented by a sequence of encoded bits. According to one or more embodiments, for example, the outer code is to simply map an information bit x(k) = 0 to a sequence m ₀ and map an information bit x(k) = 1 to a sequence m ₁ . Such a simple outer code facilitates low-complexity decoding operation at the receiver 38.

Figure 9 also shows that, in one or more embodiments, the interleaver 24 is recursively addressed so as to constitute a recursively addressed interleaver 80 that outputs recursively addressed interleaved bits 82. This means that any given output address of the interleaver 80 is computed from one or more previously computed output addresses. The output address a i + 1) for instance is computed recursively from the output address a i) . In other words, the interleaver 80 is a special class of interleavers which allows recursively computing addresses in the interleaving process.

Figure 10 shows the receiver 84 counterpart to Figure 9 as including a memoryless outer code decoder 86 and a recursively addressed interleaver 88 and de-interleaver 90. The recursively addressed de-interleaver 90 and interleaver 88 each compute any given output address from one or more previously computed output addresses. The memoryless outer code decoder 86 decodes each outer coded bit independently of any other outer coded bit using the de-interleaved soft values 92 for that outer coded bit, in order to produce information bit soft values 94. The decoder 86 also produces extrinsic information 96 in an analogous manner as described bove.

A memoryless outer code and recursively addressed interleaving, combined with exploitation of the modulation's memory effect, facilitate simple and effective turbo processing at the receiver 84. The interleaving pattern, for example, facilitates simple interleaving and deinterleaving operations without giving up much performance potential.

Figures 1 1 and 12 illustrate corresponding processing performed by the transmitting node 18 and the receiving node 36 in accordance with one or more embodiments described above. As shown in Figure 1 1 , processing 100 at the transmitting node 18 is performed for transmitting a sequence of information bits using a serially concatenated coding system. The processing 100 involves outer encoding information bits in the sequence by encoding any given information bit independently of any other information bits in the sequence (Block 1 10).

Processing 100 further entails interleaving the outer coded bits using a recursively addressed interleaver (Block 120). Such interleaving includes computing any given output address of the interleaver from one or more previously computed output addresses. Processing 100 further includes digitally modulating the interleaved bits in order to generate modulation symbols (Block 130). This digitally modulation comprises generating a modulated symbol for a current symbol period in dependence on a modulated symbol for a previous symbol period.

As shown in Figure 12, processing 200 at the receiving node 36 is performed for iteratively processing a received sequence of symbols that has been transmitted using a serially concatenated coding system. The processing 200 is performed for one or more iterations. For each iteration, the processing 200 entails demodulating symbols in the sequence in order to generate demodulator output soft values, by demodulating a current symbol in the sequence in dependence on the previous symbol in the sequence and based on any interleaved extrinsic information obtained during a previous iteration of processing the current symbol (Block 210). For the current iteration, the processing 200 also includes de-interleaving the demodulator output soft values using a recursively addressed de-interleaver in order to obtain soft values for outer coded bits represented by the sequence (Block 220). Such de-interleaving includes computing any given output address of the de-interleaver from one or more previously computed output addresses. For the current iteration, the processing 200 further comprises outer decoding each outer coded bit independently of any other outer coded bit using the soft values for that outer coded bit, in order to generate one or more soft values for a corresponding information bit (Block 230). For the current iteration, the processing 200 also includes generating extrinsic information for each outer coded bit based on the one or more soft values for the corresponding information bit and the soft values for that outer coded bit (Block 240). Finally, for the current iteration, the processing 200 includes interleaving the extrinsic information in order to obtain the interleaved extrinsic information (i.e., for that current iteration) (Block 250). In at least some embodiments, the outer code is a repetition code. As used herein, a repetition code represents an information bit with a pattern of one or more code bits that repeat. In some embodiments, this repeating pattern is formed from a single code bit that repeats, meaning that the same code bit is repeated throughout the code. For example, such a "single- bit" repetition code may represent an information bit Ί ' with a single code bit Ί ' that repeats to form a code of Ί 1 1 1 1 1 ', and represent an information bit '0' with a single code bit '0' that repeats to form a code of '000000' (or vice versa). When the single repeating code bit has the same value as the information bit, the repetition code effectively repeats the information bit. In other embodiments, by contrast, the repeating pattern is formed from multiple different code bits that repeat. For example, such a "multi-bit" repetition code may represent an information bit Ί ' with a code bit pattern ' 10' that repeats to form a code of '101010', and represent an information bit '0' with a different code bit pattern '01 ' that repeats to form a code of '0101010'. In at least some embodiments, the repetition code represents different information bits with code bit patterns that are bit-wise complementary.

In more detail, a "single-bit" repetition code that effectively repeats the information bit may be regular or uniform in the sense that it repeats each information bit the same number of times. For example, in some embodiments the repetition code repeats each information bit 4 times (i.e., the repetition code has a regular or uniform repetition factor of L=4). Where the outer code simply maps an individual information bit x(k)=0 to a sequence m ₀ and maps an individual information bit x(k)=1 to a sequence m ₁ , for example, m ₀ = (0, 0, 0, 0) ^T and m ₁ = (1, 1, 1, 1) ^T . With a repetition factor of 4, the signal-to-noise ratio (SNR) required for achieving 0.1 % information bit error rate (BER) is improved by 14.5 dB. This translates to significant range improvement. Other repetition factors may of course be used.

The decoding operation for such a regular "single-bit" repetition code involves simply summing up the encoded bit soft values:

L-1

L _x (.k) =∑L _b (.k, l) ,

1=0

where k is the index of information bit and L _b (k, l) is the encoded bit soft value corresponding to the Ith repetition of information bit x{k) . The information bit soft value L _x {k) is used for determining whether information bit x{k) is 0 or 1 . If L _x {k) > 0 x{k) = 0 , otherwise x{k) = 1. If the iterative turbo processing is to continue to the next stage, extrinsic information for encoded bit b(k, l) is needed to be fed back to the demodulator as the a priori information. Such extrinsic information is computed in some embodiments as L _{b e} (k, l) = L _x (k) - L _b (k, l) .

In one or more other embodiments, by contrast, a "single-bit" repetition code that repeats each information bit is irregular or non-uniform in the sense that it repeats different information bits a different number of times. That is, the repetition code has different repetition factors for different individual information bits. Accordingly, different repetition factors L _k are used for different information bits x(k) in the equations above.

In still other embodiments, though, any arbitrary (L,1 ) code is used as the outer code. Here, the notion of (L,1 ) code means that every information bit is mapped to a length-L codeword. This allows the code to be a linear code or a non-linear code. A linear code can be represented by m _x = Gx , where x is the information bit (taking value 0 or 1 ), and G is a so-called generator matrix. The repetition code described previously in an example is a linear code, e.g., with G = (1,1, 1,1) ^T .

A nonlinear code cannot be generated using a generator matrix. However, regardless of whether the outer code is a linear or nonlinear code, a codeword representing information bit x - i, i = 0, or 1 , can be expressed as m _; = (m _; (0),m _; (l), ...m _; (L - l)) ^T . Each encoded bit m _; (l) e {0, 1} . The decoding operation is as simple as the repetition code,

L-1

L _x (k) = ^ L _¾ (^, /) (m ₁ (/) -m ₀ (/)) . The extrinsic information 58 from the decoder 44 is

1=0

obtained in one or more embodiments by: L _{b e} (k,l) = L _JC (^) (m ₁ (/) -m ₀ (/)) - L _¾ (^,/) .

Arbitrary (L,1 ) codes cover a wide range of codes. For example, a Manchester code (e.g., of length 4) may include m ₀ = (0,0,1, l) ^T ,m ₁ = (1,1,0,0) ^T . As a second example, the outer code may be m ₀ = (0,0, l,l, l,l,0,0) ^T ,m ₁ = (1, 1, 0, 0,0,0, 1,1) ^T . These two examples also reflect code that represent different information bits with codes that are bit-wise complementary. In any event, as a third example, the code may be m ₀ = (l,0,0,0,l,l, l,0) ^T ,m ₁ = (0, 0, 0, 0, 1,1, 1,1) ^T .

Alternatively or additionally, the outer code is a nonbinary code. In this case, each coded bit (or more correctly speaking "symbol") m _; (/) takes values from an alphabet A and the size of A is greater than 2. Where the digital modulation memory effect involves phase changes, for instance, each letter in the alphabet A is mapped to a phase change of the digital modulation.

Although GFSK has been used as an example to describe one or more embodiments, embodiments herein however apply generally to any digital modulation with memory effect. Modulations such as Gaussian Frequency Shift Keying (GFSK) and Gaussian Minimum Shift Keying (GMSK), Differential Phase Shift Keying (DPSK), etc., all have memory effects. GFSK is used in BLE devices. GMSK is used in GSM/EDGE radio base station nodes and user terminals.

In view of the above modifications and variations, those skilled in the art will appreciate that embodiments herein include a transmitting node 18 configured to operate as described above, such as by performing the processing in Figure 1 1 . Although the transmitting node 18 in some embodiments comprises any functional means or units for such operation, Figure 13 illustrates one example transmitting node 18 configured according to one or more embodiments herein.

The transmitting node 18 comprises transceiver circuits 300 for communicating over an air interface with a receiving node 36 in a wireless communication network, processing circuits 310 for performing processing described herein, and memory 320 for storing program code and data needed for operation. The transceiver circuits 300 may, for example, comprise transmitter circuits and receiver circuits that operate according to the BLE standard or other known standard. The processing circuits 310 may comprise one or more processors, hardware circuits, firmware, or a combination thereof. Memory 320 may comprise one or more volatile and/or non-volatile memory devices. Program code for controlling operation of the transmitting node 18 is stored in a non-volatile memory, such as a read-only memory or flash memory. Temporary data generated during operation may be stored in random access memory. The program code stored in memory 320, when executed by the processing circuits 310, causes the processing circuits 310 to perform the methods shown above.

Where the processing circuits 310 comprise a processor, for instance, the transmitting node 18 may comprise a processor and a memory, where the memory contains instructions executable by the processor whereby the transmitting node 18 is configured to perform the processing described above (e.g., in Figure 1 1 ).

Figure 14 illustrates the transmitting node's main functional components (e.g., of the processing circuit(s) 310) according to one exemplary embodiment. The functional components include an outer code encoding unit 400, an interleaver unit 410, and a memory effect modulation unit 420. In one embodiment, these units 400, 410, 420 each comprise a programmable circuit that is configured by program code stored in memory to perform their respective functions. In other embodiments, one or more of the functional components may be implemented, in whole or in part, by hardware circuits. Regardless, the units 400, 410, 420 function as respectively described above for outer encoding, interleaving, and modulating.

Embodiments herein also include a computer program, comprising instructions which, when executed on at least one processor, cause the at least one processor to carry out the processing described above (e.g., in Figure 1 1 ). Embodiments further include a carrier containing this computer program, wherein the carrier is one of an electronic signal, optical signal, radio signal, or computer readable storage medium.

Figure 15 in this regard illustrates a computer program 500 (e.g., as stored in a computer readable storage medium accessible to the transmitting node 18) that includes program code according to one exemplary embodiment. The computer program includes a code module for outer code encoding 510, a code module for interleaving 520, and a code module for memory effect modulation 530. Those skilled in the art will appreciate that embodiments herein include a receiving node 36 configured to operate as described above, such as by performing the processing in Figure 12.

Although the receiving node 36 in some embodiments comprises any functional means or units for such operation, Figure 16 illustrates one example receiving node 36 configured according to one or more embodiments herein.

The receiving node 36 comprises transceiver circuits 600 for communicating over an air interface with a transmitting node 18 in a wireless communication network, processing circuits 610 for performing processing described herein, and memory 620 for storing program code and data needed for operation. The transceiver circuits 600 may, for example, comprise transmitter circuits and receiver circuits that operate according to the BLE standard or other known standard. The processing circuits 610 may comprise one or more processors, hardware circuits, firmware, or a combination thereof. Memory 620 may comprise one or more volatile and/or non-volatile memory devices. Program code for controlling operation of the receiving node 36 is stored in a non-volatile memory, such as a read-only memory or flash memory. Temporary data generated during operation may be stored in random access memory. The program code stored in memory, when executed by the processing circuits 610, causes the processing circuits 610 to perform the methods shown above.

Where the processing circuits 610 comprises a processor, for instance, the receiving node may comprise a processor and a memory, where the memory contains instructions executable by the processor whereby the receiving node 36 is configured to perform the processing described above (e.g., in Figure 12).

Figure 17 illustrates the main functional components (e.g., of the processing circuit(s) 610) according to one exemplary embodiment. The functional components include a memory effect demodulation unit 700, a de-interleaving unit 710, an outer code decoding unit 720, and an interleaving unit 730. In one embodiment, these units 700-730 each comprise a

programmable circuit that is configured by program code stored in memory to perform their respective functions. In other embodiments, one or more of the functional components 700-730 may be implemented, in whole or in part, by hardware circuits. Regardless, the units function as respectively described above for demodulation, de-interleaving, outer code decoding, and interleaving.

Embodiments herein also include a computer program, comprising instructions which, when executed on at least one processor, cause the at least one processor to carry out the processing described above (e.g., in Figure 12). Embodiments further include a carrier containing this computer program, wherein the carrier is one of an electronic signal, optical signal, radio signal, or computer readable storage medium.

Figure 18 in this regard illustrates a computer program 800 (e.g., as stored in a computer readable storage medium accessible to the receiving node) that includes program code according to one exemplary embodiment. The computer program includes a code module for demodulation 810, a code module for de-interleaving 820, a code module for outer code decoding 830, and a code module for interleaving 840.

Although described above with respect to individual information bits, at least some embodiments herein apply to information blocks that each comprise multiple information bits. In this case, processing at the transmitting node involves outer encoding information blocks in the sequence by encoding any given information block independently of any other information blocks in the sequence. Processing also includes interleaving the outer coded blocks using a recursively addressed interleaver, and digitally modulating the interleaved blocks. Embodiments herein also include corresponding processing at the receiving node.

The present invention may, of course, be carried out in other ways than those specifically set forth herein without departing from essential characteristics of the invention. The present embodiments are to be considered in all respects as illustrative and not restrictive, and all changes coming within the meaning and equivalency range of the appended claims are intended to be embraced therein.