GOVERNMENT FUNDING

[0001] Research leading to various aspects of the present invention were sponsored, at least in part, by the U.S. Air Force Office of Scientific Research, Grant No. FA9550-13-1- 0028. The U.S. Government may have certain rights in the invention.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit under 35 U.S.C. § 119(e) of U.S.

provisional application serial number 62/115,111, filed February 11, 2015, the disclosure of which is incorporated by reference in its entirety.

FIELD

[0003] Disclosed embodiments are related to methods for nano and micro-patterning.

BACKGROUND

[0004] Fabrication of structural elements with nanoscale dimensions has previously employed patterning techniques such as photolithography, electron-beam lithography, and focused ion-beam. While these methods can pattern at high fidelity, each involves a trade-off among four key criteria: resolution, scalability, processing cost, and/or processing time. More recent methods attempting to overcome these limitations include directed assembly, DNA- mediated assembly, superlattice nanowire pattern transfer, dip-pen lithography, and soft- lithography. Together, these approaches aim to assemble or pattern nanoscale materials, thereby expanding the nanofabrication repertoire. Many of these strategies, however, require the design of new chemistries or sophisticated masks each time a new pattern is desired, thus reducing flexibility and throughput. Furthermore, such methods are prone to high defect densities, thus precluding reliable patterning over large substrate areas. SUMMARY

[0005] In one embodiment, a method for forming a device includes:

electrochemically etching a first material layer comprising a first material disposed on a substrate, wherein electrochemically etching the first material layer comprises applying to the first material layer an electrochemical potential that changes according to a sequence; and forming a pattern of a second material on the substrate during the electrochemical etch, wherein the pattern relates to the sequence.

[0006] In another embodiment, a method for forming a device includes: applying a plurality of electrochemical etching cycles to etch and pattern a first material layer disposed on a substrate through one or more openings formed in a masking layer disposed on the first material layer.

[0007] In some embodiments, an applied electrochemical etching cycle may include electrochemically etching a first material layer disposed on a substrate through one or more openings formed in a masking layer disposed on the first material layer and converting the first material layer at a boundary of an etched region underlying the masking layer to an etch resistant second material disposed on the substrate.

[0008] In select embodiments, an applied electrochemical etching cycle may include applying a first voltage for a first duration and applying a second voltage for a second duration, where the second voltage is different from the first voltage.

[0009] In certain embodiments, an applied electrochemical etching cycle may include sweeping an applied electrochemical etching potential from a first voltage to a second voltage at a first scan rate and from the second voltage to a third voltage at a second scan rate.

[0010] In yet another embodiment, a method for forming a semiconductor device, the method comprising: forming one or more openings in a masking layer disposed on a first material layer comprising a first material, wherein the first material layer is disposed on a substrate; electrochemically etching and patterning the first material layer by sweeping from a first voltage to a second voltage with a first scan rate; and electrochemically etching and patterning the first material layer by sweeping from a third voltage to a fourth voltage with a second scan rate. [0011] In another embodiment, a device includes a substrate, a first material layer comprising a first material disposed on the substrate, a masking layer disposed on the first material layer, and an opening formed in the masking layer. A portion of the substrate underlying the opening is substantially free of the first material layer, and an area of the portion is greater than an area of the hole. The device also includes one or more features comprising a second material disposed on the portion of the substrate underlying the masking layer. The one or more features are symmetrically arranged about the hole, and the features are spaced apart by one or more predetermined distances.

[0012] In yet another embodiment, a device includes a substrate and an array of posts comprising a first material disposed on the substrate. The device also includes one or more features disposed on the substrate and surrounding each post of the array of posts. The one or more features comprise the first material and are located equal distance between at least two posts of the array of posts.

[0013] In another embodiment, a device includes a substrate and a first material layer comprising a first material disposed on the substrate. At least one portion of the substrate substantially free of the first material layer. The device also includes a post comprising a second material disposed on the substrate within each portion and a plurality of features comprising the second material disposed on the substrate and symmetrically arranged around the post within each portion.

[0014] It should be appreciated that the foregoing concepts, and additional concepts discussed below, may be arranged in any suitable combination, as the present disclosure is not limited in this respect. Further, other advantages and novel features of the present disclosure will become apparent from the following detailed description of various non- limiting embodiments when considered in conjunction with the accompanying figures.

BRIEF DESCRIPTION OF DRAWINGS

[0015] The accompanying drawings are not intended to be drawn to scale. In the drawings, each identical or nearly identical component that is illustrated in various figures may be represented by a like numeral. For purposes of clarity, not every component may be labeled in every drawing. In the drawings: [0016] Fig. 1 is a flow diagram of an exemplary method to pattern a substrate;

[0017] Fig. 2 is an exemplary graph of a possible cyclical voltage profile;

[0018] Fig. 3 is an exemplary graph of a possible stepped formation voltage profile;

[0019] Fig. 4A is a schematic top view of a masking layer disposed on substrate;

[0020] Fig. 4B is a schematic cross-sectional view of the substrate of Fig. 4A;

[0021] Fig. 5A is a schematic top view of the substrate of Fig. 4A with an opening in the masking layer;

[0022] Fig. 5B is a schematic cross-sectional view of the substrate of Fig. 5A;

[0023] Fig. 6A is a schematic top view of the substrate of Fig. 5A after

electrochemical cycling;

[0024] Fig. 6B is a schematic cross-sectional view of the substrate of Fig. 6A;

[0025] Fig. 7A is a schematic top view of the substrate of Fig. 6A after removing the masking layer;

[0026] Fig. 7B is a schematic cross-sectional view of the substrate of Fig. 7A.

[0027] Fig. 8 is a schematic representation of a patterning process of a material layer deposited onto a master pattern;

[0028] Fig. 9A is a schematic representation of an electrochemical cell used to pattern a masked substrate during a first portion of a formation cycle;

[0029] Fig. 9B is a schematic representation of the formation processes occurring during the portion of the formation cycle illustrated in Fig. 9A;

[0030] Fig. 10A is a schematic representation of an electrochemical cell used to pattern a masked substrate during a second portion of a formation cycle;

[0031] Fig. 10B is a schematic representation of the formation processes occurring during the portion of the formation cycle illustrated in Fig. 10A;

[0032] Fig. 11 is a schematic representation of features patterned on substrate using an etching profile with a first duration;

[0033] Fig. 12 is a schematic representation of features patterned on a substrate using an etching profile with a second shorter duration than that of Fig. 11;

[0034] Fig. 13 presents a graph of patterned feature periods versus scan rate;

[0035] Fig. 14 is a scanning electron micrograph of a pattern formed using a scan rate of 65 mV/s; [0036] Fig. 15 is a scanning electron micrograph of a pattern formed using a scan rate of 100 mV/s

[0037] Fig. 16 is a scanning electron micrograph of a pattern formed using a scan rate of 300 mV/s

[0038] Fig. 17 is a dark-field scanning TEM of a cross-section of a pattern formed in a germanium layer disposed on a silicon substrate;

[0039] Fig. 18 is a scanning electron micrograph of a pattern formed using a hole formed in the associated mask;

[0040] Fig. 19 is a scanning electron micrograph of a pattern formed using a square hole formed in the associated mask

[0041] Fig. 20 is a comparison of scanning electron micrographs of patterns formed using different scan rates;

[0042] Fig. 21 A is a scanning electron micrograph of a patterned platform raised above the surrounding substrate;

[0043] Fig. 21B is a close-up of the patterned features shown in the scanning electron micrograph of Fig. 21 A;

[0044] Fig. 22 is a comparison of the patterned features formed at different pH levels;

[0045] Fig. 23A is a scanning electron micrograph of a cross-section of patterned features formed on a substrate;

[0046] Fig. 23B is a close-up of the electron micrograph shown in Fig. 23A;

[0047] Fig. 23C is a close-up of the scanning electron micrograph shown in Fig. 23B;

[0048] Fig. 23D presents electron dispersive spectroscopy (EDS) results for the electron micrograph shown in Fig. 23C;

[0049] Fig. 24 is a graph of cyclic voltammetry traces applied to pattern a substrate;

[0050] Fig. 25 presents the patterned feature evolution during the cycling shown in

Fig. 24;

[0051] Fig. 26 is a graph of patterned feature period for different ring pairs and different scan rates;

[0052] Fig. 27 is a scanning electron micrograph of patterned copper features on a silicon substrate; [0053] Fig. 28 presents electron dispersive spectroscopy measurements showing Cu and Si for one of the patterned features shown in Fig. 27;

[0054] Fig. 29 presents a scanning electron micrograph of a patterned copper feature and associated electron dispersive spectroscopy measurements;

[0055] Fig. 30A is a schematic layout of overlapping patterned features formed on a substrate;

[0056] Fig. 30B is scanning electron micrograph layout of overlapping patterned features formed on a substrate

[0057] Fig. 31 is a scanning electron micrograph and associated electron dispersive spectroscopy measurements of a patterned cobalt phosphate layer on a silicon substrate;

[0058] Fig. 32 is a graph of cyclic voltammetry traces applied to pattern the substrate shown in Fig. 31;

[0059] Fig. 33 is a graph of 0 ₂ evolved by the patterned cobalt phosphate catalyst;

[0060] Fig. 34 is a scanning electron micrograph of a patterned layer forming a terraced structure;

[0061] Fig. 35 is a graph of feature height across a diameter of the patterned layer shown in Fig. 34 obtained using an atomic force microscope;

[0062] Fig. 36 is a cyclical voltammetry trace applied to the patterned layer shown in

Fig. 34;

[0063] Fig. 37 is a scanning electron micrograph of a patterned layer formed using variable scan rates during formation;

[0064] Fig. 38 is a graph of potential and current for the formation pulses applied to a patterned substrate;

[0065] Fig. 39 is a scanning electron micrograph of an array of patterned features formed on a substrate;

[0066] Fig. 40 is a scanning electron micrograph and associated electron dispersive spectroscopy measurements for one of the patterned features shown in Fig. 39;

[0067] Fig. 41 A is three dimensional schematic representation of the measured feature height obtained using atomic force microscopy (AFM) of one of the patterned features shown in Fig. 39; [0068] Fig. 4 IB is a graph of feature height taken across a diameter of the AFM scan shown in Fig. 41 A;

[0069] Fig. 42 is a graph of calculated radial distances for features formed using a constant potential and pulse duration;

[0070] Fig. 43 is an optical image of a patterned layer formed using variable pulse durations to form constant features with a constant radial pitch;

[0071] Fig. 44 is a scanning electron micrograph of the patterned layer shown in Fig.

43;

[0072] Fig. 45 presents a comparison of optical images of patterned layers formed with varying pulse durations;

[0073] Fig. 46A-46D are optical images of a patterned layer being formed over multiple formation cycles;

[0074] Fig. 47A-47C are optical images of an initial etch front formed in a patterned layer at different applied potentials;

[0075] Fig. 48A-48D are scanning electron micrographs and associated electron dispersive spectroscopy measurements for a patterned layer formed using first and second potentials applied without a delay between them;

[0076] Fig. 49A-49D are scanning electron micrographs and associated electron dispersive spectroscopy measurements for a patterned layer formed using a first potential and a second potential applied after a 30 minute delay;

[0077] Fig. 50 is a schematic representation of the formation mechanisms for the patterned layers;

[0078] Fig. 51A-51C are scanning electron micrographs of patterned silver circular

Bragg gratings;

[0079] Fig. 52 is a graph of feature height for the patterned layer shown in Figs. 51 A-

51C;

[0080] Fig. 53A is an optical image of silver Circular Bragg Gratings (CBG); and

[0081] Fig. 53B-53C are images of the scattering profiles of the CBG shown in Fig.

53A. DETAILED DESCRIPTION

[0082] The inventors have recognized that typical nano-fabrication methods require the design of new chemistries or sophisticated masks each time a new pattern is desired, thus reducing flexibility and throughput. Furthermore, such methods are prone to high defect densities, thus precluding reliable patterning over large substrate areas. Therefore, the inventors have recognized the benefits associated with flexible manufacturing techniques which may enable the relatively easy construction of nano-enabled devices using solid-state materials with nanoscale dimensions and controllable long-range order. This may include simple and scalable methods for large-area patterning of periodic metallic and non-metallic nanostructures on electrochemically active substrates using cyclic electrochemical etching of a substrate through a pattern of one or more holes formed in an etching mask. The ability to pattern complex nanostructures over large areas in a facile and reliable manner has significant implications for fabrication of electronic, photonic, and energy devices including but not limited to gratings, antennas, patterning site specific catalysts, active optical circuits, plasmonic filters on large areas, resonators, high area detectors, sensors, and filters to name a few.

[0083] In view of the above, the Inventors have recognized the benefits associated with forming a device by electrochemically etching a layer of a first material disposed on a substrate. Specifically, the electrochemically etching is done in a manner such that an applied electrochemical potential changes according to a sequence to form a pattern of a second material on the substrate during the electrochemical etching sequence. Further, the formed pattern is related to the electrochemical etching sequence. For example, in some embodiments the etching sequence might include applying a plurality of electrochemical etching cycles to etch and pattern a first material layer disposed on a substrate through one or more openings formed in a masking layer disposed on the first material layer. These electrochemical etching cycles may correspond to a number of different types of potential profiles as the disclosure is not so limited. In one such embodiment, an electrochemical etching cycle might include the application of a plurality of discrete pulses which may correspond to, for example, a first voltage applied for a first duration and a second voltage applied for a second duration where the voltages are different from one another. In another embodiment, the electrochemical etching cycle may include scanning between two or more different voltages. The above noted applied voltages, scan rates, and/or durations may either be constant between subsequent electrochemical etching cycles, or they may vary between subsequent electrochemical etching cycles, as the disclosure is not so limited.

[0084] Without wishing to be bound by theory, it is believed that the patterned features formed according to the process described herein are formed in the following manner. During an initial etching portion of an electrochemical etching cycle, an appropriate voltage potential is applied that etches the material layer through an associated opening in a masking layer. This results in a concentration gradient of the etched material within the electrolyte that varies from a larger ion concentration at a boundary of the etched region to a lower ion concentration at the opening. The applied voltage potential is then varied to an appropriate potential to convert the material located at a boundary of an etched region of the layer underlying the masking layer to an etch resistant material disposed on the substrate. This process is then repeated during subsequent etching cycles expanding the etched regions and forming additional etch resistant material during each cycle which forms a plurality of patterned features on the substrate within the etched region. As detailed further below, the shape, pitch (i.e. spacing), width, height, and other appropriate dimensions of the patterned features may be controlled in a variety of ways.

[0085] In one embodiment, and as depicted in Fig. 1, a method for forming a nano- patterned device includes providing a substrate with a first material layer disposed on the substrate at 2. The material layer is a different base material than the underlying substrate. An etching mask is subsequently formed on the first material layer at 4. The etching mask may be formed directly on the first material layer or it may be disposed on top of one or more intermediate layers as the disclosure is not so limited. The etching mask may be made from any appropriate material for use with a desired etchant. One or more openings are then patterned into the etching mask 6. The one or more openings may be arranged in any desirable pattern and have any number of different shapes and sizes as described in more detail below. The substrate including an etching mask with the one or openings formed therein is then subjected to a plurality of electrochemical etch cycles to form a patterned structure associated with each of the openings at 8. Without wishing to be bound by theory, it is believed that surrounding edge portions of the first material layer around the openings and patterned areas are dissolved during the anodic portion of each cycle. A corresponding feature comprising a second type of material disposed on the substrate is then formed during the cathodic portion of each cycle. The deposited feature is resistant to further etching.

Consequently, the deposited features remain on the substrate during subsequent cycles. As this process is repeated, this results in a plurality of features being deposited onto the substrate during multiple cycles of an electrochemical etching process. In some chemistries, depending on whether the electrochemical etching is ended on a cathodic or anodic portion of the cycle, posts aligned with each of the openings may be retained on, partially removed from, and/or completely removed from the substrate at 10. However, in other chemistries, these posts aligned with the openings may not be present. For example, the presence of posts was observed for germanium (Ge) on silicon (Si) patterned devices while the posts were not observed for cobalt (Co) on silicon (Si) patterned devices. Regardless of whether posts are present or not on a final patterned device, after the cyclic electrochemical etching, the mask is subsequently removed and optional further processing of the patterned substrate may be conducted at 12 and 14.

[0086] Without wishing to be bound by theory, the shape, size, and positioning of the features patterned using the methods disclosed herein are dependent on the particular voltage profiles applied during electrochemical etching. More specifically, the spacing and/or heights of the resulting features may be controlled by varying the applied voltage potentials, pulse durations, and/or voltage profile shapes. Depending on the embodiment, an

electrochemical etching process may include a plurality of individual etching pulses with discrete maximum and minimum magnitudes and durations. These magnitudes and durations may either be constant, or they may vary with time, as the disclosure is not so limited.

Alternatively, in some embodiments a continuously varied voltage profile that is swept between different voltages to create the different portions of the etching cycles may also be used. Various embodiments of applied electrochemical etching cycle profiles are detailed further below.

[0087] Fig. 2 depicts one embodiment of a sequence of electrochemical etching cycles that include continuously varied voltage potentials that are scanned between different maximum and minimum voltages. In the depicted embodiment, a plurality of cycles are applied that vary between different first and second voltage magnitudes Vi and V ₂ that may be held constant during subsequent etching cycles. However, in some embodiments, the applied voltage magnitudes may vary as illustrated by the change in the applied voltage magnitude from V ₂ to a third voltage magnitude V ₃ which may be less than or greater than V ₂ . While the first voltage magnitude was not varied in the depicted embodiment, it should be understood that Vi may also be varied between cycles as well. It should also be understood that the durations of the various portions of an electrochemical etching cycle may also be held constant during a formation process and/or may vary during subsequent electrochemical etching cycles as the disclosure is not so limited. For example, in one embodiment, and as illustrated in the figure, the durations, and associated scanning rates, of the applied potential between Vi, V ₂ , and V ₃ may either be constant between electrochemical etching cycles as shown by duration Ti and/or the duration may be varied during a formation process as shown by a second duration T ₂ . Additionally, the various portions of a single electrochemical etching cycle may either have the same or different durations and/or associated scan rates. Based on the forgoing, it should be understood that the applied voltage magnitudes, durations, and/or scan rates may either be constant journey formation process and/or they may be varied during a formation process as the disclosure is not so limited.

[0088] In another embodiment, a sequence of electrochemical etching cycles follows a stepped profile of discrete pulses applied to electrochemically etch and patterned a substrate. As illustrated in Fig. 3, a first voltage Vi is applied for a first duration TV The applied voltage profile is then stepped up to a second voltage V ₂ for a second duration T ₂ prior to being stepped down to \ In some embodiments, this electrochemical etching cycle may be repeated multiple times with the same applied voltages and durations for each cycle. However, in some embodiments, after completing an electrochemical etching cycle the first voltage Vi may be held for a third duration T ₃ that is different than TV In the depicted embodiment T ₃ is greater than TV However, this also possible that T ₃ may be less than TV Similarly, the duration that the second voltage V ₂ is applied may also be varied in subsequent electrochemical etching cycles as illustrated by duration T ₄ that is different than TV

Additionally, in some instances the various applied voltage magnitudes applied during subsequent electrochemical etching cycles may also be varied as illustrated by upper voltage magnitude V ₃ and lower voltage magnitude V ₄ . Again, it should be understood that the upper and lower voltage magnitudes may either be less than or greater than the applied upper and lower voltage magnitudes of the previous electrochemical etching cycle. Additionally, in some embodiments, the durations and/or voltage magnitudes may become progressively larger and/or smaller over the course of a sequence of the applied electrochemical etching cycles. Of course, while constant voltages have been depicted during individual pulses in the figures, embodiments in which the voltage is not constant during a pulse are also

contemplated.

[0089] While several sequences of electrochemical etching cycles are described above, it should be understood that the current disclosure is not limited to only the electrochemical etching cycles illustrated in the figures. Instead, the current disclosure should be found to embrace any of the noted variations and combinations for a sequence of applied electrochemical etching cycles described herein.

[0090] Without wishing to be bound by theory, increasing the duration, and/or decreasing the scan rate, of an electrochemical cycle leads to increased feature spacings and/or widths. Correspondingly, decreasing the duration, and/or increasing the scan rate, of an electrochemical cycle leads to decreased feature spacings and/or widths. Additionally, this concept may be applied either to both, or only one of, the etching and feature formation portions of an electrochemical etching cycle. For example, the duration of a first pulse used to etch a material may be selected to provide a desired feature spacing while a duration of a second subsequent pulse may be selected to provide a desired feature width. Additionally, these durations may be changed during subsequent cycles to either provide constant, or varying, feature spacings/or and widths as the disclosure is not so limited.

[0091] In some embodiments, appropriate voltage magnitudes for the various voltage pulses include, but are not limited to -0.1 V to 1.3 V, -0.1 V to 1.2 V, 0.1 V to 1.2 V, and 0.1 V-0.8 V as well as other appropriate ranges. Of course, while the above voltages may be appropriate for certain material systems, it should be understood that other voltage ranges may be used with other material systems as the disclosure is not so limited. Additionally, the voltages may either undergo a continuous sweep, a discontinuous sweep such as a step sweep, a stepped pulse profile, or any other appropriate form. In instances where a sweep profile is used, the sweep rates may vary between 30 mV/s to 1000 mV/s, 30 mV/s to 500 mV/s, or any other desired sweep rate. In other embodiments, pulses may be applied for 0.5 seconds, 1 sec, 2 sec, 3 sec, 5 sec, 10 sec, 20 sec, or any other appropriate duration. Again, without wishing to be bound by theory, increased sweep rates and decreased durations may be equated with increased feature spacing and/or width. Depending on the desired scan rate and number of cycles, the total etching process may be on the order of, or less than, a minute. However, other processing times are also contemplated.

[0092] Figs. 4A and 4B depict a substrate 100 including a first material layer 102 disposed on the substrate and an etching mask 104 disposed on the first material layer prior to patterning. Figs. 5A and 5B illustrate the formation of one or more openings 106 in the etching mask 104 which may be formed using any appropriate technique for forming a hole in a masking layer. As can be seen, in the depicted embodiment, the opening does not extend into the first material layer. However, in some embodiments, the openings either extend partially, or completely through, the first material layer as the disclosure is not so limited. Figs. 6A and 6B illustrate the device after being subjected to multiple electrochemical etching cycles. As can be seen, the etching mask 104 is still intact and the opening 106 is

substantially the same size. However, as illustrated in Fig. 6B, the first material layer has been patterned to form a central post 108, which may not be present in some material systems, and one or more features 110 and associated void space located between the etching mask and substrate around each opening. The central post and associated features are aligned with the opening 106 located in the etching mask 104. The features have a height that is less than a height of the original first material layer. Therefore, the features are located underneath the etching mask forming the noted void space between the features and mask. Figs. 7A-7B depicted the patterned device after the masking layer has been removed which may be done using any appropriate technique including etching, dissolution, as well as grinding to name a few.

[0093] In the depicted embodiment, the features surrounding the post are spaced from each other by a radial spacing, or pitch, P and symmetrically arranged around the central post. Without wishing to be bound by theory, such a constant spacing may be due to the

application of sequentially increasing pulse durations, and/or decreasing scan rates, during a formation process. However, the spacing and/or widths of these features may be individually varied depending on the etching parameters applied during the deposition of that particular feature. For example, larger and smaller periods between the features may be present.

Additionally, while a central post has been depicted, in other embodiments, a central post may not be present. Again, without wishing to be bound by theory, it is believed that the central post is removed at the end of the anodic sweep or pulse and is redeposited during the cathodic sweep or pulse permitting very precise control over whether or not a central post is present in the final device at each patterned location.

[0094] While a single opening and associated post and deposited features has been depicted in the figures, it should be understood that any number of openings may be formed in an etch mask. Consequently, any number of patterned areas may be formed on the substrate. Additionally, depending on the relative spacing of these patterned areas as well as the number of electrochemical etching cycles conducted, the patterned areas may interact with one another. For example, and as described in more detail below, depending on the particular arrangement of the original openings in the etch mask, the deposited features may form various shapes on the substrate. These shapes may correspond to any appropriate shape and are not limited to only those described herein. For example, by controlling the etching bath pH, materials selection, pulse parameters (e.g. voltage range, scan rate, pulse duration, number of scans, etc.), and other appropriate etching parameters, it is possible to control the size and shape of the resulting deposited features. For example, thin rings, mesa like structures, or terraced structures may be formed. Additionally by controlling the shape of the hole, the resulting shapes may be influenced. For instance, circular and square openings in the mask result in concentric circular features. However, elongated linear openings result in the formation of one or more concentrically located ovals similar to race tracks with parallel linear sides and curved ends. Similar results are expected for non-linear shapes that would result in shapes that surround the non-linear opening. These shapes may interact with one another to form complex geometries as well. For example, an arrangement of concentrically arranged rings patterns formed around four mask etch openings arranged in a square shape will form a square feature located equal distance between the openings, and if present, the central posts. Other more complex geometries may be formed by controlling the location, size, and shape of the openings.

[0095] The deposited features may have any appropriate pitch, height, and/or width as the disclosure is not so limited. However, in one embodiment, a pitch of the deposited features is between about 200 nm and 10 μιη. Additionally, the height of the features may be between or equal to about 10 nm and 50 nm. The features may also have a width that is between or equal to about 200 nm to several micrometers. While specific dimensions are given, other feature dimensions are also contemplated.

[0096] As noted above arrays of features may be formed. Depending on their particular application, these patterned areas may act as pixels or individual elements.

However, when the deposited features associated with two or more patterned areas overlap they can form a desired shape. For example, a square lattice array may be used to create a one or more substantially square elements made from the deposited overlapping concentric rings. Similarly, a hexagonal close packed array may be used to create a regular structure. These features could be combined with linear elements to create connections between structures or to form other possible combinations of structures. By altering the distance, and arrangement, of openings within a masking layer, it is believed that any number of different shapes and structures could be formed using the methods described herein. Additionally, multiple patterned features may be disposed on the substrate without the use of an array to again form separate structures from the overlapping portions of the formed patterns.

Therefore, it should be understood that the one or more structures formed by overlapping portions of two or more patterned features are not limited to any particular layout or shape.

[0097] Due to the simplicity in forming openings with simple shapes such as dots and lines in a masking layer, the disclosed patterning processes may be applied to virtually any size surface area. For example this patterning process may be used on an entire silicon wafer surface which may be between about 1 to 12 inches in diameter, or any other size wafer.

[0098] It should be understood that the substrate and first material layer may correspond to any appropriate material combination capable of being electrochemically etched while leaving the substrate intact and forming a second material on the substrate during cycling that is resistant to further etching to deposit a desired pattern. For example, combinations of semiconductors materials and/or metallic materials might be used. Several specific embodiments include, but are not limited to: a silicon (Si) substrate and germanium (Ge) layer disposed on the substrate; a silicon substrate and cupper (Cu) layer disposed on the substrate; a silicon substrate and gold (Au) layer disposed on the substrate; a silicon substrate and germanium layer disposed on the substrate; a silicon (Si) substrate and a cobalt (Co) layer disposed on the substrate; and a multiple-layered system such as cobalt (Co) and copper (Cu) layers disposed sequentially in any appropriate order on top of a substrate such as silicon (Si). While silicon substrates are noted above, other appropriate substrates, such as a gallium nitride (GaN) substrate, might also be used.

[0099] It should be understood that any appropriate electrolyte may be used, and that appropriate electrolytes may vary depending on the particular material system being patterned. Several possible electrolytes include, but are not limited to, KP0 ₄ , H ₂ S0 ₄ , and Na ₂ S0 ₄ , KC1. When working with materials that may form a passivated oxide film, appropriate electrolytes capable of depositing the materials without forming a passivated film may be used. For example, KC1, in addition to other appropriate electrolytes, may be used for patterning Nickle (Ni) layers. Additionally, it should be understood that depending on the particular chemistry in use, the electrolytes may include any number of different solvents and co-solvents including both aqueous and non-aqueous bath chemistries.

[00100] Depending on the particular material system being used, the material redeposited onto the substrate during cyclic electrochemical etching, may be an oxide or different crystalline phase than the original first material layer such that the deposited material is resistant to further etching. These materials may include, but are not limited to, germanium oxide (GeO), copper, gold, and other appropriate materials.

[00101] After removing the etching mask, additional processing may be done. For example, portions of features, such as the rounded ends of oval shaped features, may be selectively etched away to form parallel linear traces. Additionally, metallic, semiconductor, or other materials could be deposited onto the traces using any appropriate deposition method. Alternatively, the underlying substrate could be etched to isolate features or form nano or microfluidic channels as might be done with a germanium substrate using a peroxide etch. In some embodiments, coatings, or other material layers, might be applied to the patterned device to add desired functionalities. Of course other types of post processing processes and features may also be included as the disclosure is not so limited.

[00102] In some embodiments, the substrate is a flexible substrate such as a conductive polymer. In such an embodiment, a pattern of holes may be formed in an etch mask prior to rolling up the substrate. The rolled up substrate may then be subjected to cyclic

electrochemical etching to form patterned nanoscale features as described herein without requiring line of sight etching as is required in typical processes. The patterned substrate may then have the etch mask removed either after unrolling, or in some instances, an etching mask may be dissolved or otherwise removed without unrolling the substrate.

[00103] In some embodiments, the etching voltages may be controlled to facilitate heterogenous etching of various material layers. In such an embodiment the voltage may be maintained such that it etches a first material layer but does not etch a second material layer. This may permit the selective formation of patterned features and/or arrays of features in specific locations where a desired material is located and may also facilitate compatibility with other typical formation processes.

[00104] Fig. 8 illustrates a related process that uses a patterned device made using the above noted methods and materials to form another patterned device. Here a master pattern 200 including a plurality of patterned features 202 disposed thereon is made as detailed herein. A desired material is then deposited onto the master pattern to form a layer 204 thereon. This layer may be deposited using any appropriate method including, but not limited to, electron beam evaporation, thermal evaporation, laser ablation, chemical vapor deposition, thermal evaporation, plasma assisted chemical vacuum deposition, laser enhanced chemical vapor deposition, jet vapor deposition, slip casting, as well as spin coating to name a few. Regardless of the specific deposition method, the deposited material forms a negative pattern 206 of the features formed on the master pattern. Subsequently, the layer is delaminated, exfoliated, or otherwise removed from the master pattern providing a patterned device made from the deposited material. For example, as detailed below in the examples a Circular Bragg Grating may be formed by depositing silver onto a patterned substrate formed using the methods described herein and subsequently delaminating the silver layer from the patterned substrate (i.e. the master pattern).

[00105] Example: Formation Processes

[00106] Without wishing to be bound by theory, Figs. 9A-10B illustrate the formation processes believed to form the patterned features on a substrate using the techniques described herein. In the figures, a 2-compartment electrochemical cell 300 includes a Pt mesh electrode submerged in the left chamber and the working electrode, which undergoes patterning, submerged in the right chamber. The working electrode, whose axial cross-section is shown in Figs. 9B and 10B, may consist, for example, of a Ge thin film, i.e. material layer 102, disposed on a substrate 100 that is exposed at defined sites (e.g. openings) through a masking, or resist, layer as described previously. During the first portion of an etching cycle, lateral etching of the material layer proceeds underneath the masking layer, Fig. 9B. During the second portion of the etching cycle, continued etching of the material layer and site- selective deposition of the patterned features 110 occur, 10B.

[00107] Example: Varying Scan Rate and/or Pulse Duration

[00108] Figs. 11 and 12 depict schematic representations of patterned substrates and the related sequence of electrochemical etching cycles used to form the patterned features 110. As illustrated in the figures, a period of the electrochemical etching cycles used to form the pattern in Fig. 11 is larger than a period of the electrochemical etching cycles used to form the pattern in Fig. 12. As illustrated in the figures, a larger period, which is related to decreased scanning rate, or increased pulse duration, results in patterned features that are located further apart, i.e. a larger pitch or spacing of the patterned features. Similarly, a smaller period, which is related to increased scanning rates, or decreased pulse durations, may result in a smaller pitch or spacing of the patterned features.

[00109] Example: Patterning Methods

[00110] The patterned substrates described in the following examples were formed by imparting patterns onto the working electrode of a standard 3 -electrode electrochemical setup similar to that shown in Figs. 9A and 10A. A parent material, which can be a semiconductor (e.g., Ge) or metal (e.g., Cu), was deposited by chemical or physical vapor deposition over the working electrode. Subsequently, a thin layer of polymer resist was dispersed over this parent layer and openings corresponding to lines or dots were formed therein to give the electrolyte access to the underlying parent film. The substrate thus prepared was the working electrode in a standard 2-compartment electrochemical cell filled with 0.1 M sulfuric acid as the electrolyte. Voltage potentials between 0.1 - 1.3 V, all potentials are referenced to the Ag/AgCl electrode, were then applied using either appropriate scan rates and/or as discrete stepped pulses. After formation the masking layer was removed.

[00111] In several specific examples described below, Silicon p-type doped substrates

(Prime Grade 3-5 Ω cm, Nova Electronic Materials) of dimension 2 cm were cleaned by UV/ozone ashing followed by etching in buffered hydrogen fluoride. A chemical vapor deposition (CVD) reactor was used to grow a 250 nm thick poly-crystalline p-type Ge film at 330 °C at a growth pressure of 28 Torr. After Ge deposition, the substrate was coated with a 500 nm thick layer of S I 805 photo-resist (S 1805, MicroChem Corp.) or PMMA e-beam resist (PMMA C5, MicroChem Corp.). Using photolithography or electron beam lithography 2 μηι x 2 μιη dots were defined through the aforementioned resists to the underlying Ge film. A portion of the substrate was left free of resist to facilitate electrical contact of this working electrode via a Cu alligator clip to the potentiostat. The back and sides of the substrate were covered with a lacquer (Microshield, Tolber Chemical) to prevent electrolyte exposure to these regions. A two-compartment electrochemical cell was filled with 0.1 M sulfuric acid. The substrate (working electrode) was submerged into one compartment. z ^' R compensation was performed prior to every patterning experiment and yielded typical resistance values in the range of 500 - 1500 Ω. Standard three-electrode cyclic voltammetry experiments, and/or discrete pulses, were applies using a Ag/AgCl reference electrode (BAS Inc.), a Pt mesh counter electrode, and potentiostat (760D series, CH Instruments Inc.). Following

electrochemical etch cycling, all resists and lacquer were removed by soaking the substrate in acetone for ~1 min followed by a 10 s rinse in isopropanol. A gentle stream of N ₂ enabled drying. For Ge patterning, scans were initiated at the open circuit potential, which was 0.1 V.

[00112] Example: Patterned Feature Characterization

[00113] A Ge thin film was deposited over a Si substrate and the overlaid polymer photolithographically include an array of 2 μιη wide linear openings. After applying the cyclic voltammetric potential sweeps to this working electrode and subsequent stripping of the resist, an AFM map of a region of one pattern revealed well-defined parallel lines of sub- micron width and height. Over the range of CV scan rates utilized in patterning (50 mV/s to 200 mV/s), the features were 20(+l) nm high and 360(+15) nm wide. TEM cross-sections revealed the features to have an amorphous morphology while EDS maps showed them to be composed of Ge and O. A feature composed of an oxide of germanium is consistent with the thermodynamically favored products of oxidation of Ge at pH 1 and applied potentials utilized for patterning. It was observed that the number of features patterned on the substrate was defined by N - 1 where N is the number of electrochemical cycles the material layer and associated substrate are subjected to.

[00114] Example: Patterned Feature Period vs. Scan Rate

[00115] As illustrated in Fig. 13, the period separating the patterned features appears to follow a power law dependence on CV scan rate, and is expected to hold true for decreasing pulse durations. The period was varied from about 500 nm to about 7 or 10 μιη. Thus, controlling the scan rate and/or pulse duration of the applied potentials may be used to control the spacing of the patterned features to be constant or variable depending on the desired application.

[00116] Example: SEM and STEM characterization of periodic Ge patterns

[00117] Figs. 14-16 are SEM images of periodic concentric rings patterned at scan rates of 65, 100, and 300 mV/s yielding average periodicities of 4.01 μιη + 0.02 μιη, 2.73 μιη + 0.07 μηι, and 0.82 μιη + 0.02 μιη, respectively. Figs. 17 is a dark-field scanning TEM image of the axial cross-section of a patterned substrate. The area of uniform dark contrast at the bottom of the image is the Si substrate. The region of bright contrast at right is the un- etched Ge film and the thin strip of bright contrast corresponds to a 20 nm thick metal layer intentionally deposited to assist in differentiation of the patterned features. It is apparent that the Ge parent film undergoes complete etching to the underlying Si substrate and that the patterned features are selectively formed over the exposed Si substrate.

[00118] Figs. 18 and 19 are SEM images of patterned periodic features emanating from the site of an opening shaped as a line and dot.

[00119] Fig. 20 compares the periodically-spaced and parallel lines patterned from a single linear opening and formed using a 100 mV s ^_1 scan rate and 450 mV s ^_1 rate.

[00120] Figs. 21A-21B are SEM images of a square Ge on Si platform raised 7 μιη above the rest of the substrate plane prior to and after patterning of the platform region. The dashed white line denotes the site where a 2 μιη wide linear opening was formed in the associated masking layer and from which the patterns emanate.

[00121] Fig. 22 is a comparison of Atomic Force Microscopy (AFM) maps of periodically patterned sub-micron rings formed at a pH of 1 and periodic concentric terraces that step down in regular 20 nm increments formed at a pH of 6.

[00122] Figs. 23A-23B are bright-field TEM images of the axial cross-section of a substrate patterned with concentric rings. A thin metal layer (dark contrast) was deposited prior to patterning to assist in differentiation of the patterned features. Fig. 23C is a high- resolution bright-field TEM image of the interface between the patterned ring and underlying Si substrate. Fig. 23D presents the corresponding Electron Dispersive Spectroscopy (EDS) elemental maps for Fig. 23C showing the presence of Ge, O, and Si within the cross-section of a patterned ring.

[00123] Example: Pattern Evolution During Electrochemical Cycling

[00124] Fig. 24 is a graph of cyclic voltammograms at 100 mV s ^_1 performed in 0.1 M

H ₂ S0 ₄ . Figs. 25 is a series of accompanying SEM images of patterned structures showing the patterned features during sequential forward sweeps (solid lines corresponding to steps 1,

3, and 5) and reverse sweeps (dashed lines 2, 4, and 6) between 0.1 and 1.2 V (vs. Ag/AgCl).

[00125] Example: Pattern Evolution During Electrochemical Cycling

[00126] Fig. 26 is a graph of the average period for the 1 ^st through 4 ^th ring pairs within randomly sampled patterns at 3 different voltage scan rates: 65 mV s ^_1 (circle), 100 mV s ^_1

(square), and 300 mV s ^_1 (triangle).

[00127] Example: Patterned Copper on Silicon Substrate

[00128] Fig. 27 is an SEM image of an array of rings patterned from a Cu film on Si. A composite Cu and Si EDS map of one pattern is shown in Fig. 28 confirming the presence of concentric rings of Cu formed on the Si substrate. High-resolution STEM images of a 60 nm thick axial cross-section of a patterned Cu ring, and the associated EDS maps of Cu and O present in the ring, are shown in Fig. 29.

[00129] Example: Overlapping Patterned Features

[00130] Fig. 30A is a schematic representation of four patterns arranged in a square pattern. The resulting patterned features form a region where the rings from the adjacent patterns overlap with each other to form a patterned square shown in Fig. 30B. The inset of Fig. 30B confirms the presence of Ge within the square structure.

[00131] Example: Cobalt Phosphate Patterned Features

[00132] A patterned cobalt phosphate (CoPi) water splitting catalyst on a

platinum/silicon substrate was formed using the methods described herein. Fig. 31 presents an SEM image of the CoPi catalyst patterned into concentric rings and the associated EDS maps confirming the presence of Co and O within the CoPi catalyst pattern. Fig. 32 is a graph of cyclic voltammograms for the patterned CoPi catalyst at a scan rate of 100 mV s ^_1 in 0.1 M KP0 ₄ (pH 7) electrolyte. The catalytic wave initiates at about 0.9 V. Fig. 33 presents a graph of 0 ₂ evolved by the patterned CoPi catalyst as measured by a fluorescent probe and 0 ₂ calculated from charge passed assuming a Faradaic efficiency of 100%. [00133] Example: Pattern Formation in Na2SQ4

[00134] Fig. 34 is an SEM image of a patterned substrate after 5 electrochemical etching cycles using a sequence controlled using cyclicvoltammetry (CV) in 0.1 M Na ₂ S0 ₄ , the scale bar in the image is 4 μιη. Fig. 35 is an AFM line scan across the diameter of the pattern revealing a concentric terrace structure with the height decreasing in discrete steps from the central pillar to the periphery of the pattern. Fig. 36 is a graph of one CV trace acquired in 0.1 M Na ₂ S0 ₄ distinguished by the appearance of quasi-reversible waves consistent with the deposition of material discernible in the SEM image.

[00135] Example: Single patterning experiment at two scan rates

[00136] In a single uninterrupted experiment, an equal number of CV cycles were performed first at 100 mV s ^_1 and then at 400 mV s ^-1 . As shown in the SEM image of Fig. 37, the first set of patterned rings has an average period of 2.80 μιη in good agreement with the prior examples for rings patterned solely at 100 mV s ^-1 . The scale bar is 10 μιη. The rings patterned following the transition to a faster scan rate have a different spacing confirming it is possible to effect the spacing by controlling the scan rate or duration of a cycle.

[00137] Example: Anodization

[00138] A 250 nm metallic Co film on a Si substrate was patterned using CV in 0.1 M

H ₂ S0 ₄ with a scan rate during patterning of 200 mV s ^-1 . After patterning, the patterned Co was anodized at a potential of 0.95 V vs. Ag/AgCl (without z ^' R compensation) for 30 min in 0.1 M KP0 ₄ , pH 7.0 electrolyte.

[00139] Example: Patterning Using a Binary Potential Step

[00140] A binary-potential step method was used to generate patterns from cobalt overlaid on silicon by alternating between two discrete potentials. The sample (the same construction used previously) was suspended in 0.1 M K ₂ S0 ₄ and subjected to ten alternating potential steps (all potentials are reported vs. Ag/AgCl) between a 0.4 V (applied for 10 s) and 1.3 V (applied for 3 s), which correspond to the CV scan limits previously used to pattern silicon with cobalt oxide in the examples above. This electrochemical procedure resulted in five rings being formed. For steps with a fixed duration, the gap between the ring decreased as a function of distance from the center. In general, an even number of N alternations results in N/2 rings. By modulating the durations of the 0.4 V and 1.3 V steps, the spacing between rings and the ring widths was found to be adjustable, respectively. Patterns with uniform gap and ring dimensions were formed by sequentially increasing the duration of each step to compensate for the decreasing spacing, thereby demonstrating that the pattern geometry can be appropriately adjusting the durations of the applied potential pulses Without wishing to be bound by theory, partitioning the patterning process into two discrete potential steps affords improved control of pattern geometry while simultaneously eliminating the use of CV.

[00141] The masked substrate that was patterned included a 9x9 array of 4 μιη square openings. See Fig. 39 for an optical image of the resulting patterned substrate. As shown in Figs. 41A and 41B five concentric rings were produced and the ridges were 1.4 μιη wide and 130 nm tall on the patterned features. Scanning electron microscopy (SEM) with energy X- ray dispersion spectroscopy (EDS) maps of Co and O indicate that the ridges are composed of Co oxide, see Fig. 40. The gaps between the rings and ring thicknesses are attenuated as a function of distance from the pattern's center. The patterns generated by the binary-potential step are comparable to the CV-based methods discussed above with regard to both ring definition and spacing.

[00142] Example: Modelling of Feature Formation with Constant Duration Pulses

[00143] A model for the etching and patterning processes of a metallic Co layer was developed. In the model, etching of metallic Co at low anodic potentials is followed by oxidation of the metal to Co oxide when the potential is stepped to more positive anodic potential. Upon returning the potential, oxidation ceases, and etching begins on the backside of the Co oxide ring, extending away from the center of the ring. A scaling analysis indicates that the etching process is dictated by cobalt ion diffusion upon etching. The scaling analysis illustrates that as the etch front of metallic Co progresses from the opening, the mass transport of Co ²⁺ away from the etch front is deterred because the distance for diffusion into bulk electrolyte increases. Since the rings form at the perimeters of etch fronts evolving radially from the center, the diffusion behavior arising from the simulation predicts slower etching further from the center of the pattern, which accounts for the decreasing ring spacing in the experimental results. In addition, the increasing surface area of the etch front increases the concentration of cobalt ions, which become constricted at the opening. Consequently, for a binary-potential step method with constant durations for each potential, spacing between the rings decreases as the rings form further from the opening. It should also be mentioned that for the simulation of the pattern, only consider the spacing between the rings was considered. Therefore, the geometries of the rings are not critical for observing the trend in the ring spacing. This trend in ring spacing is verified experimentally as noted above.

Further, the experimental results supported by scaling analysis show that the mechanism of pattern formation establishes that the ring position depends on the distance of cobalt ion diffusion into the bulk electrolyte with the kinetic limitations of a confined etch front. Fig. 42 is a graph of predicted ring spacing from the finite-element simulations for constant duration pulses. Again, as illustrated in the figure, the ring spacing decreases with increasing distance from the central opening.

[00144] Example: Patterning Using Varying Duration Pulses

[00145] Figs.43 and 44 present optical and SEM images of Co patterned on Si using binary potential steps with both potential steps held for 5, 7, 9, 12 and 15 seconds during subsequent cycles. As can be seen in the figures, the radial spacing, i.e. pitch, of the formed features is approximately constant confirming that it is possible to control the spacing of the formed features by controlling the duration and/or scan rate of an electrochemical etching cycle. Specifically, the well-defined pattern had rings with 3.0 μιη widths and 3.8 μιη spacings.

[00146] Fig. 45 illustrates the dependence of pattern geometry on applied pulse duration for five applications of the two-potential sequence. In the series of patterns shown potentials of 0.4 V and 1.3 V were applied multiple times followed by one additional application of 0.4 V. To determine the effect of the duration of 0.4 V, 1.3 V was held for 3 s for each application and 0.4 V was held for the specified time indicated over each image {horizontal row). Similarly, 0.4 V was held at 10 s each application and 1.3 V was held for the time identified at the left of each image {vertical column). The center image shows the case where both potentials were held for 3 s. As confirmed by the figure, by modulating the durations of the 0.4 V and 1.3 V steps, the spacing between rings and the ring widths could be adjusted, respectively. Without wishing to be bound by theory, the correlation between ring spacings and ring widths with their respective potentials implies that at 0.4 V, the etching of Co metal occurs, while at 1.3 V, an oxide layer is formed. This result suggests that potential steps and durations could be selected to control the geometries of the resulting pattern. Again, this correlation is confirmed by the uniform gap and ring dimensions formed by sequentially increasing the duration of each step as shown in Fig. 44 above.

[00147] Example: Feature evolution

[00148] To delineate the correlation between applied potentials and electrochemical processes, the pattern formation was monitored using in situ optical microscopy. A video recording of the pattern formation by alternating between 0.4 V (10 s) and 1.3 V (3 s) ten times was synchronized to the applied potential and current so that the evolution of a pattern could be observed through optical micrographs, Figs. 46A-46D. Fig. 46A corresponds to a half cycle, Fig. 46B corresponds to a full cycle, 46C corresponds to two cycles, and 46D corresponds to the full 5 cycles. As shown in the figures, a bright-contrasted circle expands from the opening for the first 10 s, followed by 3 s upon which a dark-contrast ring propagates into the surrounding area. From AFM height and EDS maps, it was determined that the bright-contrasted circle and surrounding bright-contrast rings correspond to regions where cobalt was removed and the dark-contrasted rings correspond to cobalt oxide. These results are in agreement with the assignment to an etching process at 0.4 V and metal oxide formation at 1.3 V. With consideration to the Pourbaix diagram of Co, the reaction during etching at 0.4 V in 0.1 M K ₂ S0 ₄ corresponds to be the two-electron oxidation of CoO to a soluble Co ²⁺ ion or CoO(OH) .

[00149] Using a similar setup as above, similar diameters of the etch fronts after stepping the potential to 0.2 V, 0.3 V and 0.4 V for 10 sec, see Figs. 47A - 47C respectively, which indicate that the etching rate is relatively independent of the applied voltage.

[00150] Figs. 48A-48D are optical microscopy, SEM, and EDS images of an oxide layer formed by applying 0.4 V over 30 s, followed by 1.3 V over 20 s successively without a delay between the applied pulses. Figs. 49A-49D are optical microscopy, SEM, and EDS images of an oxide layer formed in the same way, but with a 30 min delay between the pulses. There is no appreciable difference between the resulting patterned features.

Therefore, without wishing to be bound by theory, the oxide formation process is

independent of diffusion, suggesting that the primary pathway for oxide formation is the direct conversion of Co metal to Co oxide. Cobalt is thus etched away at 0.4 V and the metallic front at the boundary of the etching front is converted into the oxide ridge at 1.3 V. This is consistent with the observation that the oxide layer extends into the CoO film during application of 1.3 V. The next ring is then formed upon cobalt etching from the backside of the Co oxide ring.

[00151] Example: Etching and Formation Mechanisms

[00152] Fig. 50 is a schematic figure showing the diffusion from the etching front to the bulk electrolyte. Arrows schematically indicate the diffusion flux of Co ²⁺ . The cross section is axisymmetric around the dash-dotted line on the right hand side of the image.

[00153] Example: Master Patterning and Bragg Grating

[00154] A Circular Bragg Grating (CBG) was formed by patterning a 0.25 mm square array containing 81 concentric ring structures formed using the methods disclosed herein. Each structure had 5 Ge rings with a period of 1 μιη patterned via 6 CV cycles at a voltage scan rate of 290 mV/s. A 150 nm Ag film was deposited over this Ge master pattern by electron-beam evaporation (Denton Vacuum LLC) after pumping to a base pressure of 2 x 10 torr. Next the Ag film side of the sample was pressed into contact with a clean quartz slide coated with a thin film of epoxy. The sample was cured overnight. After this, the Ge master pattern was peeled away from the Ag film using tweezers. The resultant Ag film remained fused to the quartz substrate and bore a high yield of recessed concentric ring structures. These recessed structures constitute the array of circular Bragg gratings shown in the SEM image of Fig. 51A-51C. An AFM line scan across a CBG verified that the depth, width, and period of the grooves is similar to the dimensions of the Ge rings in the master pattern, see Fig. 52. Notably, the master can be reused multiple times to template other CBG arrays composed of different metals.

[00155] To obtain scattering profiles from the CBG, a broadband (λ = 450 - 800 nm) super continuum laser (EXB-6, NKT Photonics) was used as an illumination source. A spectrometer (SpectraPro 300i, Acton Research) was used to select a narrowband

illumination with a central wavelength of λ = 500 nm. The scattering images, Figs. 53B and 53C, corresponding to the gratings shown in Fig. 53A, were captured by a Si charge-coupled device while the circular Bragg grating specimen was translated through the focal plane of a lOx optical lens. The acquired images of the scattering profiles were acquired at two slightly different imaging planes within ~1 μιη of the focal plane. These images show that point scattering, Fig. 53B, and annular scattering, Fig. 53C, arise from each CBG. In particular, complex "checkerboard" interference patterns are clearly discernable at the interstices between CBGs Fig. 53C. Such structured scattering is unique to a periodic array of periodic grating structures, where such surfaces may be interesting candidates for meta- surface applications especially given the ease, scale, and configurability with which they can be patterned.

[00156] While the present teachings have been described in conjunction with various embodiments and examples, it is not intended that the present teachings be limited to such embodiments or examples. On the contrary, the present teachings encompass various alternatives, modifications, and equivalents, as will be appreciated by those of skill in the art. Accordingly, the foregoing description and drawings are by way of example only.