Title:
MICROTLB AND MICRO TAG FOR REDUCING POWER IN A PROCESSOR
Document Type and Number:
WIPO Patent Application WO2005024635
Kind Code:
A3
Abstract:
A processor (10) comprises a cache (16), a first TLB (30), and a tag circuit (36). The cache (16) comprises a data memory (20) storing a plurality of cache lines and a tag memory (22) storing a plurality of tags. The first TLB (30) stores a plurality of page portions of virtual addresses identifying a plurality of virtual pages for which physical address translations are stored in the first TLB (30). The tag circuit (36) is configured to identify one or more of the plurality of cache lines that are stored in the cache (16) and are within the plurality of virtual pages. In response to a hit by a first virtual address in the first TLB (30) and a hit by the first virtual address in the tag circuit (36), the tag circuit (36) is configured to prevent a read of the tag memory (22) in the cache (16).
Inventors:
SHEN GENE W (US)
NELSON S CRAIG (US)
NELSON S CRAIG (US)
Application Number:
PCT/US2004/018042
Publication Date:
May 26, 2005
Filing Date:
June 04, 2004
Export Citation:
Assignee:
ADVANCED MICRO DEVICES INC (US)
SHEN GENE W (US)
NELSON S CRAIG (US)
SHEN GENE W (US)
NELSON S CRAIG (US)
International Classes:
G06F12/00; G06F12/08; (IPC1-7): G06F12/10
Foreign References:
| US6560679B2 | 2003-05-06 | |||
| US6138225A | 2000-10-24 |
Other References:
JIN-HYUCK CHOI, JUNG-HOON LEE, SEH-WOONG JEONG, SHIN-DUG KIM AND CHARLES WEEMS: "A Low Power TLB structure for Embedded Systems", COMPUTER ARCHITECTURE LETTERS, vol. 1, January 2002 (2002-01-01), XP002319140, Retrieved from the Internet [retrieved on 20050224]
YOUTAO ZHANG ET AL: "Low cost instruction cache designs for tag comparison elimination", PROCEEDINGS OF THE 2003 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN. ISLPED'03. SEOUL, KOREA, AUG. 25 - 27, 2003, INTERNATIONAL SYMPOSIUM ON LOW POWER ELCTRONICS AND DESIGN, NEW YORK, NY : ACM, US, 25 August 2003 (2003-08-25), pages 266 - 269, XP010658648, ISBN: 1-58113-682-X
JUNG-HOON LEE ET AL: "A selective filter-bank tlb system", PROCEEDINGS OF THE 2003 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN. ISLPED'03. SEOUL, KOREA, AUG. 25 - 27, 2003, INTERNATIONAL SYMPOSIUM ON LOW POWER ELCTRONICS AND DESIGN, NEW YORK, NY : ACM, US, 25 August 2003 (2003-08-25), pages 312 - 317, XP010658658, ISBN: 1-58113-682-X
INOUE K ET AL: "A history-based I-cache for low-energy multimedia applications", LOW POWER ELECTRONICS AND DESIGN, 2002. ISLPED '02. PROCEEDINGS OF THE 2002 INTERNATIONAL SYMPOSIUM ON AUG. 12-14, 2002, PISCATAWAY, NJ, USA,IEEE, 12 August 2002 (2002-08-12), pages 148 - 153, XP010600877, ISBN: 1-58113-475-4
YOUTAO ZHANG ET AL: "Low cost instruction cache designs for tag comparison elimination", PROCEEDINGS OF THE 2003 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN. ISLPED'03. SEOUL, KOREA, AUG. 25 - 27, 2003, INTERNATIONAL SYMPOSIUM ON LOW POWER ELCTRONICS AND DESIGN, NEW YORK, NY : ACM, US, 25 August 2003 (2003-08-25), pages 266 - 269, XP010658648, ISBN: 1-58113-682-X
JUNG-HOON LEE ET AL: "A selective filter-bank tlb system", PROCEEDINGS OF THE 2003 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN. ISLPED'03. SEOUL, KOREA, AUG. 25 - 27, 2003, INTERNATIONAL SYMPOSIUM ON LOW POWER ELCTRONICS AND DESIGN, NEW YORK, NY : ACM, US, 25 August 2003 (2003-08-25), pages 312 - 317, XP010658658, ISBN: 1-58113-682-X
INOUE K ET AL: "A history-based I-cache for low-energy multimedia applications", LOW POWER ELECTRONICS AND DESIGN, 2002. ISLPED '02. PROCEEDINGS OF THE 2002 INTERNATIONAL SYMPOSIUM ON AUG. 12-14, 2002, PISCATAWAY, NJ, USA,IEEE, 12 August 2002 (2002-08-12), pages 148 - 153, XP010600877, ISBN: 1-58113-475-4
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