CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] The present application claims priority to U.S. Provisional Application No. 63/396,568 filed August 9, 2022, the contents of which are incorporated herein by reference in their entirety.

STATEMENT OF GOVERNMENT SPONSORED RESEARCH

[0002] This invention was made with government support under N68335-20-C-0441 awarded by the Defense Advanced Research Projects Agency. The government has certain rights in the invention.

TECHNICAL FIELD

[0003] The present embodiments relate generally to magnetic shields, and more particularly to microfabricated magnetic shields that are configured to provide isolation of superconducting electronics (SCE) circuits/chips from each other and an external environment.

BACKGROUND

[0004] Recently, the push to integrate superconducting electronic devices has generated the need for physically larger areas being protected from DC magnetic fields. It is desirable to allow even more local magnetic shields that mitigate any influence of chip-to-chip coupling of the circuits or signal currents via local magnetic fields. Further miniaturization is therefore of high interest, but requires new concepts and technology, especially for attachment and completion of the magnetic circuits. In general, a solution is desired that integrates shields with multichip modules (MCMs).

[0005] It is against this technological backdrop that the present Applicant sought to solve these and other technological problems rooted in this technology. SUMMARY

[0006] One or more embodiments relate to custom microfabricated magnetic shields that are configured to provide isolation of superconducting electronics (SCE) circuits/chips from each other and an external environment. Whereas most superconducting circuits require magnetic shielding and most shields work by fully encapsulating the circuits, leaving little access for quite rigid and fragile fibers, one or more embodiments allow custom magnetic shield shapes to be fabricated. The shield design can depend upon the particular application, and many variations are possible. For example, in an optical interconnect application, the design can depend on whether an active (VCSEL) or passive photonic (grating/edge coupled) scheme is selected. A flexible solution is provided that supports both techniques. The shields can be created by depositing a monolithic layer conformally in a pit that has been fabricated in a silicon substrate. In embodiments, to improve the shielding, magnetic vias composed of permalloy can be introduced into the shield design. The vias can connect the magnetic shield to a permalloy layer beneath the silicon substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] These and other aspects and features of the present embodiments will become apparent to those ordinarily skilled in the art upon review of the following description of specific embodiments in conjunction with the accompanying figures, wherein:

[0008] Figures 1(a) and 1(b) illustrate an example COMSOL simulation of an 11 mT field applied to a 300 pm cylindrical shell.

[0009] Figure 2 is a cutaway illustration of an example HIPCEMS structure with integrated multi-layer magnetic shielding and fiber couplers according to embodiments. [0010] Figure 3 is a cross section of an example photonic structure according to embodiments.

[0011] Figures 4(a) and 4(b) illustrate an example FEA model setup for TPP mirror insertion loss estimate according to embodiments.

[0012] Figure 5 illustrates an example estimated insertion loss of the TPP mirror with 30 nm Ag layer according to embodiments. [0013] Figure 6 is a cross section of an example magnetic shield geometry for FEA modeling according to embodiments.

[0014] Figures 7(a) to 7(c) illustrate example aspects of addition of magnetic vias to magnetic shields according to embodiments.

[0015] Figures 8(a) to 8(d) illustrate example in-plane and out-of-plane shielding simulations according to embodiments.

[0016] Figure 9 is an expanded view of an example mTSV according to embodiments.

[0017] Figures 10(a) to 10(c) illustrate an example test setup for magnetic shield testing according to embodiments.

[0018] Figure 11 is a graph illustrating example magnetic shield testing results at room temperature and 4°K according to embodiments.

[0019] Figures 12(a) and 12(b) illustrate example interconnects printed for unclad optical fiber (a) and interconnects printed for clad optical fiber (b) according to embodiments.

[0020] Figures 13(a) and 13(b) illustrate example aspects of a custom surface patterning tool according to embodiments.

[0021] Figures 14(a) and 14(b) illustrate example aspects of measured magnetic flux density inside an unshielded dummy cylinder and a 300 pm Permalloy shield according to embodiments.

[0022] Figures 15(a) to 1 (c) illustrate example aspects of a HIPCEMS SMCM package with 3x3 array of SQUID chips according embodiments.

DETAILED DESCRIPTION

[0023] The present embodiments will now be described in detail with reference to the drawings, which are provided as illustrative examples of the embodiments so as to enable those skilled in the art to practice the embodiments and alternatives apparent to those skilled in the art. Notably, the figures and examples below are not meant to limit the scope of the present embodiments to a single embodiment, but other embodiments are possible by way of interchange of some or all of the described or illustrated elements. Moreover, where certain elements of the present embodiments can be partially or fully implemented using known components, only those portions of such known components that are necessary for an understanding of the present embodiments will be described, and detailed descriptions of other portions of such known components will be omitted so as not to obscure the present embodiments. Embodiments described as being implemented in software should not be limited thereto, but can include embodiments implemented in hardware, or combinations of software and hardware, and vice- versa, as will be apparent to those skilled in the art, unless otherwise specified herein. In the present specification, an embodiment showing a singular component should not be considered limiting; rather, the present disclosure is intended to encompass other embodiments including a plurality of the same component, and vice-versa, unless explicitly stated otherwise herein. Moreover, applicants do not intend for any term in the specification or claims to be ascribed an uncommon or special meaning unless explicitly set forth as such. Further, the present embodiments encompass present and future known equivalents to the known components referred to herein by way of illustration.

[0024] In general, the present embodiments relate to “Hybrid Integration of Photonics and Cryogenic Electronics with Magnetic Shielding (HIPCEMS)”, an approach for a scalable heterogeneous packaging plan that results in extreme energy efficiency information transfer at high data rates and low bit error rate of digital data between superconducting and photonic technologies in a 4K environment. Example embodiments of HIPCEMS feature a mechanically robust package that withstands thermal cycling from 300°K without performance degradation. [0025] Among other things, the present Applicant recognizes that compact magnetic shielding paves the way for a new generation of magnetic systems, such as for atomic, molecular, and optical timing and sensing devices, where long term stability of atomic sensors is desirable for timing and navigation. Also, advances in atom traps and atomic interferometry have led to chip scale atomic clocks making high precision, atomic-based timing and navigation devices more accessible (DeNatale, I. F., et al. "Compact, low-power chip-scale atomic clock." 2008 IEEE/ION Position, Location and Navigation Symposium. IEEE, 2008). Recently, the push to integrate superconducting electronic devices has generated the need for physically larger areas being protected from DC magnetic fields. This need could be approached either from a “put all superconducting circuits inside a single shield” approach or an approach which separately shields each SCE chip. The latter is the direction in which the present embodiments follow, in part because it may allow even more local magnetic shields that mitigate any influence of chip-to- chip coupling of the circuits or signal currents via local magnetic fields.

[0026] Meanwhile, further miniaturization is of high interest, but requires new concepts and technology, especially for attachment and completion of the magnetic circuits. In general, a solution is required that integrates shields with multichip modules (MCMs). It is expected that improved magnetic shielding can potentially lower the noise floor and increase the device stability and circuit margins in these high precision devices. In general, the shields that enclose the devices will consist of high permeability material that serves to redirect the magnetic flux lines and suppress their parasitic effects.

[0027] Figures 1(a) and 1(b) illustrate an example COMSOL simulation of an 11 ml field applied to a 300 pm cylindrical shell surrounding an AMO device. Among other things, the present Applicant recognizes that, while conventional electromagnetic interference (EMI) shielding simply requires a conductor 102 shown in Figure 1(a) for shielding via image charges, DC magnetic shielding requires high permeability material 104 as shown in Figure 1(b) (e.g. p _r about 8000) to provide a low reluctance path, redirecting magnetic fields around its volume. ( J. C. Wu, L. Li, J. C. Harrison and R. N. Candler, "Micro-to millimeter scale magnetic shielding," 2017 19th International Conference on Solid-State Sensors, Actuators and Microsystems (TRANSDUCERS), Kaohsiung, 2017, pp. 838-841, doi:

10.1109/TRANSDUCERS.2017.7994179).

[0028] Some embodiments of milliscale shielding utilize conventional machining to create five layers of cylindrical Amumetal shields, including a 10 mm length and 6.4 mm diameter shield with 350 pm thickness (see Donley, E. A., et al. "Demonstration of high- performance compact magnetic shields for chip-scale atomic devices." Review of Scientific Instruments 78.8 (2007): 083102). That work provided a transverse shielding factor of 1845 at 15 mT applied external field. For three concentric shields the longitudinal shielding factor was 1.9 x 10 ⁵ , and the transverse shielding factor was 5.9 x io ⁶ . However, the outermost shield had a volume of 3 cm ³ , preventing this layering technique from being integrated on-chip. Furthermore, individual wires must be threaded by hand with conventional shields, making interconnect extraction challenging. [0029] Electrodeposited magnetic shields have also been explored for shielding photomultiplier tubes (PMTs) as the trajectory of photoelectrons are altered by undesired magnetic fields. Alternating layers of nickel-iron and copper have been deposited on conductive aluminum mounts for PMTs with 130 mm length and 37 mm diameter (Dmitrenko, V. V., et al. "Electromagnetic shields based on multilayer film structures." Bulletin of the Lebedev Physics Institute 42.2 (2015): 43-47). For applied fields in the range of 0.1-0.2 mT, shielding factors of 8 to 10 were measured from approximately 500 pm of total shielding thicknesses. This method of electrodeposited shielding was applied to a large mount and was not optimized for batch device shielding used in chip-scale applications.

[0030] Alternatively, the two example types of electrodeposited shields according to embodiments allow for the compact integration of magnetic devices, including the direct integration of magnetic shielding on the device. The milliscale single layer shields provide high efficiency shielding around arbitrary shapes, and the microscale multilayer shields pave the way for the parallelized fabrication of chip-scale shielding. Overall, these shields enable total system miniaturization through conformal deposition and scalability through batch fabrication.

[0031] The HIPCEMS concept can integrate custom microfabricated magnetic shields to provide isolation of superconducting electronics (SCE) circuits/chips from each other and the external environment. Most superconducting circuits require magnetic shielding and most shields work by fully encapsulating the circuits, leaving little access for quite rigid and fragile fibers. The HIPCEMS shields according to embodiments solve this problem and others by allowing custom magnetic shield shapes to be fabricated.

[0032] Example aspects of a solution according to embodiments can be seen in Figure 2 which is representative of a multilayer fabricated shield. More particularly, Figure 2 is a cutaway illustration of an example HIPCEMS structure with integrated multi-layer magnetic shielding 202 and fiber couplers 204 according to embodiments. The actual number of shield layers are optimized by the present embodiments. An example shield as shown in Figure 2 encapsulates the entire chip 206. Electrical leads are not shown for clarity but are illustrated and discussed below.

[0033] The shield design of embodiments can depend on the particular application, and can accommodate a variety of types of interconnects and/or signal lines. For example, in an optical interconnect application, the design can depend upon whether an active (VCSEL) or passive photonic (grating/edge coupled) scheme is selected; however, it is a flexible solution that should support both techniques. The shields can be created by depositing a monolithic layer conformally in a pit that has been fabricated in a silicon substrate.

[0034] During development of embodiments, four example areas of research were performed: (I) FEA modeling of silicon-on-insulator (SOI) photonic devices. Simulation of photonic devices aims to determine optimal performance parameters for photonic devices to be fabricated in subsequent effort. (II) FEA modeling of magnetic shields to estimate the magnetic shielding characteristics of the permalloy-plated magnetic shields for a range of shield sizes and geometries. (Ill) Vibrating sample magnetometry (VSM) characterization of plated magnetic shields and magnetic shield testing at room and cryogenic temperatures are performed to validate fabricated shields and characterize shielding performance. (IV) Fabrication of two photon polymerized (TPP) test structures. Test structures are used to evaluate efficacy of TPP structure performance at cryogenic temperatures: in particular, TPP structure adhesion to substrate and size reduction at cryogenic temperatures is of interest. An area of interest is development of the TPP fabrication process. A brief summary of the work is presented below.

[0035] 1. Finite Element Analysis (FEA) Modeling of Silicon-on-Insulator (SOI)

Photonic Devices

[0036] FEA modeling of SOI devices is intended to allow optimization of power transfer/minimization of power loss from the fiber optic cabling to the Si waveguide. One example of SOI photonic circuitry according to embodiments is shown in Figure 3 and can be based on a coupler described in Gordillo, O.A.J., et al. (2019), “Plug-and-play fiber to waveguide connector,” Optics Express, 27(15), for example. Of interest is the optical performance of the photonic interconnect fabricated using TPP to which the fiber optic cabling 302 is coupled. The TPP interconnect 308 is designed to function as a total internal reflection mirror (TIR) where 1550 nm light is reflected off the angled boundary into the designed Si grating couplers 304. Simulations indicate significant optical loss will occur at the mirror 306 boundary even for optimized geometry. Further modeling suggests that metallizing the boundary with thin film silver (Ag) to serve as a reflective mirror can drastically reduce loss at the boundary. Selective metallization of TPP structures using Ag has been performed and is reported in several publications (e.g. Maruo, S., & Saeki, T. (2008). “Femtosecond laser direct writing of metallic microstructures by photoreduction of silver nitrate in a polymer matrix.” Optics express, 16(2), 1174-1179). A parametric sweep simulation was performed to optimize the Si grating coupler.

[0037] Optical loss is a notable concern at cryogenic temperatures. Estimation of the optical loss contributed by the TPP mirror is one step in characterizing the coupling efficiency from the optical fiber to the SOI circuitry. The insertion loss is estimated by measuring the input power into the fiber boundary and measuring the output power along a “dummy” line which represents the power to be coupled into the desired substrate. Note that the estimated insertion loss of the TPP mirror does not consider the loss due to refractive index differences between the TPP polymer and the chosen substrate.

[0038] Figure 4(a) illustrates an example FEA model setup for TPP mirror insertion loss estimate. Element 402 shows the boundary lines along which the total input and output lines were measured. Figure 4(b) displays the transverse E-field. Note that the refractive indices of the Si device and handle layers and SiCh BOX layer are set equal to the refractive index of the TPP mirror such that only loss from the mirror is measured.

[0039] The simulated input and output power flow densities for a TPP mirror with a 30 nm Ag layer such as that shown in Figure 4 are plotted in Figure 5. The total input power density (line 502) is 0.5896 W/m ² and the total output power density (line 504) is 0.555 W/m ² . The insertion loss of the ideal mirror is calculated to be 0.607 dB. By optimizing the grating structure, it is expected that the coupling efficiency can be made to approach 70% for the TPP coupler/grating combination. This can be realized by apodization of the grating structure as mentioned herein; however, there will always be additional losses due to fabrication tolerances in the grating. There is a coupling efficiency trade-off between a horizontally mounted fiber and the traditional near vertical mounted fiber due to the required mirror. This trade-off was deemed necessary to allow for incorporation of the magnetic shielding for grating based couplers as described below. Ultimately, the measured coupling efficiency will be determined by the fabrication quality of the TPP mirror and the grating. Surface roughness of the mirror will cause additional scattering of the input light which will degrade the coupling efficiency.

[0040] 2. FEA Modeling of Permalloy -Plated Magnetic Shielding [0041] FEA was performed using COMSOL® Multiphysics to validate the shielding performance of magnetic shields fabricated in accordance with embodiments. The aim of the simulations was to determine the internal magnetic flux density of the shield and to consider design possibilities which can ensure a sub 4 pT internal magnetic flux density. The modeling measures the internal magnetic field of the shield when subjected to an external field of 50 pT (Earth’s magnetic field). Simulations indicate the shielding factor provided by the shields will be sufficient to achieve sub 4 pT fields inside the shield when magnetic vias are added to the shield design. Additionally, FEA simulations indicate that the shielding performance of the shields improves as the shield size is decreased.

[0042] Figure 6 is a cross section of an example magnetic shield geometry for FEA modeling with COMSOL® Multiphysics according to embodiments. The example magnetic shield geometry shown in Figure 6 is a rectangular cube 602 of dimensions 10 x 10 x 3 mm ³ . The 3-layer magnetic shield 604 is comprised of two 100 pm thick permalloy layers plated onto either side of 100 pm thick copper (Cu) layer. The shield is attached to a 500 pm thick silicon (Si) substrate 606 which was chosen for simulation purposes and can be varied to match other substrates of interest (e.g. 725 pm). An additional 100 pm thick permalloy layer 608 is plated onto the bottom of the Si substrate 606. A 50 pT external magnetic field is applied for all simulations.

[0043] With the 3-layer magnetic shield and a 50 pT external magnetic field parallel to the substrate the minimum magnetic flux density (Bmin) at the center of the shield is 27.3 pT. The 27.3 pT minimum flux density exhibited by the magnetic shield is significantly higher than the maximum allowable 4 pT field. To improve the shielding, magnetic vias composed of permalloy are introduced into the shield design. Four vias 702 are added to the shield design, one at each of the corners of the shield as shown in Figure 7(a). The vias connect the magnetic shield 604 to the permalloy layer 608 beneath the silicon substrate 606. The inclusion of the magnetic vias reduces the internal magnetic field of the shield to well below the 4 pT threshold. Figure 7(b) displays an isosurface plot of the internal magnetic fields inside the magnetic shield which exceed the 4 pT threshold. Note that fields greater than 4 pT shown by region 706 are only present around the perimeter of the shield and the center is devoid of fields exceeding the threshold. Figure 7(c) displays the contour field lines for 2, 3, and 4 pT internal fields. [0044] Throughout the Phase I effort, simulations for both the in-plane and out-of-plane magnetic fields were performed. An example of simulation results is shown in Figures 8(a) to 8(d) for example in-plane and out-of-plane applied fields as illustrated in Figures 8(c) and 8(d), respectively. The white areas 802 shown inside the shield in Figures 8(a) and 8(b) represent areas where the field it less than 4 pT.

[0045] An expanded view 902 of one of the vias 702 is shown in Figure 9. One example of obtaining an optimum size and configuration of the mTSVs is described in more detail below. [0046] 3. Magnetic Shield Testing at Room and Cryogenic Temperatures

[0047] The shielding performance of the plated magnetic shields was tested at both room

(RT) and cryogenic temperatures (e g. 4°K). The magnetic shield testing setup consists of a cylindrical test magnet (DH101 from K&J Magnetics) and a magnetic Hall probe held at a fixed distance from each other using a Cu fixture.

[0048] Figures 10(a) to 10(c) illustrate an example test setup for magnetic shield testing according to embodiments. A Gaussmeter probe as shown in Figures 10(a) and 10(b) measured the magnetic field produced by a magnet. The magnetic shield is then slid over the magnet and the field is measured to determine the shielding fact of the shield under test as shown in Figure 10(c). The probe is connected to a Lakeshore DSP 475 Gaussmeter which measures the magnetic field. First, the magnetic field is measured without adding the shield. Next, the magnetic shield is slid over the magnet and the field is measured. The ratio of the field measured without the shield divided by the field measured with the field is the shielding factor. The test is repeated for the magnet at three different distances (2 mm, 6.47 mm, and 10.94 mm). Test distance between probe and magnet is adjusted by adding spacers to the Cu fixture. The Gaussmeter is zeroed with the probe held away from the test magnet before each measurement. [0049] Testing results indicate the shields successfully reduce internal magnetic fields. At RT, the tested shield exhibited a shielding factor of approximately 24. After RT testing, the shield was tested at 4°K. The testing setup was placed in a pulse tube and the RT testing procedure was repeated. After the initial 4°K measurement, the shield had cracked. 4°K testing continued and a second RT test was conducted to compare 4°K results to RT results when the shield had cracked. [0050] The results of the cryo and second RT tests are shown in Figure 11. Note that the shielding factor in both cases has been significantly reduced as shown by line 1106 due to the shield cracking. However, the test confirms that the shield factors at RT and 4°K are very similar (8.25 and 8.96, respectively). Figure 11 shows the measured magnetic field without the shield versus the magnetic field with the shield for each of the three separation distances. A linear fit of the data is shown in Figure 11 (green line 1102 (RT) and red line 1104 (4°K)).

[0051] Notable takeaways from magnetic shield testing include: (1) RT shield testing results are likely indicative of the shielding performance at cryogenic temperatures. The tested shield actually performed slightly better at 4°K than at RT. Thus, RT shield testing results may serve as good predictors of cryo temperature performance of magnetic shields. (2) Future designs of magnetic shields must be designed with considerations for thermal shock. Thermal stresses due to CTE mismatch of constituent materials are significant at cryogenic temperatures and can result in fracture as observed during this testing. Thus, future shields must be designed to reduce the likelihood of failure due to thermal stress at cryogenic temperatures.

[0052] 4 Two Photon Polymerized (TPP) Interconnects

[0053] An example method of coupling fiber optic signals to SOI circuitry according to embodiments is via a two-photon polymerized (TPP) coupler with internal reflection mirror as shown in Figure 3. TPP allows sub -wavelength resolution and precise positioning of fabricated structures. Phase I efforts have been focused on developing reliable TPP fabrication processes in order to fabricate the optical interconnects previously mentioned. Specific examples of processes and parameters of interest include: (1) determining appropriate resin chemistry for TPP interconnect fabrication. (2) Determination of appropriate fabrication settings (laser power and write-speed) to ensure photoinitiator excitation while maintaining good resolution. (3) Determining proper post-write processing of samples in order to remove unpolymerized resin from newly written structures. (4) Test of adhesion of samples to substrate (Si in this case) at low temperature.

[0054] Proof-of-concept TPP optical interconnects are presented in Figures 12(a) and 12(b). Two proof-of-concept interconnects are printed: the first shown in Figure 12(a) with the intent to accommodate an unclad fiber (~10 pm diameter) and the second shown in Figure 12(b) with the intent to accommodate a cladded fiber (-125 pm) diameter. The TPP structure quality is currently not adequate for the intended application. However, the warping/ swelling in the demonstrated TPP structures is from post-processing the written structures, not from the laser polymerization process. Thus, post-processing needs to be further developed.

[0055] 5. Related Work

[0056] Some aspects of related fabrication results are shown in Figures 13(a) and 13(b).

[0057] Figure 13(a) illustrates an example custom surface patterning tool for NIH SBIR.

Cantilever fabricated from silicon nitride with a 5pm flow channel as shown in Figure 13(b) illustrates an example custom Silicon-on-Insulator membrane with greater than 10: 1 aspect ratio holes for virus separation.

[0058] The present Applicant has produced the first-ever microfabricated magnetic shield using batch fabrication processing. As part of this related work, the present Applicant developed a custom electroplating tool for depositing high quality Permalloy, a high permeability soft magnetic material. Example results on magnetic shielding used with such a tool are shown in Figures 14(a) and 14(b).

[0059] Figure 14(a) illustrates example measured magnetic flux density inside an unshielded dummy cylinder (1402) and a 300 pm Permalloy shield (1404) and plotted against the current in the electromagnet that was used to generate the magnetic field. High shielding factor is observed up to 19 mT in the shielding region 1406 until saturation limits material permeability (1408). Figure 14(b) illustrates example measured shielding factor 1410 calculated from the plot in Figure 14(a). Error bars are shown from Gaussmeter resolution. Shielding factor decreases below 100 past 19 mT due to saturation of the Permalloy. The shield design can be optimized around a desired field level to ensure that saturation does not occur.

[0060] 6. Technical approach

[0061] The Phase I base effort showed that an example HIPCEMS approach to magnetic shielding of electronics/photonic structures and two photon polymerization (TPP) process has the potential for compatibility with cryogenic temperatures. However, in order to reduce program scope and risk, there is also a Phase I option and Phase II that will include the magnetic shielding of super conducting electronics (SCE). During the Phase I option period, it is planned to address issues related to the magnetic shields that were discovered during the Phase I base period. The Phase I effort also showed that the desired level of magnetic shielding cannot be achieved without the use of magnetic vias through the substrate. The process of creating magnetic through silicon vias (mTSVs) will be studied and evaluate the creation of superconducting multichip modules (SMCM) as well as designing superconducting electronic (SCE) chips. It will be ensured that the technology developed is compatible with existing process flows

[0062] During a Phase II effort, work was performed on integrating multilayer magnetic shields into a compatible substrate with magnetic thru silicon vias (mTSVs) that can provide the desired shielding. Also simulated were larger scale magnetic shields to determine performance parameters. Additional simulations were performed to determine shield to shield coupling, minimum spacing between SCE chips and shields, power line shielding. The appropriate SMCM and process to fabricate SMCMs for testing are used. Techniques are developed for attaching the shields to the SMCMs and characterization of the integrated packages. Previous SMCM work can be used to reduce the development risk. Shield and mTSV design will be performed with process compatibility and system-level optimization in mind (e.g. integration with fiber alignment structures where possible). The design can be optimized for integration with SMCM and flip-chip die-attach techniques. A goal of the Phase II effort was to produce a CTE-matched SMCM with integrated shielding that is capable of operating at cryogenic temperatures while enabling traditional bump bonding techniques for electrical connections.

[0063] An example HIPCEMS SMCM module with both an array of superconducting electronics (SCE) chips and shields according to embodiments is shown in Figures 19(a) to 19(c). Figure 19(a) is a top-down view of example HIPCEMS SMCM package with 3x3 array of SQUID chips (drawn to scale although enlarged for readability.) Figure 19(b) is a 3D cutaway view of integrated shields (not drawn to scale.) Figure 19(c) is a 3D cutaway view with mTSVs and integrated shielding (not to scale.)

[0064] The exact mTSV location and density will be heavily dependent upon the SCE chip and will be factored into the design of the SMCM. An integrated SMCM can be demonstrated with an array of 5x5mm SQUID array chips to measure residual field and magnetic shielding so that a program review can determine whether the program should continue. An array of shields and known field sensitive and dense circuit SCE chips can be integrated into a SMCM. Further integration and optimization of the shields during the Phase II option period can be performed the actual design and fabrication will depend on other factors. [0065] One example design flow according to embodiments

[0066] 1 Create fabrication process for HIPCEMS substrates with mTSVs that is compatible with others.

[0067] 2. Design HIPCEMS SMCM for use with SCE chips.

[0068] 3. Fabricate a test structure that incorporates magnetic shields, mTSVs and

SMCM

[0069] 4. Integrate and package HIPCEMS module.

[0070] 5 Characterize the integrated solution at cryogenic temperatures.

[0071] Another example design flow according to embodiments is as follows: [0072] 1. Design and fabricate HIPCEMS module based on third party furnished specifications.

[0073] 2. Integrate and package third party furnished superconducting electronic components.

[0074] 3. Characterize performance of packaged electronics at cryogenic temperatures.

[0075] 4. Transfer design and fabrication processes for HIPCEMS commercialization.

[0076] According to certain aspects, consideration was given to define the process flow for the mTSV fabrication according to embodiments. One example aspect is to see in what ways magnetic materials will be allowed in the fabrication facility (e.g., covered with a protective layer, not allowed at all such that all magnetic processing must be performed after fabrication. One goal of some embodiments is to find a process where fabrication does the Nb patterning in their process. One possible process flow involves fabrication including etching through holes for the mTSVs early in their process and refilling them with a sacrificial material (e.g., silicon dioxide, Nb, gold). These materials can then be etched and refill the trenches with permalloy. Another factor to discuss will be when any sensitive materials (e.g., Niobium) are deposited during the process, and if they must be passivated.

[0077] Also included in the process flow can be the permalloy on the back of the MCM. During the option, COMSOL simulations can be performed to determine if a continuous plane will be acceptable or if shield-to-shield interactions through this back plane necessitate some form of “moating” to isolate the shields. [0078] One example magnetic shield fabrication process design flow is as follows. For the shields, silicon substrates are used as the base layer. Deep reactive ion etching (DRIB) is used to define the structure. Also considered is Potassium Hydroxide (KOH) etching for defining the shield trenches. KOH trenching and subsequent electroplating can be used for another project, so the downselect for the etch method will leverage those results. It is anticipated being able to downselect to DRIE or KOH etching during Phase II. After etching, electrodeposition can be used to deposit copper and permalloy layers into the cavities, and chemical mechanical polishing to planarize the layers.

[0079] Embodiments can further include creating a SQUID array based PDK. Magnetic field suppression testing can begin with an analog operation, 5x5 mm SCE test chip based on an array of SQUIDs or SQUIFs and proximal current lines to generate the perturbing magnetic fields with the end goal of an array of such chips mounted on an SMCM to explore large areas. These are designed and then fabricated. Up to 3 5x5 mm design sites on and SFQ5EE 8 Nb layer MPW process runs are supplied to this effort. It is noted that chips containing SQUIFs have been tested, demonstrating the established ability to test these sensitive devices. The SQUID array is designed so that it will have a sensitivity of 1 pT for characterizing shield performance.

[0080] Embodiments can further include developing a shield to MCM bonding techniques. The example tools and process flow is developed to achieve quality shield to MCM bonding techniques based on In thermo-compression bonding. To facilitate this process development, a study was conducted for what GFI is available. Processes and characterized performance of the magnetic shields is evaluated based on various bonding parameters (force, time, temperature, etc.). The bonding temperature can typically be held under 80° C to ensure safety of the SCE chips. The bonding is typically a flux-less process and an epoxy underfill can be applied post-bonding in 1 pL increments. Bond strength on either test or mechanical samples will be tested by shear testing. Repeated thermal cycling at least to liquid nitrogen temperatures will be conducted to ensure proper adhesion. A FC 150 flip-chip bonding system which has ±0.5 pm placement accuracy and ±1 pm post-bond accuracy can be used. The FC150 accommodates a wide variety of materials and processes including, but not limited to, die bonding, flip chip bonding, thermocompression and adhesive bonding. [0081] Embodiments can further include optimizing magnetic shield thermal properties. In these and other embodiments, modeling and low temperature material properties is performed - from both literature and experiments - to co-optimize the shield for while considering its performance as a magnetic shield and thermal shunt, all while taking realistic design parameters (e.g., maximum thickness for electroplated permalloy and copper layers) into consideration. [0082] COMSOL is used to simulate the thermal properties of the shields. Cryogenic material properties (e.g., thermal conductivity) will be obtained from literature. In some cases such as the cryogenic thermal conductivity of our permalloy, perform experiments to obtain more accurate values if time and budget permit. The heat source can be refined to better capture the location and amount of heat generated. Additionally, if needed one can model a more complete substrate thermal interface. Initial simulations assumed a thermal ground plane on the back of the substrate under the chip. The effort will include insuring that that heat sink is compatible with the entire 3D packaging concept required. One example method for improving thermal conductivity is increasing the thickness of electroplated copper layers. One could also add copper vias in addition to mTSVs. However, the MCM thermal conductivity is generally reasonable, so one would only add the process step of copper vias if the simulations show a marked (and required) improvement in thermal conduction. It is desired that the addition of copper vias is process compatible if simulations show that this step is necessary.

[0083] An example development approach according to embodiments is as follows. [0084] A first task of the effort focuses on integrating an array of SCE chips with a central magnetic shield on a SMCM. The performance of the HIPCEMS module is characterized at cryogenic temperatures and deliver the best performing device.

[0085] COMSOL is used to simulate the minimum allowed spacing between shields. The minimum shield spacing can be defined by the spacing where shi el d-to- shield interaction prevents the interior magnetic field from being kept above 4 pT. The layout and current run through the signal lines will be dictated by the layout designed during the Phase I option and submitted for fabrication. Work is also performed to identify if additional mechanical structures will be needed to attach the shields.

[0086] Simulations performed by the present Applicant included 5 mm x 5 mm shields, which capture state the size scale for state-of-the-art chips. Looking forward to the time where the Phase II option will be ending, it is likely that chip size will have increased, likely to 20 mm x 20 mm. In preparation for this, shields are simulated that encompass 20 mm x 20 mm chips and design layer thicknesses to achieve adequate shielding for the larger chip sizes. In anticipation of increased current drives, embodiments can increase the nominal current, which is currently 3.5 A in a line 1 mm away from the shield, to a more reasonable value. Initially used is the ratio of areas enclosed by the shields to scale the current value. Also attempted is to optimize the shield sizes to minimize the footprint while still allowing adequate shielding. This should provide higher integration density for chips on the SMCM.

[0087] These simulations can provide the following information. First, they will provide initial geometries for the shields we will fabricate in Phase II. Second, they will give an indication if additional shielding around the current bias lines is needed. For the 5 mm x 5 mm chips, it is not expected there to be a need to provide additional shielding directly around the DC current bias lines. However, shielding factor decreases with increasing shield size (all else being equal), so it is possible the 20 mm x 20 mm shields will need shielding current lines even though we do not expect the 5 mm x 5 mm shields to need this extra form of shielding. In order to make the shielding relevant for future generations, devices can be simulated based on predicted state of the art (e.g., chip size and current) that could be possible at the end of the phase 2 option. If the simulations show that shielding the current lines will also be necessary, include shielded current lines in our designs. Third, the simulations will provide design guidance on the spacing of the mTSVs. For 5 mm x 5 mm shields, it is found that having four mTSVs per shield - located at the corners - provides a sufficient reluctance to allow flux to escape the top shield cap. With these simulations, we will determine how many mTSVs are required for 20 mm x 20 mm shields.

[0088] An example refined mTSV fabrication process according to embodiments is as follows. This can be a continuation of the work from the Phase I Option. The basic process from the Phase I Option can be continued, with a few additional items for consideration. In particular, a custom agitation setup can be used to improve material quality inside the vias if needed. The film quality depends on adequate agitation close to the substrate to maintain the right chemical mixture at the surface. Experience is leveraged for designing and 3D printing custom agitation fixtures for other magnetic shielding applications. [0089] Also, a dual sided plating technique can be used. This process can be used if there are issues filling the trenches because one would only have to plate halfway through from each side. Finally, the aspect ratio can be adjusted (decreased) by making wider trenches if there are issues with complete filling of trenches. Changing the aspect ratio is a simple design change. The reason for not moving to it as a first option is that it increases the fill factor of the mTSVs, which will leave less room for routing electrical interconnects. The attractiveness of adjusting the aspect ratio will become clear after the simulations from the option period are completed. For example, if the simulations show a high density of mTSVs (i.e., a picket fence) are required for the 20 mm x 20 mm shield, increasing the aspect ratio will be less attractive. If the simulations show that the 20 mm x 20 mm shield only requires sparse mTSVs, similar to the corner-located mTSVs of the 5 mm x 5 mm devices, then changing the aspect ratio will provide a possible method to alleviate challenges fdling the vias.

[0090] Since the number and aspect ratio of the mTSVs will depend heavily on the SCE chip design and power requirements, we understand that there will be trade-offs in placement and size of the mTSVs. A solution can be developed that is compatible with the high density integration requirements.

[0091] Embodiments include creating a SMCM prototype with integrated shields and mTSVs. For example, an MCM is created that will support a 3 x 3 array of SCE SQUID chips with a magnetic shield over the center SCE chip. The design should compatible with other processes and will allow integration with the shields. Once the SMCM has been designed, the SMCM with mTSVs will be fabricated.

[0092] Embodiments include designing and fabricating one or more magnetic shields over magnetic field sensors. For example, magnetic shields are designed, the shield cap layer isfabricated, and shield bonding will occur. The SQUID array SCE chips created in the Phase I Option can be used. The SQUID arrays will be arranged into a set of 3 x 3 chips for testing, as described below. That is, there will be 9 discrete SQUID array chips as shown in Figures 15(a) to 15(c). The goal of the experiment will be to show that a magnetic field less than 4 pT is maintained inside the shields. Thermal shock and vibration testing will be performed as an initial check of shield robustness. A shield will be placed on the middle die of a 3 x 3 array of chips. This will allow characterization of possible chip-to-chip coupling, and it can serve as a platform for multiple shield testing.

[0093] It should be appreciated that although mTSVs and shields are discussed in an example configuration of a shield over the middle chip in a 3x3 array of chips, with mTSVs at the corners of the shield (i.e. shielding caps), this should not be viewed as limiting. For example, the entire shield can be viewed as comprising three parts: the shield over the array, the mTSVs, and any permalloy plated on the back, rather than as separate structures. Any one or all of these components can be formed from commercial forming processes.

[0094] Embodiments include characterizing an initial HIPCEMS SMCM prototype. For example, the fully packaged article can be tested using a 4.2 K testing setup. A test plan which defines the range and details of testing can be used. Once the test plan has been created and approved, design and develop testing infrastructure and support boards/devices will be performed, as necessary, to act as a foundation for future iterations of the technology.

Functionality and performance of the prototype HIPCEMS module will be studied at 4°K. Also studied is the reliability of the prototype SMCM during thermal cycling to verify critical mTSV, shield integrity and adhesion reliability. The magnetic shielding effectiveness of the test articles are characterized and these results as well as the best performing prototype are provided. [0095] The present embodiments can be used to develop breakthrough cryogenic superconducting RF and microwave devices. These devices and systems can include some of the most efficient RF and microwave systems known and can be particularly useful for advanced and complex RF systems like SIGINT, electronic warfare (EW), advanced radar systems and quantum information processing. Most of the successfully transitioned analog parts are currently delivered in machined microwave tight boxes and suffer both signal insertion loss due to the connectors and additional fabrication/assembly costs due to their discreteness. Moving the microwave circuits onto an MCM would allow miniaturization of the total system assembly without requiring cofabrication or common materials choices. This sort of heterogeneous hybridization of analog parts will be enabled by HIPCEMS. HIPCEMS also provides an enabling technology for further adoption of SCE systems.

[0096] Some example commercialization alternatives are as follows. Superconducting systems are some of the most efficient RF and microwave systems known and are particularly useful for advanced and complex RF systems like SIGINT, electronic warfare (EW), and advanced radar systems; however, they currently require cryogenic cooling to operate. It is expected that the creation of an advanced photonic/electronic packaging scheme for cryogenic electronics/computing should allow for greater adoption of superconducting electronics and quantum information processing.

[0097] Although current quantum computers are limited in number, the trend for adoption is accelerating rapidly. Unfortunately, there are still engineering challenges to overcome for widescale adoption. The HIPCEMS technology proposed forms the basis for integrating magnetic shields into superconducting multichip module (SMCM) packaging. The combination of photonic and electronic circuits with integrated magnetic shielding would allow high-speed, low loss data communication. Conventional systems for bidirectional data transmission between room and cryogenic temperatures communicate using electrical signals, with any conversion between optical and electrical signals taking place at room temperature. This ultimately limits data rate and communication distance. In order to solve this problem, the electrical to photonic conversion must happen at cryogenic temperatures.

[0098] Quantum computing is still in its nascent form and will need numerous new technological developments to reach full commercialization at desired scales. HIPCEMS technology combines attributes of additive manufacturing and standard microelectronic fabrication. Given the development pathway for quantum information systems, it is expected that custom application specific packages will be required at first with the eventual adoption of industrial standards. It is understood that elements of the HIPCEMS technology such as the magnetic shielding or optical interconnect scheme may have advantages in other applications and will be licensed separately.

[0099] Although the present embodiments have been particularly described with reference to preferred examples thereof, it should be readily apparent to those of ordinary skill in the art that changes and modifications in the form and details may be made without departing from the spirit and scope of the present disclosure. It is intended that the appended claims encompass such changes and modifications.