Field of the invention

The present invention relates to auxiliary memory system of a computer.

5 This invention when host computer access the necessary data from disk memory having relatively the large capacity , in particular, relates to, what we call, the computer mirror disk RAM system which can react directly to access from the host computer by being estabilished the mirror disk lβ RAM which has same capacity as above - mentioned disk memory, and in which the data within the disk memory can be stored automatically just like mirror, so we call it the mirror disk RAM, and then making this mirror disk RAM the host computer's own memory.

15 Background of the invention

In the auxiliary memory device in general computer system, we ordinarily use the disk device operated by means of only mechanical means in accessing the necessary data and, above mentioned disk device is widely used in the respect that it 2β can store relatively large capacity memory.

In the computer system which use above-noted disk device as auxiliary memory device, however, the necessary data process required form all sorts of terminals which are connected with host computer is supplied according to time - sharing and 25 the process operation toward above-mentioned terminals is carried out by applying the necessary data as data after accessing necessary data from disk device under the above-mentioned host computer's control.

According to prior art to be known until now, it 36 takes so much time for host computer to access the necessary data because of using the disk device operated mechanically.

In here, the time for accessing mechanically is measured by ras unit.

Therefore, the prior computer system is unsuitable for 35 use because that its processing speed is low from the view of

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the efficiency and ability of the computer, which processing speed is shown in nano-sec unit.

So to speak, because that the necessary data exists within the round nagnβtic disk, the data process is carried out for the terns of accessing the track section and the appropriate zone, in one word, by ■echanicai nethod, then reading the data and then writing it.

So, according to the above method, computer's data process speed is very low from the point of computer's view.

As above-mentioned, this time increase for data accessing has remained as problem because that it raised the bottle-neck phenomenon all over the whole computer system.

Summary of the invention.

The purpose of this invention is to provide the novel computer mirror disk RAM system which can enhance processing speed excitingly by being estabilished mirror disk RAM which has the same content as memory disk and then providing the technical means by which mirror disk RAM and host computer become a integrated electric system.

The another purpose of this invention is to provide

MDRS (Mirror Disk RAM system) which can cope with the variation of _. disk capacity used in computer system easily in the method that MDR (Mirror Disk RAM) can plan the capacity value variably and alternatively in proportion to the memory capacity of disk memory because of including the memory element and micro computer within the MDR itself.

In particular, a distinctive feature of this invention is MDRS including at least micro computer and RAM, both of which alternatively control above-noted necessary circuit bloc in response to call from the host computer or micro computer which have ability to transfer the content from Disk memory to MDR just like mirror automatically, and back up the updated contents onto disk memory when the work of host computer ended up.

Brief description of the drawings.

Fig. 1 is the schematic block diagram of this invention.

Fig. 2 is more embodied block diagram of this invention in Fig. 1

Fig. 3 shows the preferred embodiment of the logic control circuit in Fig 2.

Fig. 4(a) shows the flow chart about main program carried out within the micro computer of this invention.

Fig. 4(b) shows the flow chart about interrupt program carried out within the micro computer of this invention,

Fig. 5 shows the practice example of utilizing the micro computer, the mirror disk RAM, and the disk memory in this invention,

Fig. 6 shows the program example of MDR's operation could be carried out by the another software in this invention.

The sign explanation of the drawings.

lθ. Mirror Disk RAM stste

1. Micro computer 2. Logic control circuit

3. Mirror disk RAM (MDR) 4. State RAM

51,52. 1,2 main switch part

61,62. RAM selected 1,2 switch part

Best node for carrying out the invention.

Reffering to Fig. 1, it shows the bloc diagram illustrating the gist of this invention.

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In here, MDRS(IB) exist between the host computer(HC) and disk memory(7).

This MDRS(l ^β ) takes the method that when host computer (HC) access the disk memory(7), the host co puter(HC) can access directly the data because that the exactly same memory corres¬ ponding to the contents memorized within disk memory(7) is stored in MDR(3), and when the operation of host computer(HC) ended up, updated data on the part of MDR(3) is backed up onto disk memory(7).

Reffering to Fig. 2, it shows the above-noted MDRS(lβ) of this invention more concretely .

In here, MDRS(lθ) is represented in connection with the host co puter(HC), and disk memory(7), while inside the HDRSC18) show the reciprocal relation among the state RAM(4), micro computer (1), logic control circuit(2), 1,2 main switch part(51,52), RAM selected 1,2 switch part(61,62), and HDR(3) which has same capacity as disk memory(7).

Above-mentioned MDR(3) is composed of the plural number of RAM (Randon Access Memory ) elements that has the capacity as same as disk memor (7).

Micro computer(l) in this MDRS has the processing program to write all memory contents of disk MEM0RY(7) on MDR(3) and back up updated contents produced by computer's use for MDR(3) onto the disk memory(7) and control the logic control circuit(2), haviy the ability to control for state RAM(4), 1,2 main ^' switch parts(51,52), and RAM selected 1,2 switch part(61,62) and, above-mentioned state RAM (4) and MDRC3) are constructed respectively in concert with access both from micro computer(l) and from host computer(HC) through 1,2 main switch part(51,52). .

And, the access request line(AR) is connected with above- noted logic control circuit and the access acknowledge line by way of this logic control circuit(2) is connected with Access- Acknowledged) of host computer(HC).

On the other hand, above-mentioned logic control circuit (2) is consisted of the following conditions.

It is logical condition that when micro computer(2) works at transferring the memory contents from disk memory(7) to HD (θ), 2 main switch part(52 ⁾ between the host co puter(HC) and state RAM (4 ⁾ , MDR(3 ⁾ is turn off, 1 main switch part(51) is turned on, while when host computer(HC) reguests to access the MRDS(IB), 2main switch part (52) is turned on, 1 main switch part(51) is turn off, and when micro computer(l) back up the updated memory produced by host co puter(HC) use for MDR(3), RAM selected 2 switch (62) is turned on, RAM selected 1 switch(61) is turned off, 1 main switch part(51) is turned on, 2 main switch part(52) is turned off, and tnat the application sign on the part of the host computer(HC) is transmitted to micro computer(l), the host computer's use for MDR(3) is approved and sign of access-ending is trans¬ ferred to micro computer(l) when the host computer(HC) use the MDR completely.

Those skilled in art take as a matter of course that if above-noted logic control circuit(2) is to meet the condition as above, any kinds of logic construction is all right.

On the other hand, referring to Fig. 3, it shows the example of above logic control circuit(2).

Above-mentioned logic control circuit(2) is briefly constructed including the Inverter, 2,3 flip floρ(22,23) which alternatively control RAM selected 1,2 switch(61,G2) and 1,2 main switch part(51,52) and 1 flip flop(21) which is connected with between 10 port of micro computer(l) and access Reguest line(AR) on the part of host computer(HC).

This logic control circuit(2) performs the necessary switching control, namely, 1,2 main switch part(51,52) and RAM selected 1,2 switch part(61,62) when micro computer enables host computer(HC) to use MDR(3) by loading the contents of disk memory (7) onto the MDR(3) in case that host computer(HC) requests to access and afterward back up the updated contents of MDR(3) onto disk memory after checking the update bloc.

And, above-noted state RAM(4) is used as instrument which supports the disk memory(7) and MDR(3) to take same contents.

Namely, in the first step when the data is loaded from disk memory(7) onto MDR(3), the value zero is writtened in the bit of state RAM because that the state RAM's(4) bit corresponding to the bloc of Disk memory (7) and MDR is designed to have the value 8 when data by bloc of disk memory(7) and MDR(3) is same.

Now here, disk memory(7) treat the data by bloc unit, and state RAM(4) has same number of bit as the bloc number of MDR(3) and disk memory(7).

But, when some bloc of MDR(3) is updated by host computer (HC), the value I is writtened automatically on the corresponding bit of state RAM(4) which indicates the address of bloc, hereafter the micro computer(l) can know updated bloc address on the part of MDR(3) by serching for the state RAM(4) when host computer(HC) ended up the access for MDR(3) and then enable the MDR(3) and disk memory(7) to take same contents by backing up the data onto disk memory(7).

On the other hand, Fig. 5 shows the interrelation among the micro computer(l), disk memory (7) and 1, 2 main switch part (51,52) in detail. As Fig. 5 shows, the micro computer(l) is composed of

MPϋ(ll), R0MQ2), RAMU3), and 10 port(14), and the address bus(AB, ), while data busCDB, ), and 10 port(14) on the part of the micro computer are respectively connected with 1 main switch part(51) and the other side, of above - mentioned 10 port(l4) is connected with disk memory (7).

And, this micro computer(l) is connected with address bus (AB _t ), data bus(DB- ) and READ and WRITE(R/ ) line through the above- mentioned 1 main switch part(51), and this address bus(AB, ) and data bus(DB,) ere in common connected with 2 main switch part(52) with another READ and RITE(R/K) line.

In the midst of the address line, address bit on the part of state RAM(4) is used as memory bloc address line which is controlled by MPϋ(ll) of micro computer(l).

And, the half of the MPD's address of the above mentioned micro computer(l) can be used as the address on the part of micro computer(l), and the rest can be used as the address for MDR(3).

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This invention's effect and processing procedure is as below.

Namely, in being power on, first MDRS(lθ) of this invention load the data memorized within the disk mcmory(7) onto MDR(3) automatically as Fig. 1 shows.

At this time, micro computer(l) carry out the works according to the program as Fig. 4(a).

Namely, the micro computer(l) turns on the 1 main switch part(51) through the logic control circuit(2) and then turn on the RAM selected 1 switch part(61).

After this, the micro computer(l) carry out the data storing operation through ROUTINE, and at this time the data memorized within the disk memory(7) is stored into MDR(3) as it is.

Accordingly, the above-mentioned MDR(3) is exist in the form of volatile memory and the disk memory(7) exist in the form of non-volitile memory.

When the above-mentioned operation ended up, the micro computer(l) enters the interrupt-enable state and hereafter RAM selected 2 switch part(62) is turned on, at this time micro computer(l) examine whether the dirtied bit namely value 1 within the state RAM(4) exist or not.

Micro computer(l) after checking the state RAM(4) continually as above, transfer the updated contents from the MDR(3) to micro computer's buffer by turning on the RAM selected 1 switch(61) and then continually carry out the operation of transfer the data from buffer to disk memory(7) after conforming that whether the buffer find out completely the corresponding bit of state RAM(4) or not.

On the other hand, in case of the interrupt-enable during the above-mentioned process, interrupt program is carried out within the micro computer(l) as Fig. 4(b).

Namely, as to interrupt request, when host computer(HC) access the data within the disk memory(7), first interrupt sign

is transferred to the logic control circuit(2) and from this logic control circuit the interrupt request is transmitted on the part of the MPU(ll) of micro computer(l).

After above-noted interrupt request, the MPU according to its own interrupt program turn on the 2 main switch part(52) and turn off the 1 main switch part(51), and in addition check whether the host computer(HC) use the MDR(3) completely or not after conforming if the buffer within the micro computer(l) is still emptied, at this time, if emptied, instantly, and if not, after writing the contents of buffer on the disk memory(7).

When the access operation on the part of the host computer

(HC) ended up as above, 1 main switch part(51) is turned on through the logic control circuit(2) which is manipulated by the micro computer(l), and at this time 2 main switch part(52) is turned off automatically.

Hereafter, RAM selected 2 switch part(62) represented in the Fig. 2 are opened, and the works related to the above- mentioned state RAM(4)'s operation are carried out.

And, when the contents of the above-mentioned MDR(3) are eraesd out, for example, by power off, the micro computer l) carries out automatically the first operation that memory contents within the disk memoryd) is transfered to MDR(3).

On the other hand, Fig. 6 shows the another program by which above-noted funtion could be carried out, what we call, by polling method on the part of micro computer, not by the program according to the interrupt request through logic control circuit(2).

It is used in the case that from the view of micro processor unit's structure .the interrupt process is in trouble owing to allocating the half of memory address for MDR(3) as this invention shows.

Now here, the micro computer loads the data of the disk memory(7) onto MDR(3) by turning on the 1 main switch(51) and RAM selected 1 swϊtch(61).

After this, micro computer directly read the contents of the host computer's application for MDR(3) as 10 port(14), and then if the application for use came in, carry out the applied routine, and if not, perform the routine of writing the MDR's data bloc updated by host computer on the disk memory by way of finding out it after checking on state RAM(4).

When the application for the host computer's use came in, the disposal routine is that first micro computer(l) enables the host computer to access the MDR(3) by turning on 2 main switch (52) and then check and see if the data to write on the disk memory(7) is still remained in the buffer, and if remained, write on the disk memory(7), and finally check and see if the use of MDR(3) ended up by reading the applied Flip Flop of the MDR (3)

If not ended up, micro computer(l) repeat the checking until it ends, and if ended, proceed the routine by which the micro computer(l) backs up the data updated by host computerOIC) onto the disk memory(7).

As for the disposal routine when the host computer(HC) doesn't access the MDR(3), the micro computer(l) turn on the 1 main switch(51) and the RAH selected 2 switch(B2) and after checking the data whether the updated data exists or not by way of reading the state RAMU), if updated, transter the bloc of MDR(3) to the Buffer by turning on the RAM selected switch(Gl).

If the buffer is found to be filled full, the micro computerOIC) enables the host co puter(HC) to utilize the MDR(3) during the time which the micro computer(l) writes it on the disk memory(7) by turning on the 2 switch(62) and hereafter enter the process to read the flip flop of the RAH use application.

In addition, reffering to Fig.5,

We should be known the method of using the micro computer(l)'s address against the relative large capacity address of the MDR(3).

As to the remaining bit, by using it as the address of the above-mentioned address bloc, it would be quite possible to make direct call the address of the HDR(3) on the part of the micro computer(l), and response to the capacity increase of the MDR(3) as the address being given to the outport select each part of the HDR(3).

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And the memory contents of disk memory (7) is put into the above-mentioned MDR just like mirror, and when the host computerCHC) calls up the above-noted disk memory(7), it is possible to make a direct response electrically.

And so, its disposal work shall be done at the same speed as the electronic semi-conducted memory element on the part of the host computerCHCL

As a result of it, we can expect to gain maximum funtions and efficiency.

Speaking of this invention's character, it will guarantee the huge funtions and the efficiency of computer system, for in the computer system(lθ) of utilizing the disk, the means of drawing out can be provided fay MDRS responding electrically when the host co puter(HC) access the disk memory in the computer system.