MIS FIELD-EFFECT TRANSISTOR

The present invention relates to transistors. The invention finds particular application in CMOS transistors.

High voltage (HV) CMOS processes can be integrated with lower voltage components. For the purpose of this specification the term "high voltage" is preferably intended to mean voltages of 6V or more, and it will be appreciated that the term "high voltage" may cover a range of up to several hundreds of Volts or more.

When high voltage CMOS processes are integrated with lower voltage components problems can arise at the interface between high and low voltage capability. The lower voltages, when applied to the gate region, should be able to switch higher voltages at the drain. This may be accomplished using a CMOS process, where the channel region of a high voltage device is formed using a thin gate oxide under the polysilicon gate but the drain part of the transistor is made using a thicker oxide (e.g. field oxide).

The present Inventor has appreciated that some problems may be associated with the above technique: If the thin oxide is continuous/of uniform thickness then the termination of the well zone will mean that the surface part of the drift region is doped with the threshold adjust implant (boron in the case of HV-NMOS). The presence of the p-type surface region disconnects the channel from the HV drift region and this causes the device to malfunction.

The present invention aims to address this problem. In order to achieve a functional layout of the transistor with thin gate oxide channel the present Inventor has devised a transistor with a gate dielectric region formed adjacent to the channel which is of intermediate thickness. This region is adjacent to a thicker oxide which is used to create a high voltage drain zone.

Accordingly, in one aspect the present invention provides a transistor comprising: a body; a source;

a gate; a drain; a gate dielectric layer for isolating the gate from the body; and a well region at least partially extending under the gate to create a channel region; wherein the gate dielectric layer comprises a thinner and a thicker portion, and wherein the well region does not reach the area covered by the thicker portion of the gate dielectric layer.

Although in the previous paragraph reference is made to "a thicker portion", this is intended to refer to the layer of intermediate thickness. This layer of intermediate thickness is thicker than the "thinner portion".

Preferably, the dielectric layer comprises an oxide layer.

In preferred embodiments the creation of a thin oxide to medium oxide transition zone helps a high voltage NMOS device to have the correct electrical behaviour. This device may then have a low threshold voltage, high drive current with low gate bias and also high voltage drain capability.

Some preferred embodiments of the invention will now be described by way of example only and with reference to the accompanying drawings, in which:

Figure 1 shows a sectional view of a transistor according to an embodiment of the present invention.

Figure 2 shows a plan view of the layout of the transistor of Figure 1.

The features shown in Figs. 1 and 2 are as follows:

1. Metallisation connection

2. Interlay er dielectric

3. Contact metal

4. Heavily doped p+ diffusion.

5. Lightly doped p- diffusion ; p-well, body

6. Lightly doped n- diffusion ; deep n-well

7. Lightly doped p- diffusion ; deep p-well

8. Field oxide dielectric

9. Metal suicide

10. Heavily doped polysilicon gate

11. Medium (thicker) gate dielectric

12. Thin gate dielectric

13. Heavily doped n+ diffusion

14. P-substrate

B Base connection

S Source connection

G Gate connection

D Drain connection

Referring to Figures 1 and 2, the lightly doped p-well 5 extends under the source and also partially under the gate 10. The lightly doped p-well 5 is located within lightly doped deep n-well 6. As can be seen in particular in Figure 1, the gate 10 is isolated from p-well 5 and n-well 6 by means of a dielectric layer 11, 12. This has a thinner portion 12 and a thicker portion 11. Although thicker portion 11 is thicker than the thinner portion 12, its thickness is still much less than the thickness of the field oxide dielectric 8, which defines the drain region. The thickness of the thicker portion 11 may for example be between 12nm and 200nm, between 12nm and 150nm, between 12nm and 120nm, between 12nm and lOOnm and preferably between 20nm and 80nm. Good results have been achieved with a thickness of 40nm. The thickness of the thinner portion 12 may for example be between 2nm and 50nm, preferably between 4nm and 20nm. Good results have been achieved with a thickness of about 7nm.

The double-arrow in Figure 1 indicates the channel region. It is formed where the gate 10 overlaps with the p-well 5. The deep n-well 6 defines a drift region. As can be seen in Figure 1, the transition from the thinner portion 12 to the thicker portion 11 is above

the drift region and not above the channel region. Expressed differently, the p-well 5 does not reach the area covered by the thicker portion 11.

With a thin to medium oxide step, the channel can interface to the drift region which is immediately under the medium oxide 11. This region does not have any surface p-type zone. Thus the channel can be effectively connected to the drain drift region. With the arrangement shown in the drawings the transistor channel region terminates before the drift region begins.

The p-well region 5 should be positioned carefully with respect to the thin-medium oxide interface, since the p-well 5, if it extended under the medium oxide 11, would normally cause the threshold voltage of the device to rise to unacceptable levels. This would also be true if the p-well 5 extended all the way over to the field oxide part 8. In preferred embodiments the magnitude of the threshold voltage can be kept below 3 V, preferably below 2V, more preferably below 1.4V and yet more preferably below 0.5V. It could be as low as substantially OV.

The p-well 5 is kept slightly back from the thin-medium oxide (12,11) join region. It terminates in the thin oxide area. As a result, the channel region inverts at a suitably low threshold voltage and can still effectively connect to the drain drift region which starts under the medium gate oxide 11 and proceeds under the thicker field oxide region 8 - eventually terminating in the drain region.

In principle, the (in Figure 1 rightmost) edge of the p-well 5 could be located precisely under the transition from the thinner portion 12 to the thicker portion 11. However, with currently available manufacturing processes and their tolerances it is best to design the device such that the edge of the p-well 5 is kept a certain distance back from the transition, for example 250nm, depending on manufacturing tolerances. This would ensure that despite slight misalignment the p-well 5 does not reach the area covered by the thicker portion 11.

The thicker portion 11 may have the effect that it prevents implant, which may be used during manufacture of the transistor, from entering the material below the thicker

portion 11, or at least reduce the amount of implant entering the material below the thicker portion.

It will be appreciated that the transition from the thinner portion 12 to the thicker portion 11 can be any suitable shape. Whilst a step as shown in Figure 1 is preferred for ease of manufacture, a gradient or similar may also be suitable.

Whilst the above embodiment has been described with reference to an oxide layer 11 , 12, it will be appreciated that this layer does not have to be an oxide layer but could be any other dielectric layer.

Also, whilst it is preferred that the edge of the well 5 does not reach the area covered by the thicker portion, it would alternatively be possible for the edge to reach the area covered by the thicker portion. However, this edge should be kept away from any field region.

It will further be appreciated that all polarities mentioned above could be reversed, the resulting devices still being in accordance with the present invention.

In the present specification some directional or positional terms (such as "above" or "covered by") have been used. These are to be interpreted in accordance with what is shown in Figure 1, but it will be appreciated that the claims are not limited to devices which are in the same orientation as the device shown in Fig. 1.

Some claims refer to the term "drain edge". Whilst the meaning of this term is believed to be clear to one skilled in the art, in order to provide further guidance it is noted that in Fig. 1 the drain edge would be at the left-hand side of the thick field oxide dielectric 8 which is located to the left of the heavily doped n+ diffusion 13 and the metal suicide 9 of the drain.

Although the invention has been described in terms of preferred embodiments as set forth above, it should be understood that these embodiments are illustrative only and that the claims are not limited to those embodiments. Those skilled in the art will be

able to make modifications and alternatives in view of the disclosure which are contemplated as falling within the scope of the appended claims. Each feature disclosed or illustrated in the present specification may be incorporated in the invention, whether alone or in any appropriate combination with any other feature disclosed or illustrated herein.