Title:
MIXER CIRCUIT AND VARIATION SUPPRESSING METHOD
Document Type and Number:
WIPO Patent Application WO/2011/058863
Kind Code:
A1
Abstract:
Provided is a mixer circuit for solving the problem that a circuit becomes very complicated in order to compensate the amplitude error and the phase error. A voltage current conversion unit (11) converts an RF signal, which is a voltage signal, to a current signal, and outputs the current signal. An RF path selection unit (12) connects its input terminal to any of its output terminals in accordance with the status of a four phase clock signal, and separately outputs, from its output terminals, a plurality of IF signals obtained by multiplying the RF signal by clock signals in the four phase clock signal. An IF path selection unit (13) switches the connection relationship between its input terminals and its output terminals in accordance with a selection signal (S), and outputs the IF signal input to each of its input terminals to its output terminal connected to the input terminal.
Inventors:
KITSUNEZUKA MASAKI (JP)
Application Number:
PCT/JP2010/068730
Publication Date:
May 19, 2011
Filing Date:
October 22, 2010
Export Citation:
Assignee:
NEC CORP (JP)
KITSUNEZUKA MASAKI (JP)
KITSUNEZUKA MASAKI (JP)
International Classes:
H03D7/14; H03D7/00; H03D7/12
Foreign References:
| JP2008118474A | 2008-05-22 | |||
| JP2003060441A | 2003-02-28 |
Attorney, Agent or Firm:
MIYAZAKI, Teruo et al. (JP)
Akio Miyazaki (JP)
Akio Miyazaki (JP)
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