Title:
MIXER CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2005/053149
Kind Code:
A1
Abstract:
A mixer circuit of a receiving system that must have a low noise characteristic for a low frequency, wherein a bypass current source (41) is connected, in parallel with an LO transistor (21), between an IF output terminal (33) and the drain terminal of an RF transistor (11), and a bypass current source (42) is connected, in parallel with an LO transistor (22), between an IF output terminal (34) and the drain terminal of the RF transistor (11), whereby the currents flowing through the LO transistors (21,22) can be reduced without reducing a bias current flowing through the RF transistor (11). In this way, a mixer circuit is provided in which flicker noise occurring from the LO transistors (21,22) can be reduced without reducing the mixer gain, the NF characteristic for a low frequency can be improved, and an excellent low frequency/noise characteristic can be achieved.
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Inventors:
HIJIKATA KATSUMASA
HAYASHI JOJI
HAYASHI JOJI
Application Number:
PCT/JP2004/016938
Publication Date:
June 09, 2005
Filing Date:
November 15, 2004
Export Citation:
Assignee:
MATSUSHITA ELECTRIC IND CO LTD (JP)
HIJIKATA KATSUMASA
HAYASHI JOJI
HIJIKATA KATSUMASA
HAYASHI JOJI
International Classes:
H03D7/00; H03D7/14; (IPC1-7): H03D7/00; H03D7/14
Foreign References:
| JPH04129407A | 1992-04-30 | |||
| JPH07254821A | 1995-10-03 | |||
| JP2001522566A | 2001-11-13 | |||
| JPH0969730A | 1997-03-11 | |||
| JP2004104515A | 2004-04-02 |
Attorney, Agent or Firm:
Hayase, Kenichi (4F, The Sumitomo Building No.2, 4-7-28,
Kitahama, Chuo-k, Osaka-shi Osaka, JP)
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