MONOLITHIC ARRAY OF SEMICONDUCTOR DEVICES, TEMPLATE WAFER, METHOD OF MANUFACTURING A TEMPLATE WAFER, AND METHOD OF MANUFACTURING AN ARRAY OF SEMICONDUCTOR DEVICES

The invention relates to a monolithic array of semiconductor devices on a wafer, a display device comprising the monolithic array, a template wafer and a method of manufacture. In particular the invention relates to a monolithic array of optoelectronic semiconductor devices, high electron mobility transistor devices, or radio frequency devices, formed on a template wafer comprising an array of porous regions.

Background lll-V semiconductor materials are of particular interest for semiconductor device design, in particular the family of Ill-nitride semiconductor materials.

“Ill-V” semiconductors include binary, ternary and quaternary alloys of Group III elements, such as Ga, Al and In, with Group V elements, such as N, P, As and Sb, and are of great interest for a number of applications, including electronics and optoelectronics.

Of particular interest is the class of semiconductor materials known as “Ill-nitride” materials, which includes gallium nitride (GaN), indium nitride (InN) and aluminium nitride (AIN), along with their ternary and quaternary alloys. (AIJn)GaN is a term encompassing AIGaN, InGaN and GaN. Ill-nitride materials have not only achieved commercial success in solid-state lighting and power electronics, but also exhibit particular advantages for quantum light sources and light-matter interaction.

While a variety of Ill-nitride materials are commercially interesting, Gallium nitride (GaN) is widely regarded as one of the most important new semiconductor materials, and is of particular interest for a number of applications.

The present invention will be described primarily by reference to GaN and InGaN, but may advantageously be applicable to alternative Ill-nitride material combinations.

It is known that the introduction of pores into bulk Ill-nitrides, such as GaN can profoundly affect its material properties (optical, mechanical, electrical, and thermal, etc.). The possibility of tuning a wide range of material properties of GaN and Ill-nitrides semiconductors by altering its porosity therefore makes porous GaN of great interest for optoelectronic applications. The present inventors have also found that by using porous Ill-nitride material as a substrate, or template, for overgrowth of additional semiconductor layers and semiconductor devices, beneficial properties such as strain relaxation may be imparted to the overgrown devices by the porous layer. Following overgrowth of the desired semiconductor devices, however, it may be desirable to remove the semiconductor devices from the porous template, and to transfer the semiconductor devices to another carrier for fabrication into an electronic or optoelectronic device. It is an aim of the present invention to facilitate the safe and reliable removal of a semiconductor device from a substrate on which it has been grown.

In the present invention, regions or layers of semiconductor material may be porosified by electrochemical etching as set out in international patent applications PCT/GB2017/052895 (published as WO2019/063957) and PCT/GB2019/050213 (published as WO2019/145728).

Problem to be Solved

Integration of different semiconductor devices, or components, into integrated end products, is a significant challenge in device fabrication.

In order to fabricate integrated semiconductor devices, in which multiple semiconductor devices of different types (for example multiple LEDs which emit different colours) are integrated onto a single device chip, it is typically necessary to grow the different semiconductor devices separately on their own template wafers, frequently using different semiconductor materials. The different semiconductor devices may then be removed from their growth templates and integrated onto a shared carrier wafer before processing the shared wafer into an end-product. For example it is frequently desirable to integrate multiple different LED types, which emit at different peak emission wavelengths, onto a single carrier wafer for fabrication into a multi-colour display device.

In order to avoid the complexity and cost of the separate growth, transfer and integration steps, it would be highly desirable to manufacture all of the required semiconductor devices monolith ically, that is, on the same wafer template. Following epitaxial growth of the different semiconductor devices on the wafer, the required devices would thus already be positioned in the desired location on the shared wafer, where they are required to be for processing into an end-product. This would eliminate the need for the separate devices to be grown separately and transferred onto the shared wafer, and would therefore speed up device fabrication and reduce cost and complexity.

No viable monolithic integration method is yet commercially available for display applications or other light-emitting applications, because conventional Ill-nitride LEDs (standard LED, Mini-LED, Micro-LED, Nano-LED) can normally emit one colour at a time. This means that for a multi-colour light-emitting device, multiple single-colour LEDs, which have different epitaxial structures and are often formed from different semiconductor materials, have to be manufactured separately and then integrated onto a shared wafer.

For “large” (not mini, micro, or nano) LEDs, there are packaging innovations whereby three individual LEDs which emit red (R), green (G), and blue (B) can be packaged in a single die or package, or three packaged LEDs of R,G,B are mounted on the same PCB or circuit board. Such red, green and blue LEDs can be made from the same material system or different material systems. For example, the red, green and blue LEDs may be GaN-based or AllnGaP based, or GaAs based.

For Mini-LEDs, similarly to “large” LEDs, different colours of mini-LEDs may be packaged together using mass transfer or pick & place techniques, in which LED chips of different colour are integrated, mounted, or packaged on the same circuitry in a single die.

For MicroLEDs, due to the small sizes of MicroLED and the required pixel density, none of the above mentioned packaging, mounting or mass transfer/pick&place methods work well with reasonable yield and cost effectiveness.

The key problem is that one LED epitaxy, or one LED chip, can conventionally only produce LEDs which emit one colour, and heterogenous integration of multiple separate chips is already difficult and complex. Added to this, red and blue-green LEDs are typically grown from different semiconductor materials, which require different lift-off processing and make integration of different colours difficult.

Efforts have been made to get all three colours RGB (red, green and blue) LEDs demonstrated on the same substrate/wafer, namely using:

1 . Selective area epitaxy or nanowire/nanorod/nanopyramids/nanoplalets method - either by varying the size of the mask/window (usually dielectric material as the mask, SiO ₂ or SiN _x ) opening to confine a selective area for the LED epitaxy, and control the size of the nanostructures, hence the MQW and ln% on the sidewall or surface of the nanostructures is controlled to emit different colours.

2. Stacking method, which uses either vertical stacking or lateral stacking:

Vertical stacking - R,G,B LEDs (of any size) were fabricated (and R,G,B LED epitaxy/material can be obtained from same or different material systems), LEDs are processed and singulated, also the original substrate is lapped and polished, and thinned, and removed. Each colour of the LEDs are then stacked one on top of another to form a pixel. This process is very complex and yield is very low, considering all R,G,B LED epitaxy must done on foreign substrates, and the active LED pn junction is a very thin layer. These drawbacks make this method unfeasible for commercial device fabrication. In addition, this technique creates a problem with absorption of the light emitted by the LEDs, because the way the R,G,B LEDs are stacked vertically can cause problem for the optical performance and cross-talk of different pixels. Each colour LED has completely different optical and electrical characteristics, and each LEDs needs its own electrical contacts, making this technique even more difficult. Overall, the vertical stacking integration process is extremely complex and may be unsuitable at least for display applications.

Lateral stacking - In lateral stacking integration, somewhat similarly to mass transfer processes, each R,G,B LED will need to be stacked/transferred side-by-side in a sub-pixel format laterally, one colour after another. This technique leads to the same problems with complex processing, low yield, and drawbacks created by combining different LEDs having different characteristics.

The monolithic integration of RGB LEDs on the same wafer therefore faces a number of challenges, and require improvement in several ways. Yield loss in existing techniques creates a high manufacture cost. It would be desirable to create monolithically integrated devices using a simple epitaxy, with no transfer/stacking/selective area epitaxy required, as this would result in lower cost and higher yield of integrated end-products. High performance is required for display applications, as well as colour uniformity. For display applications, system integration and power management it would also be highly beneficial for the different semiconductor devices on the integrated wafer to have similar optical and/or electrical characteristics. It is an aim of the present invention to address these issues, and to provide a method of manufacture with high yield and simple processing throughout the entire display fabrication process.

To simplify LED manufacturing processes and reduce mass production cost, Poro Technologies has released LEDs featuring embedded nanoporous architecture, which enables GaN-based LEDs to output full color range. These LEDs are described, for example, in international patent applications PCT/GB2021/050152 (published as WO2021/148808) and PCT/GB2021/052020 (published as WO2022/029434).

Summary of Invention

In the present invention, an embedded patterned nanoporous architecture enables monolithic integration of multiple different semiconductor devices on a single wafer. For example the present invention enables monolithic integration of multiple LEDs having different emission colours (different peak emission wavelengths) on a single semiconductor wafer.

The present invention is defined in the independent claims, to which reference should now be made. Preferred or advantageous features of the invention are set out in the dependent sub-claims.

In a first aspect of the present invention there is provided a monolithic array of semiconductor devices on a wafer, comprising: a first semiconductor device occupying a first device area on the wafer directly above, or over, a first porous region in the wafer, the first porous region having a first structure, first porosity and first dimensions; and a second semiconductor device occupying a second device area on the wafer. The first and second semiconductor devices may have the same epitaxial semiconductor device structure, and the second semiconductor device is not positioned over a porous region having the same structure, porosity and/or dimensions as the first porous region.

The first and second semiconductor devices may have the same epitaxial device structure but respond differently in response to the same driving conditions. The first and second semiconductor devices may have the same layered structure. The presence of underlying porous regions of semiconductor material may affect the composition of overgrown devices, for example by altering indium incorporation (or incorporation of other elements) into the device active regions that are positioned over a porous region during epitaxial growth of the devices. Thus the chemical composition of the active region in the first semiconductor device may differ slightly from the chemical composition of the active region in the second semiconductor device, even when both devices are formed in the same epitaxy. The porous region may also affect layer thicknesses in the device active regions, such that the layer thicknesses vary slightly between the first and second semiconductor devices.

As described further below, the first and second semiconductor devices are preferably formed on the wafer simultaneously, using a single epitaxial deposition process, such that both of these semiconductor devices are formed with identical epitaxial structures. Thus the number of layers, layer thicknesses and layer compositions of the device structures are preferably identical for the first and second semiconductor devices.

The lateral shapes and dimensions of the first and second semiconductor devices may differ from one another, as the first device are may differ from the second device area in size and shape.

As the wafer design under the first and second semiconductor devices is different, the characteristic electronic and/or optical properties of the first and second semiconductor devices will be different, even though these semiconductor structures both contain the same device structure.

The present inventors have found that the electronic and/or optical performance of a semiconductor device is affected by growing said device over an underlying porous region. When a semiconductor device is epitaxially grown over a porous region of semiconductor material, the crystal structure of the overgrown device inherits certain properties from the underlying porous material, which means that the device will exhibit different characteristics to the same device structure grown over non-porous material. Differences in the properties of underlying porous regions (for example variations in porosity, thickness and the lateral dimensions of the porous regions) lead to different effects on overgrown structures, so growing the same device structure over two different porous regions (or one porous region and one non-porous region) will produce two devices which behave differently.

Benefits provided to the semiconductor devices by overgrowth above porous regions include strain relaxation, lattice parameter enlargement, wafer bow reduction, and beneficial mechanical and thermal influences during the growth of the light-emitting region at high temperatures. The removal of dislocations from the semiconductor material of the porous region during porosification greatly reduces the strain in porous regions of the wafer. Epitaxially grown semiconductor structures contain strain which is increased if a layered structure contains layers of different compositions, as mismatches in the lattice dimensions of different layers contributes to increasing strain in the crystal structure. The inventors have found that forming pores in a region of the structure can significantly reduce strain in the structure by removing dislocations and increasing the compliance of the remaining porous region. Thus, during epitaxial growth of semiconductor device structures over a porous region, the porous material is more compliant to matching the lattice of the overlying device structure and any intervening layers. This results in the overgrown semiconductor device experiencing significantly lower strain than would be the case had same device structure been deposited on an entirely non-porous wafer.

As semiconductor devices formed over porous regions experience lower strain, there are also fewer structural defects in the device structures to act as non-radiative recombination centres to harm device performance.

The first semiconductor device is preferably formed over the first porous region during manufacture, so that the first porous region influences the structure and mechanical properties of layers of semiconductor that are epitaxially deposited over the porous region. Layers of semiconductor material that are deposited over the porous region during growth experience benefits such as strain reduction, lattice parameter enlargement, and wafer bow reduction, which are imparted to the device’s active region and affect its structure and its electronic and/or light-emitting behaviour.

Once a semiconductor device has been epitaxially grown over a porous region, and the quality of the device’s active region has been enhanced by the influence of the porous region, the beneficial effects of the porous region on the device properties are permanently imparted to the semiconductor device.

The inventors have found, for example, that growing an LED structure over a porous region of Ill-nitride material causes a significant shift in emission wavelength towards longer wavelengths, compared to an identical LED structure grown on a non-porous substrate.

The inventors have demonstrated this by growing a conventional green/yellow (emission between 500-570nm, or 570nm-590nm) InGaN LED structure on a non-porous GaN wafer, and demonstrating that the LED emits green/yellow light as expected. The same “green/yellow” InGaN LED structure was grown on a template containing a porous region, and when an electrical bias was applied across the LED the LED emitted light in the red range of between 600 and 750 nm.

By providing a monolithic array of semiconductor devices in which one or more first semiconductor devices are positioned over a first porous region, and one or more second semiconductor devices are not positioned over the same porous region, the first and second semiconductor devices will perform differently in use, even though they have the same device structure. This advantageously allows an array of differently-performing semiconductor devices (for example LEDs which emit at different peak wavelengths) to be manufactured in a single step as a monolithic array, without the transfer and re-pitching steps required in the prior art.

By controlling the presence - or absence - of an underlying nanoporous region in the wafer below the semiconductor devices, and by controlling the dimensions and porosity of porous regions where they are present, it is thus possible with the present invention to produce semiconductor devices with different properties monolithically on the same wafer using only a single epitaxy. In a preferred embodiment for example, LEDs which emit different colours of light can be formed on the same wafer, using a single epitaxial growth process for all LEDs, by overgrowing the differently coloured LEDs over differing porous/non-porous regions of the wafer.

The first semiconductor device is positioned over the first porous region, as a result of the first semiconductor device having overgrown on the first device area with the porous region underneath. By overgrowing the first semiconductor device over the first porous region, the present inventors have found that the first semiconductor device will be affected by the underlying first porous region, as the crystal structure of the first semiconductor device inherits certain properties from the underlying porous material which affect the performance of the first semiconductor device. Porous region characteristics including the first porosity and first dimensions (thickness and/or lateral dimensions) of the first porous region affect the crystal structure of the overgrown first semiconductor device, and thus affect the behaviour of the first semiconductor device.

The second semiconductor device, however, is not overgrown over a porous region having the same properties as the first porous region. The second semiconductor device may be overgrown over a second region of the wafer which does not have the same properties as the first porous region. The second region may be non-porous, or it may be porous, but with the porous second region being different in some way from the first porous region. For example the second region may be a second porous region of Ill-nitride material. Compared with the first porous region, the second porous region may have a different thickness, and/or a different composition, and/or a different structure (for example a different sequence of layers of material), and/or a different average pore size, and/or a different % porosity. If one or more of these parameters is different in the second porous region compared to the first porous region, the properties imparted to the overgrown second semiconductor device will be different from those imparted to the first semiconductor device by the first porous region.

The second semiconductor device may be positioned over a second porous region which has the same structure and porosity as the first porous region, but a different thickness. Alternatively, the second semiconductor device may be positioned over a second porous region which has the same structure and dimensions as the first porous region, but a different % porosity or average pore size.

In a first preferred embodiment, the second semiconductor device may be formed over a second porous region which is not identical to the first porous region - for example a second porous region having a porosity and/or dimensions that are different from those of the first porous region. In this case, the different porosity and/or dimensions of the second porous region will affect the overgrown second semiconductor device differently to the effect of the first porous region on the first semiconductor device. The electronic and/or optical characteristics of the second semiconductor device will therefore be different from those of the first semiconductor device, even though the device structures are identical.

Alternatively, in a second preferred embodiment, the second semiconductor device may not be positioned over a porous region. In other words, the wafer may be entirely non- porous underneath the second device area. In this embodiment, the second semiconductor device is overgrown over a non-porous wafer with no porous material underlying the second device area, so the electronic and/or optical characteristics of the second semiconductor device are not affected by the presence of any porous region under the device. The electronic and/or optical characteristics of the second semiconductor device will therefore be different from those of the first semiconductor device, even though the device structures are identical, because the first semiconductor device is affected by underlying porous material while the second semiconductor device is not. Wafer

The wafer preferably comprises a substrate and a plurality of layers of semiconductor material on the substrate.

Preferably all of the semiconductor material used in the present invention is Ill-nitride semiconductor material. Thus preferably the wafer comprises a plurality of layers of Ill- nitride semiconductor material on the substrate. Each semiconductor layer in the wafer (besides the substrate) is preferably formed from one of GaN, InGaN, AIGaN, AllnGaN or AIN.

The substrate may be Silicon, Sapphire, SiC, p-Ga2O3. The crystal orientation of the substrates can be polar, semi-polar or non-polar orientation. The substrate thickness may typically vary between 100 pm and 1500 pm. The wafer may have a variety of sizes, such as 1cm ² , or 2 inch, 4 inch, 6 inch, 8 inch, 12 inch, or 16 inch diameter or larger.

The wafer may alternatively be termed a template, as during manufacturing the multi-layer semiconductor wafer is used as a template for overgrowth.

The or each porous region is preferably formed in a sub-surface layer of the wafer. The porous region may be positioned in a layer of semiconductor material which is arranged between a non-porous surface layer of the wafer, and the substrate. Preferably the first and second semiconductor devices are positioned on a non-porous surface layer of the wafer.

The array may comprise electrical contacts which are operatively coupled to the first and second semiconductor devices, such that the first and second semiconductor devices are independently driveable by a power source.

First Porous Region

The first porous region preferably occupies a portion of a layer of semiconductor material in the wafer, particularly preferably a portion of a sub-surface layer.

The first porous region preferably does not occupy an entire layer of the wafer, as the first porous region does not underlie the second semiconductor device. When viewed from above in plan view, the first porous region preferably occupies a discrete portion of the wafer footprint. Where the wafer comprises a plurality of first porous regions, for example an array of first porous regions, the array of first porous regions occupies an array of discrete portions of the wafer footprint. The wafer may be patterned with an array of first porous regions. Preferably the or each first porous region is surrounded by non-porous semiconductor material in the same layer, and above and below the first porous region.

The first semiconductor device is preferably grown over a semiconductor wafer template which contains the first porous region. The semiconductor wafer template may also contain a number of layers of semiconductor material arranged to provide a suitable substrate for the overgrowth of the device structure.

The first porous region may have a thickness of at least 1 nm, preferably at least 10 nm, particularly preferably at least 50 nm. For example, the porous region may have a thickness between 1 nm and 10000 nm.

The first porous region may have a porosity between 1% and 99% porosity, or between 10% and 80% porosity, or between 20% and 70% porosity, or between 30% and 60% porosity. The porosity of the first porous region may be measured as the volume of all pores relative to the volume of the whole first porous region.

The degree of porosity has been found to have an effect on the performance characteristics of the overgrown semiconductor device, for example an effect on the magnitude of the wavelength shift caused by the porous region. In general, the higher the % porosity, the larger the wavelength shift of an LED compared to the same LED structure formed over a non-porous template.

The first porous region is preferably formed from one of GaN, InGaN, AIGaN, AllnGaN or AIN.

Second Porous Region

In a first preferred embodiment, the second semiconductor device is positioned over a second porous region of the wafer. The second porous region may have a second porosity different from the first porosity, and/or dimensions different from the first dimensions. The second porous region is thus not identical to the first porous region, which means that the overgrown second semiconductor device will perform differently from the first semiconductor device formed over the first porous region.

The second porous region occupies a portion of a layer of semiconductor material in the wafer, particularly preferably a portion of a sub-surface layer. Preferably the second porous region is positioned in the same wafer layer as the first porous region. The second porous region and the first porous region preferably occupy different lateral positions in the wafer, so that the first and second semiconductor devices on the first and second device areas each overlie their own respective porous region.

The second porous region preferably does not occupy an entire layer of the wafer, so that the second porous region underlies the second semiconductor device but does not underlie the first semiconductor device. When viewed from above in plan view, the second porous region preferably occupies a discrete portion of the wafer footprint. Where the wafer comprises a plurality of second porous regions, for example an array of second porous regions, the array of second porous regions occupies an array of discrete portions of the wafer footprint. The wafer may be patterned with an array of second porous regions. Preferably the or each second porous region is surrounded by non-porous semiconductor material in the same layer, and above and below the second porous region.

The second semiconductor device is preferably grown over a semiconductor wafer template which contains the second porous region.

The second porous region may have a thickness of at least 1 nm, preferably at least 10 nm, particularly preferably at least 50 nm. For example, the second porous region may have a thickness between 1 nm and 10000 nm.

The second porous region may have a second thickness different from the thickness of the first porous region. The second porous region may have a greater thickness than the first porous region, or a lower thickness than the first porous region. The second porous region may have lateral dimensions which are different from the lateral dimensions of the first porous region.

The first porous region may have a first shape, and the second porous region may have a second shape different from the first shape.

The second porous region may have a porosity between 1% and 99% porosity, or between 10% and 80% porosity, or between 20% and 70% porosity, or between 30% and 60% porosity. The porosity of the second porous region may be measured as the volume of all pores relative to the volume of the whole first porous region.

The degree of porosity has been found to have an effect on the performance characteristics of the overgrown semiconductor device, for example an effect on the magnitude of the wavelength shift caused by the porous region. In general, the higher the % porosity, the larger the wavelength shift of an LED compared to the same LED structure formed over a non-porous template.

The second porous region may have a higher % porosity than the first porous region, or a lower % porosity than the first porous region. The second porous region may contain a smaller average pore size, or a larger average pore size, than the first porous region.

The second porous region is preferably formed from one of GaN, InGaN, AIGaN, AllnGaN or AIN.

The porosity of the or each porous region may be between 1 %-99 % porosity, preferably between 20% to 90% porosity or between 30% - 80% porosity.

The thickness of the or each porous region may be greater than 1 nm, more preferably greater than 10 nm, particularly preferably at least 40 nm or 50 nm or 100 nm.

The or each porous region may comprise a continuous layer section of porous Ill-nitride material, which occupies a portion of a wafer layer also containing sections of non-porous Ill-nitride material, and/or sections of porous Ill-nitride material having a different porosity.

The or each porous region may comprise a single layer section of porous GaN, or a single layer section of porous InGaN, or a stack comprising one or more layers of porous GaN and/or one or more layers of porous InGaN.

Second Semiconductor Device over Non-porous

In a second preferred embodiment, the second semiconductor device is not positioned over a porous region. In other words, the footprint of the wafer that is directly underneath the second device area is non-porous through its entire thickness. There may be no porous semiconductor material positioned directly between the substrate of the wafer and the second semiconductor device.

In this embodiment, the second semiconductor device is overgrown over a non-porous wafer with no porous material underlying the second device area, so the electronic and/or optical characteristics of the second semiconductor device are not affected by the presence of any porous region under the device. The electronic and/or optical characteristics of the second semiconductor device will therefore be different from those of the first semiconductor device, even though the device structures are identical, because the first semiconductor device is affected by underlying porous material while the second semiconductor device is not.

Further Semiconductor Devices

In addition to the first and second semiconductor devices on the wafer, the monolithic array may comprise one or more additional semiconductor devices.

The monolithic array may comprise a third semiconductor device also having the same semiconductor device structure as the first and second semiconductor devices. The third semiconductor device may occupy a third device area on the wafer, and the third semiconductor device is not positioned over a porous region having the same porosity and dimensions as the first porous region. This means that the third semiconductor device will perform differently from the first semiconductor device under the same driving conditions. The third semiconductor device may be positioned over a third porous region having a porosity different from the first porosity and/or third dimensions which are different from the first dimensions of the first porous region. In embodiments where the second semiconductor device is positioned over a second porous region, the third porous region may have a third porosity different from the second porosity and/or third dimensions which are different from the second dimensions of the second porous region. Alternatively, in embodiments where the second semiconductor device is positioned over a second porous region, the third semiconductor device may not be positioned over any porous region.

The section of wafer beneath the third semiconductor device should have different porosity characteristics from the sections of wafer beneath the first and second semiconductor devices, so that the characteristics of the third semiconductor device differ from those of the first and second semiconductor devices.

The first, second and third semiconductor devices may advantageously have the same device structure but respond differently in response to the same driving conditions.

In a preferred embodiment, for example, the first, second and third semiconductor devices may be red, green and blue-emitting LEDs, and the first, second and third semiconductor devices may form a pixel of a display device.

The monolithic array may comprise further semiconductor devices having the same semiconductor device structure, for example fourth or fifth semiconductor devices, on the wafer, over sections of the wafer with different porosity characteristics. By controlling the porosity characteristics, such as the % porosity, pore size, and dimensions of different porous regions in the wafer, any number of semiconductor devices having different operating characteristics may be provided from a single device epitaxy.

Array of Multiple First and Second Semiconductor Devices

In a particularly preferred embodiment, the monolithic array comprises an array of multiple first semiconductor devices on the wafer, above a corresponding array of first porous regions in the wafer, and an array of multiple second semiconductor devices on the wafer.

The array of second semiconductor devices may be positioned above a corresponding array of second porous regions in the wafer.

Alternatively, each of the second semiconductor devices in the array is not positioned over a porous region of the wafer. Each of the second semiconductor devices in the array may be positioned over a non-porous region of the wafer.

The monolithic array may optionally comprise an array of multiple third semiconductor devices on the wafer, above a corresponding array of third porous regions in the wafer, the third porous regions having different porosity characteristics from the first porous regions.

Semiconductor Devices

The present invention is not limited to a particular semiconductor device, as a wide variety of electronic and optoelectronic semiconductor device structures are known in the art, and the effect of the present invention may be achieved using a variety of conventional semiconductor device types and device structures.

Regardless of the type of devices formed on the wafer, if the first and second devices are formed over regions having different porosity characteristics, the optical and/or electrical characteristics of the devices will be different even when their epitaxial device structures are the same.

The first semiconductor device may be a different size and/or shape and/or geometry to the second semiconductor device. For example the first device area may be larger than the second device area, such that the first semiconductor device is larger in lateral dimensions than the second semiconductor device. Where the first and second semiconductor devices are optoelectronic devices like LEDs, for example, the lateral size of the LED affects the brightness and optionally the wavelength emitted by the LED. It may be desirable therefore to make different semiconductor device subpixels different sizes to compensate for differences in the brightness of different emitted wavelengths.

In a preferred embodiment, the semiconductor device structure is an optoelectronic device structure, such as a light-emitting diode (LED) or a vertical cavity surface emitting laser (VCSEL), so that both the first and second semiconductor devices are optoelectronic devices.

Alternatively the semiconductor device structure may be an electronic or electrical component, such as a high electron mobility transistor (HEMT) or a radio frequency (RF) device. The semiconductor device structure may be a high electron mobility transistor (HEMT), such that the first and second semiconductor devices are both HEMTs. Or the semiconductor device structure may be a radio frequency device, such that the first and second semiconductor devices are both radio frequency devices.

Particularly preferably the semiconductor device structure is an LED structure, for example a mini-LED, micro-LED or nano-LED structure. The LED may comprise a light-emitting region which preferably comprises a multiple quantum well (MOW) containing a plurality of quantum wells (QWs), or quantum dots, quantum wires, or other quantum nanostructures.

An LED comprises an n-doped portion, a p-doped portion, and a light-emitting region located between the n-doped portion and a p-doped portion, the light-emitting region comprising a light-emitting layer which emits light at a peak emission wavelength under electrical bias thereacross.

The light-emitting region, and/or the LED, may have lateral dimensions (width and length) of greater than 100 pm and less than 300 pm. In this case, the LED may be termed a “mini- LED”. In preferred embodiments, the mini-LED may be square or circular or square with circular corners and have dimensions such as 300 pm x 300 pm, 200 pm x 200 pm , 100 pm x 100 pm.

The light-emitting region, and/or the LED, may alternatively have lateral dimensions (width and length) of less than 100 pm. In this case, the LED may be termed a “micro-LED”. The micro-LED may preferably have lateral dimensions of less than 80 pm, or 70 pm, or 60 pm, or 50 pm or 30 pm, or 25 pm, or 20 pm, or 15 pm or 10 pm, or 5 pm or 3 pm or 2 pm. In preferred embodiments, the micro-LED may be square or circular or square with circular corners and have dimensions such as 75 pm x 75 pm, 50 pm x 50 pm, 40 pm x 40 pm, 30 pm x 30 pm, 25 pm x 25 pm, 20 pm x 20 pm or 10 pm x 10 pm, or 5 pm x 5 pm, or 2 pm x 2 pm, or 1 pm x 1 pm, or 500 nm x 500 nm or smaller.

The light-emitting region, and/or the LED, may alternatively have lateral dimensions (width and length) of less than 1 pm. In this case, the LED may be termed a “nano-LED”. The nano-LED may preferably have lateral dimensions of less than or 500nm, or 200nm, or 100nm, or 50nm.

The LEDs may be circular, triangle, rectangular, square, oval, diamond, hexagonal, pentagonal, and any combination of these shapes. In the case of irregular-shapes of pixel design, at least one dimension should fall within the dimensions defined above in order for the LEDs to be classed as mini- or micro-LEDs. For example the width or diameter of the LEDs are preferably less than 100 pm so that the LEDs are classed as micro-LEDs.

Preferably the first semiconductor device and the second device are each LED subpixels, such that the first and second semiconductor devices form a device pixel.

The semiconductor device structure may be a single-emission-wavelength LED structure, such that the first and second semiconductor devices are LEDs which emit at single peak emission wavelengths in response to a driving current.

In a preferred embodiment, the first semiconductor device may be an LED which emits at a first peak wavelength in response to a first driving current, and the second semiconductor device emits at a second peak wavelength different from the first peak wavelength in response to the same first driving current. As discussed above, this difference in emission characteristics is caused by the different porosity characteristics of the wafer sections on which the first and second devices are overgrown, as the presence of a porous region, and the porosity and dimensions of that porous region, has an influence on the crystal structure and emission behaviour of any overgrown LED.

In a particularly preferred embodiment, the first semiconductor device is an LED positioned over the first porous region and the second semiconductor device is an LED which is not positioned over a porous region, and the first semiconductor device LED emits red light in response to a driving current, while the second semiconductor device LED emits green/blue light in response to the same driving current. A single LED semiconductor structure, corresponding to a conventional green/blue LED design, may thus provide two different emission colours when grown in a single epitaxy on a monolithic wafer, simply by overgrowing the first LED over a porous region and the second LED not over a porous region. The presence of the first porous region under the first LED creates a red-shift in the conventional peak emission wavelength of this LED structure, so that the second LED emits at the expected emission wavelength but the first LED emits at a longer red emission wavelength.

Variable-wavelength LEDs

In another preferred embodiment, the first and/or second semiconductor device may be a variable-wavelength LED configured to emit a variable peak emission wavelength in response to variations in the driving current provided to the LED. In addition to the variations in peak emission wavelength created by the differing porosity characteristics of the wafer sections underlying the first and second semiconductor devices, it may thus be possible to tune the emission wavelength of one or both LEDs by providing different driving currents to the LEDs.

A variable-wavelength light emitting diode (LED) preferably comprises: an n-doped portion; a p-doped portion; a light-emitting region located between the n-doped portion and a p-doped portion, the light-emitting region comprising a light-emitting layer which emits light at a peak emission wavelength under electrical bias thereacross; wherein the LED is configured to receive a power supply, in which the peak emission wavelength of the LED is continuously controllable over an emission wavelength range by varying, or controlling, the power supply. The peak emission wavelength of the variablewavelength LED is preferably continuously controllable, or continuously variable, over an emission wavelength range of at least 40 nm by varying, or controlling, the power supply.

As the peak emission wavelength of the variable-wavelength LED is preferably continuously controllable, or continuously variable, over an emission wavelength range the LED can be described as a variable-wavelength LED.

The variable-wavelength emission behaviour of the LED structure is enabled by the fact that the LED structure (the n-doped portion, the light-emitting region and the p-doped portion) are grown over a template containing a porous region. The present inventors have found that the presence of a porous region of Ill-nitride material in the template structure prior to overgrowth of the LED structure leads to higher quality crystal growth and thus significant benefits including the possibility of varying the emission wavelength of the LED light-emitting region. The mechanism by which the porous region enables the variable wavelength emission of the LED is the subject of ongoing study. Benefits provided to the LED by the porous region include strain relaxation, lattice parameter enlargement, wafer bow reduction, and mechanical and thermal influence during the light-emitting region being grown at high temperatures.

Thus the first semiconductor device may be a variable-wavelength LED, as the first semiconductor device is overgrown over a porous region of semiconductor material. The second semiconductor device may also be a variable-wavelength LED in embodiments comprising a second porous region. If the second semiconductor device is not formed over a second porous region, the second semiconductor device will not inherit the crystal structure features which make it possible for the LED to emit across a range of wavelengths.

The variable-wavelength LED is configured to receive a supply of power, or a drive current, from a power supply or LED driver. The term “power supply” is used herein to refer to the power, or current, supplied to drive an LED during use.

The peak emission wavelength of the LED may preferably be continuously controllable, or continuously variable, over an emission wavelength range by varying, or controlling, the magnitude of a drive current provided to the variable-wavelength LED.

In traditional LED devices, changes to the driving current provided to the LED produces a very small shift in emission wavelengths, but the present inventors have found that the wavelength shift can be broadened and controlled to a greater extent than traditional LED materials. Rather than the few nm emission range of prior art devices, the LED of the present invention is controllable to emit over a far broader emission range, for example a range of at least 40 nm. As the present LED is tunable to emit over a broad wavelength range, it may be referred to as a variable-wavelength LED.

The LED may be a dynamic colour-tunable LED, in which the peak emission wavelength of the LED is tunable by varying the driving conditions provided to the LED by the power supply. The LED is preferably driveable to emit at a single peak emission wavelength in response to a stable power supply, but to emit at different peak emission wavelengths in response to variations in the power supply. Thus the LED may be used to emit a particular colour for a prolonged period, or alternatively the LED may be driven to emit a variety of different wavelengths by providing varying driving conditions.

Preferably, the n-doped portion, the p-doped portion and the light-emitting region all comprise or consist of Ill-nitride material, preferably GaN, InGaN, AIGaN or AllnGaN

The variable-wavelength LED preferably contains a single epitaxially-grown diode structure containing the n-doped portion, the p-doped portion and the light-emitting region. Thus the variable peak emission wavelengths of the LED are all emitted by the same LED diode structure and composition.

The LED preferably comprises a porous region of Ill-nitride material. The light-emitting region of the LED is preferably formed over a porous region of Ill-nitride material. In some embodiments, one of the n-doped portion or the p-doped portion may contain the porous region of Ill-nitride material. In other embodiments, the n-doped portion; the p-doped portion; and the light-emitting region are provided on a substrate which comprises the porous region of Ill-nitride material. During epitaxial growth of the LED, the light-emitting region is preferably overgrown after the porous region has been formed.

The present inventors have found that a porous region of Ill-nitride material enables the same LED to emit at a range of peak emission wavelengths, rather than at one specific wavelength. The peak emission wavelength of the LED may be varied across an emission wavelength range by varying the power supply provided to the LED. The present invention therefore provides a variable-wavelength LED, which may be controlled to emit at any wavelength across a continuous emission wavelength range. By varying the driving conditions provided to the LED by the power supply, the LED is capable of emitting at any wavelength within the emission wavelength range of said LED, and not simply at discrete peak emission wavelengths.

The present inventors have found that the ability of the LED to emit at tuneable wavelengths across a broad emission range may be imparted by either incorporating a porous region of Ill-nitride semiconductor material into the LED structure, or forming the LED diode structure over a porous region of Ill-nitride semiconductor material. Benefits provided to the LED by the porous region include strain relaxation, lattice parameter enlargement, wafer bow reduction, and beneficial mechanical and thermal influences during the growth of the light-emitting region at high temperatures.

The light-emitting region of the LED is preferably formed over a porous region of Ill-nitride material during manufacture, so that the porous region influences the structure and mechanical properties of layers of semiconductor that are epitaxially deposited over the porous region. Layers of semiconductor material that are deposited over the porous region during growth experience benefits such as strain reduction, lattice parameter enlargement, and wafer bow reduction, which are imparted to the LED light-emitting region and affect its structure and its light-emitting behaviour.

Once the LED light-emitting (active) region has been epitaxially grown over the porous region, and the quality of the active region has been enhanced by the influence of the porous region, the beneficial effects of the porous region on the emission properties are permanently imparted to the LED active region. Thus the LED diode structure may be retained on the porous region, in which case the variable-wavelength LED comprises a porous region of Ill-nitride material, or alternatively, during the processing of LEDs into devices after epitaxial growth, the porous region may be removed from the LED structure.

The width of the emission wavelength range may vary depending on the structure and composition of the LED structure (the n-doped portion, light-emitting region and p-doped portion), and on the structure and porosity of the porous region. The width of the emission wavelength range may also vary depending on the size and shape of the LED (the pixel size and shape).

In preferred embodiments, the peak emission wavelength is controllable over an emission wavelength range of at least 40 nm, or at least 50 nm, or at least 60 nm, or at least 70 nm, or at least 80 nm by varying the power supply. Preferably the peak emission wavelength is controllable over an emission wavelength range of up to 100 nm, or 110 nm, or 120 nm, or 130nm, or 140nm, or 150nm, or 160nm, or 170nm, or 180nm, or 190nm, or 200 nm, or 400 nm, or 450 nm. The size of the emission wavelength range obtainable by the present LED is thus far greater than the emission ranges achievable with LEDs of the prior art.

The variable-wavelength LED is advantageously controllable to emit at any peak emission wavelength within its emission wavelength range. By varying the characteristics of the power supply and LED pixel size and shape, the variable-wavelength LED may therefore be controlled to emit light at any selected peak emission wavelength within this range. The emission wavelength of the variable-wavelength LED is preferably continuously variable across its emission wavelength range in response to driving conditions provided by a power source being varied continuously across a range of driving conditions.

The position of the emission wavelength range in the electromagnetic spectrum may also vary depending on the design of the variable-wavelength LED structure (the n-doped portion, light-emitting region and p-doped portion). For example the wavelengths contained in the emission wavelength range may depend on the number and composition of light emitting layers in the variable-wavelength LED. A large variety of LED active regions are known in the art for emitting at different wavelengths in the visible spectrum, so by lightemitting region forming the LEDs of the present invention with different light-emitting regions, emission wavelength ranges covering different portions of the spectrum may be obtained.

The variable-wavelength LED emission wavelength range may be between 400 nm and 850 nm, or between 400 nm and 800 nm, or between 400 nm and 690 nm, or between 400 nm and 675 nm. The emission wavelength range may be a sub-range within the range of 400 nm to 750 nm. The emission wavelength range may be tuned to cover any part of this range by selecting different LED active regions and controlling the size and shape of the LED pixels.

Preferably the emission wavelength range of the variable-wavelength LED extends from a lower end below 410 nm, or 430 nm, or 450 nm, or 470 nm, or 500 nm, or 520 nm, or 540 nm, or 560 nm, to an upper end above 570 nm, or 580 nm, or 600 nm, or 610 nm, or 630 nm, or 650 nm, or 675 nm. The first and second ends of the emission wavelength range may be tuned depending on the selection of LED structure and LED shape and size, as described above.

For example in preferred embodiments the lower end of the emission wavelength may be between 400 nm and 450 nm (violet) or between 450 nm and 500 nm (blue) or between 500 nm and 570 nm (green), and the upper end of the emission wavelength may be between 570 nm and 590 nm (yellow), or between 590 nm and 610 nm (orange), or between 610 and 700 nm (red).

In a preferred embodiment, the variable-wavelength LED emission wavelength range may extend from a lower end that is below 500 nm to a higher end that is above 610 nm, so that the peak emission wavelength of the LED may be varied to emit at any wavelength from blue (below 500 nm) to red (above 610 nm) by varying the power supply. Providing a single LED design that can be controlled to emit at blue wavelengths (450-500 nm), green (500- 570 nm) and also at yellow (570-590 nm), orange (590-610 nm) and red (610-760 nm) is highly advantageous, and could provide significant advantages for LED displays.

In other preferred embodiments, the variable-wavelength LED emission wavelength range may extend between 520 nm and 660 nm, or between 550 nm and 650 nm, by varying the power supply to the LED.

In a particularly preferred embodiment, the peak emission wavelength is controllable between 540 nm and 680 nm, or between 560 nm and 675 nm, by varying the power supply. Thus, the same LED may be controllable to emit at a peak emission wavelength anywhere between 540 nm in the green and 680 nm in the red. Green and red LEDs have historically been more difficult to manufacture than shorter wavelength blue LEDs due to issues such as the difficulty of incorporating the required indium content into the lightemitting region. Providing a single LED design that can be controlled to emit at green wavelengths (500-570 nm) and also at yellow (570-590 nm), orange (590-610 nm) and red (610-760 nm) is therefore highly advantageous, and could provide significant advantages for LED displays.

In another preferred embodiment, the peak emission wavelength is controllable between 520 nm and 675 nm, or between 550 nm and 650 nm, by varying the power supply.

Although the variable-wavelength LED can emit across a continuous emission wavelength range, in some embodiments it may be desirable to control the LED to function in a plurality of discrete emission modes, for example in response to a power supply having a plurality of driving modes. For example by driving the LED in a plurality of different modes corresponding to discrete emission colours, a simplified colour display may be provided, in which discrete emission colours are mixed in known methods to give a desired visual effect.

The variable-wavelength LED is preferably controllable to emit at least two discrete peak emission wavelengths by varying the driving conditions provided by the power supply between two discrete driving conditions (such as two discrete magnitudes of drive current). The LED may be controllable to emit at a first peak emission wavelength in response to a first driving condition provided by the power supply (which may be a drive current having a first magnitude), at a second peak emission wavelength in response to a second driving condition provided by the power supply (which may be a drive current having a second magnitude different from the first magnitude).

The variable-wavelength LED is preferably controllable to emit at least three discrete peak emission wavelengths by varying the driving conditions provided by the power supply. The peak emission wavelength of the variable-wavelength LED may thus be variable over at least three “colours” in the EM spectrum.

The variable-wavelength LED may be controllable to emit at a first peak emission wavelength in response to a first driving condition provided by the power supply, at a second peak emission wavelength in response to a second driving condition provided by the power supply, and at a third peak emission wavelength in response to a third driving condition provided by the power supply.

The variable-wavelength LED may preferably be controllable to emit a blue peak emission wavelength in response to a first driving condition provided by the power supply, to emit a green peak emission wavelength in response to a second driving condition provided by the power supply, and to emit a red peak emission wavelength in response to a third driving condition provided by the power supply.

The variable-wavelength LED may be controllable to emit a first peak emission wavelength in the range 400-500 nm in response to a first driving condition provided by the power supply, to emit a second peak emission wavelength in the range 500-550 nm in response to a second driving condition provided by the power supply, and to emit a third peak emission wavelength greater than 600 nm in response to a third driving condition provided by the power supply.

Preferably, the variable-wavelength LED is controllable to emit a first peak emission wavelength in the range 430-460 nm in response to a first driving condition provided by the power supply, to emit a second peak emission wavelength in the range 510-560 nm in response to a second driving condition provided by the power supply, and to emit a third peak emission wavelength in the range 600-660 nm in response to a third driving condition provided by the power supply.

The first, second and third driving conditions may be first, second and third current densities, or the first, second and third driving conditions may be first, second and third power densities. The morphology of quantum wells (QWs) in the active light-emitting region may be varied. For example the light-emitting region may contain uniform QWs with well-defined interfaces or fragmented QWs with less well-defined interfaces, fragmentation, or QW well width/composition fluctuation or quantum dots like localisation centres. This control of QW morphology can determine the range of the variable emission wavelength to be controlled and manipulated.

The light-emitting region preferably comprises a plurality of quantum wells (QWs). The quantum wells may be continuous. The quantum wells may be fragmented, or discontinuous.

The variable-wavelength LED may comprise a current constraining layer, or a current limiting layer, which is a dielectric layer configured to confine the lateral area of the LED through which current is conducted. The use of a current constraining layer may advantageously allow further control of the current density, in order to better control the peak emission wavelength of the LED.

The current constraining layer may advantageously enable the manipulation of the power density provided to the variable-wavelength LED, in order to control the peak emission wavelength.

The current constraining layer is preferably a layer of dielectric material. For example, the current constraining layer may be any dielectric, for example SiO ₂ , SiN or SiNx.

The current constraining layer may be positioned in a variety of positions in the variablewavelength LED, as long as it confines the lateral area of the LED through which current is conducted. The current constraining layer may be positioned in the LED between an electrical n-contact and an electrical p-contact.

The current constraining layer may be positioned adjacent to either the n-doped portion or the p-doped portion of the LED. For example the current constraining layer may be positioned between the n-doped portion and the light-emitting region. Alternatively the current constraining layer may be positioned between the light-emitting region and the p- doped portion. The current constraining layer may be positioned between an electrical contact and the LED structure (n-doped portion, p-doped portion and light-emitting region).

The current constraining layer preferably comprises an aperture extending through the current constraining layer, or one or more apertures extending through the current constraining layer. The aperture may preferably be positioned in the centre of the current constraining layer. For example the current constraining layer may comprise a circular opening in the centre of the LED structure.

The variable-wavelength LED may be configured so that an electrical contact is in contact with the LED structure via the aperture in the current constraining layer, so that the area of the aperture defines a contact area over which the contact and the LED structure are touching.

The lateral dimensions of the or each aperture is preferably much smaller than the lateral dimensions of the LED. By providing an aperture through the dielectric current constraining layer, high local current density may be achieved, which may advantageously enable improved control of the power through the LED.

For example the lateral width (or diameter) of the aperture may be equal to or less than 50% of the lateral width of the LED structure (the LED mesa). The width of the aperture may be equal to or less than 45%, or 40%, or 35%, or 30%, or 25%, or 20% of the width of the LED structure.

The relative area of the aperture compared to the overall area of the current constraining layer (the blocked region) may be varied to modify the local current density.

The light emitting region preferably comprises a multiple quantum well (MQW) containing a plurality of quantum wells (QWs), or quantum dots, quantum wires, or other quantum nanostructures.

In some embodiments, the light-emitting region comprises a plurality of quantum wells (QWs), and the quantum wells are continuous.

The present inventors have found that non-uniformities in the light-emitting region have a significant effect in broadening the emission wavelength range across which a light-emitting region can emit light in response to variations in the power supplied to the LED. In the prior art, non-uniformities in the light-emitting region are typically considered problematic flaws, which are unwanted and should be avoided in any way possible because the goal is typically a high-quality, low-flaw semiconductor wafer. The present inventors have eschewed this prejudice in the art, and found that intentionally creating non-uniformities in the light emitting region may advantageously broaden the emission wavelength range and result in a variable-wavelength LED which can emit over a far broader wavelength range than has ever been possible in the prior art.

In alternative embodiments of the present invention, the light-emitting region is non- uniform, fragmented, or discontinuous. The light-emitting region may be deliberately introduced to achieve the effect of carrier localisation centres in InGaN quantum wells, such as multiple types of QW region with different Indium composition and well width and quantum barriers, non-uniform, or fragmented, or broken, or gappy, or discontinuous quantum wells which would result in fluctuation in the well width, InGaN quantum dots or nanostructures, quantum wells formed on polar, semi-polar or non-polar facets.

In a preferred embodiment, the light-emitting region comprises a plurality of quantum wells (QWs), and the quantum wells are non-uniform, fragmented, or discontinuous.

The plurality of QWs may comprise fluctuations in well-width. For example the well width of the QWs may fluctuate by at least 2%, 5%, 10%, 20%, 25%, or 50%, or 75%. The well width fluctuations can be variations between quantum wells (vertical direction) as well as within one quantum well (lateral direction).

The plurality of QWs may comprise fluctuations in alloy composition. For example the indium composition of the QWs may vary by at least 2%, 5%, 10%, 20%, 25% or 50% or 75% across the light-emitting region.

The inventors have found that fluctuations in well-width and/or alloy composition may induce carrier localisation centres, either in the upper interface or lower interface of the QWs. Any carrier localisation centres would induce the variable wavelength in the variablewavelength LED of the present invention. The larger the density of those carrier localisation centres, the larger the variable wavelength range can be achieved.

The variable-wavelength LED may comprise a v-shaped pit which extends, or propagates, through the light emitting active region. Preferably the LED comprises a plurality of v- shaped pits which extend through the light-emitting region.

Preferably the variable-wavelength LED may comprise a density of v-shaped pits (measured looking down onto the LED structure from above) of at least 1 x 10 ⁷ /cm ² , for example at least 5 x 10 ⁷ /cm ² or at least 1 x 10 ⁸ /cm ² , for example a density of v-shaped pits of 1 x 10 ⁷ /cm ² to 5 x 10 ⁹ /cm ² . The variable-wavelength LED may comprise a density of v-shaped pits of less than 5 x 10 ⁹ /cm ² , for example a density of v-shaped pits of less than 1 x 10 ⁹ /cm ² or less than 5 x 10 ⁸ /cm ² .

V-shaped pits are a phenomenon known in the art of epitaxial semiconductor growth, and methods of growing v-shaped pits in semiconductor structures are known in the art. For example, v-shaped pits and their growth are described in the prior art in The effect of nanometre-scale V-pits on electronic and optical properties and efficiency droop of GaN- based green light-emitting Diodes; Zhou et al; Scientific Reports | (2018) 8:11053 | DOI:10.1038/S41598-018-29440-4.

These v-shaped pits are v-shaped when viewed in cross-section, but in reality form as conical or funnel-shaped voids in semiconductor structures that are grown from the bottom up using conventional epitaxial growth methods. While the cross-section of the pits is v- shaped, the pits are typically hexagonal when viewed from above. The point of the v- shaped pits are always directed downwards towards earlier-deposited layers of semiconductor structure, as the pits widen as subsequent layers of epitaxial growth are deposited on top of the structure.

Although v-shaped pits are known in the art, they are typically considered a problematic flaw in semiconductor structures, which are unwanted because the goal is typically a high- quality, low-flaw semiconductor wafer.

In the unusual situations where v-shaped pits have been incorporated into semiconductor structures in the past, the v-shaped pits have been used as a screening mechanism to create higher band gap regions which prevent current carriers going down threading dislocations as a leakage path.

In some preferred embodiments of the present invention, however, v-shaped pits are intentionally incorporated into the variable-wavelength LED structure. The v-shaped pits extend far enough down into the semiconductor structure that they terminate in a layer below the active light-emitting region. This means that the v-shaped pits must extend through the thickness of the active light-emitting region. The present inventors have found that v-shaped pits extending through the light-emitting region of the LED structure may advantageously broaden the emission wavelength range over which a variable-wavelength LED can emit.

As the v-shaped pits extend through the active region of the LED, during epitaxial growth from the bottom up, quantum well (QW) layers that are planar across the rest of the structure are grown on the sloping side walls of the v-shaped pits. The QWs deposited on the pit sidewalls are distorted and stretched around the sides of the pits, so end up being of different thickness and composition compared to the planar QWs across the bulk of the structure.

Around the v-shaped pits, QW layers of semiconductor material are grown as flat planar layers. The active light-emitting region is thus planar around the v-shaped pit. In the location of the v-shaped pits, however, the active layers are distorted and stretched downwards along the sidewalls into the v-shaped pit. This stretching effect changes the thickness of the QWs on the sidewalls of the pit, so that they are different in thickness compared to the planar QW layers formed over the rest of the LED structure.

The inventors have found that v-shaped pits can create local strain relaxation, and MQWs deposited on the sidewall of these v-pits will have different thickness and composition compared to the rest of the MQW, hence the MQW in the region of the v-shaped pits will produce a different emission wavelength.

The quantum wells grown on the side walls of the v-shaped pit are thinner than the bulk planar QWs elsewhere in the structure, which may affect the QW bandgap and allow the QWs in this region to emit at wavelengths different from those emitted by the planar QWs elsewhere in the structure. In addition to this, the QWs on the pit sidewalls may end up having a higher indium (In) content than the surrounding planar QWs, because the sidewalls expose a semipolar facet of the QWs - this facet incorporates more indium during epitaxial growth, so the QWs in the region of the v-shaped pits may be higher in indium than the planar QWs around the pits. Higher indium incorporation typically leads to longer peak emission wavelengths. Both the QW thickness and the indium content affect the emission wavelengths produced by the light-emitting region. The presence of v-shaped pits in the LED structure may thus advantageously modify the composition and thickness of QWs in the light-emitting region in a way that expands the emission wavelength range over which the LED can be driven to emit light. V-shaped pits typically grow from threading dislocations in the semiconductor structure. The threading dislocations are perpetuated upwards through the structure as additional layers are grown over layers containing a threading dislocation, and at a certain point the dislocation widens into a v-shaped pit. Typically the skilled person aims to keep threading dislocation concentrations low in order to produce a “high quality” low-flaw wafer.

V-shaped pits can alternatively be grown using 3-dimensional epitaxial growth modes. 3D epitaxial deposition techniques are known in the art and are typically used to grow “islands” or “pyramids” of semiconductor material on a template. By controlling deposition of the LED structure using 3D epitaxial deposition techniques, v-shaped pits can be artificially grown in desired locations, with no need for a threading dislocation to be present to “seed” the formation of the v-shaped pit. By using this deposition control, the bottom (nadir) of the pit may be created at a desired location in the structure - both a desired lateral position and a desired height in the structure, for example in a particular layer of the semiconductor structure below the active light-emitting region.

The bottom of the v-shaped pit may be located in the connecting layer of the semiconductor structure. The connecting layer may be positioned between the porous region and the n-doped portion.

The bottom of the v-shaped pit may be located in a pre-strain layer of the semiconductor structure. The pre-strain layer may be positioned above the n-doped portion and below the light-emitting region.

Preferably the variable-wavelength LED comprises a plurality of v-shaped pits which extend through the active light-emitting region.

Preferably the variable-wavelength LED comprises a density of v-shaped pits (measured looking down onto the LED structure from above) of at least 1 x 10 ⁷ /cm ² , for example at least 5 x 10 ⁷ /cm ² or at least 1 x 10 ⁸ /cm ² . The LED may comprise a density of v-shaped pits of less than 5 x 10 ⁹ /cm ² , for example a density of v-shaped pits of less than 1 x 10 ⁹ /cm ² or less than 5 x 10 ⁸ /cm ² .

For example the variable-wavelength LED may comprise a density of v-shaped pits of 1 x 10 ⁷ /cm ² to 5 x 10 ⁹ /cm ² , or 5 x 10 ⁷ /cm ² to 5 x 10 ⁹ /cm ² , or 1 x 10 ⁸ /cm ² to 5 x 10 ⁸ /cm ² . The variable-wavelength LED may comprise more than 0.1 v-shaped pit per square micrometre, or more than 1 v-shaped pits per square micrometre, or more than 2 v-shaped pits per square micrometre.

The concentration of v-shaped pits in the variable-wavelength LED is preferably controlled, as too many v-shaped pits may negatively affect the light emission of the LED by disrupting radiative recombination. For example the LED may comprise fewer than 10 v-shaped pits per square micrometre, or fewer than 8 v-shaped pits per square micrometre, or fewer than 6 v-shaped pits per square micrometre.

In a preferred embodiment the LED structure may comprise no greater than 10 ^A 9 threading dislocations per square centimetre. Preferably the semiconductor structure below the active light-emitting region (typically a substrate, the porous region and a connecting layer) comprise no more than 10 ^A 9 threading dislocations per square centimetre. The threading dislocation density is preferably limited to this level so that further epitaxial growth does not create too many v-shaped pits in the light-emitting region.

Both the density and size (the depth) of the v-shaped pits may be controlled. The size of the V-pits can be controlled by the position and the growth conditions of the pre-strain layer and the low-temperature nGaN layer where the pits started.

The morphology of quantum wells (QWs) in the active light-emitting region may be varied. For example the light-emitting region may contain uniform QWs with well-defined interfaces or fragmented QWs with less well-defined interfaces, fragmentation, or QW well width/composition fluctuation or quantum dot like localisation centres. This control of QW morphology can determine the range of the variable emission wavelength to be controlled and manipulated.

The light-emitting region preferably comprises a plurality of quantum wells (QWs). The quantum wells may be continuous. The quantum wells may be fragmented, or discontinuous.

If QWs are continuous and very uniform in thickness and composition, recombination of charge carriers can only happen in regular well defined ways. On the other hand, if QWs are fragmented or discontinuous, this creates lots of nanostructures, which in turn creates different band gaps that result in emission of different colours.

Display Device In a second aspect the invention may provide a display device, comprising a monolithic array of semiconductor devices on a wafer according to the first aspect of the invention described above. In the display device of the second aspect, the first and second semiconductor devices are each LED subpixels, such that the first and second semiconductor devices form a device pixel, and the device comprises an array of multiple device pixels on the wafer. The first and second LED subpixels preferably emit at different peak emission wavelengths in response to a drive current. One or both of the first and second LED subpixels may optionally be a variable-wavelength LED as described above.

The array of multiple device pixels preferably comprises an array of multiple first semiconductor devices forming an array of first LED subpixels, interspersed with an array of multiple second semiconductor devices forming an array of second LED subpixels.

The present invention may thus advantageously allow a display device to be formed by manufacturing, in a single device epitaxy step, a monolithic array of LED subpixels on a wafer, containing arrays of subpixels which emit at different peak emission wavelengths. Previously it has only been possible to produce such multi-wavelength display devices by growing differently-coloured subpixels separately, and then transferring and combining those different subpixels onto a shared wafer. The present invention thus provides a greatly simplified method of producing a multi-colour display device, eliminating many of the costly, cumbersome and technically-challenging processes required in the prior art.

The display device may optionally comprise an array of multiple third semiconductor devices forming an array of third LED subpixels, such that each device pixel is comprised of three subpixels which emit at different peak emission wavelengths.

All of the features described above in relation to the first aspect of the invention may equally be applied to the second aspect of the invention.

Template Wafer

In a third aspect the invention may provide a template wafer for a monolithic array of semiconductor devices. The template wafer may comprise: a surface layer of non-porous Ill-nitride material; a first porous region of Ill-nitride material beneath the surface layer, the first porous region having a first structure, first porosity and first dimensions; and a second region of Ill-nitride material beneath the surface layer; in which the first porous region and the second region occupy different lateral portions of the wafer, so that the first porous region is positioned under a first area of the surface layer and the second region is positioned under a second area of the surface layer; in which the second region is either non-porous, or in which the second region is a second porous region which does not have the same structure, porosity and dimensions as the first porous region.

A lateral area of the surface layer, positioned directly over the first porous region, preferably forms a first device area on which a first semiconductor device may be overgrown. A separate lateral area of the surface layer, positioned directly over the second region, preferably forms a second device area on which a second semiconductor device may be overgrown.

The template wafer is preferably a wafer as described above in relation to the first and second aspects of the invention. Features of the wafer described in relation to these aspects are therefore applicable to the template wafer of the third aspect.

As discussed above, by using such a wafer template, multiple semiconductor devices can be overgrown on the surface layer of the wafer using a single epitaxy, and the different properties of the first porous region and the second region will cause those overgrown devices to perform differently in use. This enables the monolithic growth of semiconductor structures with different electronic and/or optoelectronic properties, using a single epitaxy. By designing the porous region(s) and non-porous regions beneath the surface layer of the wafer, the wafer template can thus be designed to determine the properties of overgrown semiconductor devices.

The wafer preferably comprises a substrate and a plurality of layers of semiconductor material on the substrate.

Preferably all of the semiconductor material used in the present invention is Ill-nitride semiconductor material. Thus preferably the wafer comprises a plurality of layers of Ill- nitride semiconductor material on the substrate. Each semiconductor layer in the wafer (besides the substrate) is preferably formed from one of GaN, InGaN, AIGaN, AllnGaN or AIN.

The substrate may be Silicon, Sapphire, SiC, p-Ga2O3. The crystal orientation of the substrates can be polar, semi-polar or non-polar orientation. The substrate thickness may typically vary between 100 pm and 1500 pm. The wafer may have a variety of sizes, such as 1cm ² , or 2 inch, 4 inch, 6 inch, 8 inch, 12 inch, or 16 inch diameter or larger.

The wafer may alternatively be termed a template, as during manufacturing the multi-layer semiconductor wafer is used as a template for overgrowth.

The or each porous region is preferably formed in a sub-surface layer of the wafer. The porous region may be positioned in a layer of semiconductor material which is arranged between a non-porous surface layer of the wafer, and the substrate. Preferably the first and second semiconductor devices are positioned on the non-porous surface layer of the wafer.

The first porous region preferably occupies a portion of a sub-surface layer of semiconductor material in the wafer.

The first porous region preferably does not occupy an entire layer of the wafer, as the first porous region does not underlie the second semiconductor device. When viewed from above in plan view, the first porous region preferably occupies a discrete portion of the wafer footprint. Where the wafer comprises a plurality of first porous regions, for example an array of first porous regions, the array of first porous regions occupies an array of discrete portions of the wafer footprint. The wafer may be patterned with an array of first porous regions. Preferably the or each first porous region is surrounded by non-porous semiconductor material in the same layer, and above and below the first porous region.

In one preferred embodiment, the second region is a non-porous region of Ill-nitride material.

In alternative preferred embodiments, the second region is a second porous region of the wafer, the second porous region having a second porosity different from the first porosity, and/or dimensions different from the first dimensions.

The second porous region occupies a portion of a layer of semiconductor material in the wafer. The second porous region may be positioned in the same wafer layer as the first porous region, or alternatively the second porous region may be positioned in a different layer of the wafer.

The second porous region and the first porous region preferably occupy different lateral positions in the wafer, so that the first and second semiconductor devices on the first and second device areas each overlie their own respective porous region. The second porous region preferably does not occupy an entire layer of the wafer, so that the second porous region underlies the second semiconductor device but does not underlie the first semiconductor device. When viewed from above in plan view, the second porous region preferably occupies a discrete portion of the wafer footprint. Where the wafer comprises a plurality of second porous regions, for example an array of second porous regions, the array of second porous regions occupies an array of discrete portions of the wafer footprint. The wafer may be patterned with an array of second porous regions. Preferably the or each second porous region is surrounded by non-porous semiconductor material in the same layer, and above and below the second porous region.

The second porous region may have a higher % porosity than the first porous region, or a lower % porosity than the first porous region. The second porous region may contain a smaller average pore size, or a larger average pore size, than the first porous region.

The second porous region may have a second thickness different from the thickness of the first porous region.

The first and/or second porous regions may have a thickness of at least 1 nm, preferably at least 10 nm, particularly preferably at least 50 nm. For example, the first and/or second porous regions may have a thickness between 1 nm and 10000 nm.

The first porous region may have a first shape, and the second porous region may have a second shape different from the first shape.

The second porous region is preferably formed from one of GaN, InGaN, AIGaN, AllnGaN or AIN.

The porosity of the or each porous region may be between 1 %-99 % porosity, preferably between 20% to 90% porosity or between 30% - 80% porosity.

The thickness of the or each porous region may be greater than 1 nm, more preferably greater than 10 nm, particularly preferably at least 40 nm or 50 nm or 100 nm.

The or each porous region may comprise a continuous layer section of porous Ill-nitride material, which occupies a portion of a wafer layer also containing sections of non-porous Ill-nitride material, and/or sections of porous Ill-nitride material having a different porosity. The or each porous region may comprise a single layer section of porous GaN, or a single layer section of porous InGaN, or a stack comprising one or more layers of porous GaN and/or one or more layers of porous InGaN.

In addition to the first porous region and second region in the wafer, the wafer may comprise one or more additional porous regions.

The surface of the wafer may comprise a third device area which is not positioned over a porous region having the same porosity and dimensions as the first porous region. This means that a third semiconductor device overgrown on the third device area will perform differently from the first semiconductor device under the same driving conditions. The third porous region may have a third porosity different from the first porosity and/or third dimensions which are different from the first dimensions of the first porous region. In embodiments where the wafer contains a second porous region, the third porous region may have a third porosity different from the second porosity and/or third dimensions which are different from the second dimensions of the second porous region. Alternatively, in embodiments where the wafer contains a second porous region, the third device area may not be positioned over any porous region.

The section of wafer beneath the third device area should have different porosity characteristics from the sections of wafer beneath the first and second semiconductor devices, so that the characteristics of a third semiconductor device overgrown on the third device area differ from those of identical devices formed on the first and second device areas.

The surface of the wafer may comprise additional device areas, for example fourth or fifth devices areas, on the upper surface of the wafer, the different device areas being positioned over sections of the wafer with different porosity characteristics. By controlling the porosity characteristics, such as the % porosity, pore size, and dimensions of different porous regions in the wafer, any number of semiconductor devices having different operating characteristics may be provided from a single device epitaxy.

In a particularly preferred embodiment, the wafer may comprise an array of sub-surface first porous regions, each of the first porous regions having the same porosity and dimensions, and an array of sub-surface second regions, each second region having the same porosity and dimensions as the other second regions, but not having the same porosity characteristics as the first porous regions. The wafer may thus be configured for the wafer surface to comprise an array of first device areas and an array of second device areas, so that arrays of first and second semiconductor devices can be overgrown directly onto the device areas on the wafer.

Manufacturing Template Wafer

In a fourth aspect, the invention may provide a method of manufacturing a template wafer for a monolithic array of semiconductor devices, comprising the steps of: providing a wafer comprising a surface layer of undoped Ill-nitride material, and a first region of Ill-nitride material beneath the surface layer, in which the first region is n-type Ill- nitride material with a first charge carrier concentration, and a second region of Ill-nitride material beneath the surface layer; and electrochemically porosifying the first region of n-type Ill-nitride material to form a first porous region in the sub-surface layer, the first porous region having a first structure, a first porosity and first dimensions; in which the second region is either not porosified, or in which the second region is porosified to form a second porous region which does not have the same structure, porosity and dimensions as the first porous region.

The method of the fourth aspect is preferably a method of manufacturing a template wafer according to the third aspect of the invention described above.

Porous regions may be formed by porosifying n-doped regions of Ill-nitride material using the porosification process as set out in international patent applications

PCT/GB2017/052895 (published as WO2019/063957) and PCT/GB2019/050213 (published as WO2019/145728).

In a preferred embodiment, the second region of Ill-nitride material may be n-type Ill-nitride material, and the method comprises the step of electrochemically porosifying the second region of n-type Ill-nitride material to form the second porous region in the sub-surface layer.

The wafer preferably comprises a substrate and a plurality of layers of semiconductor material on the substrate, preferably a plurality of layers of Ill-nitride semiconductor material on the substrate. The second n-type region is preferably a sub-surface n-type region positioned below a surface layer of the wafer, and the second n-type region is preferably porosified by through- surface etching through the surface layer.

In an alternative embodiment, the second region of Ill-nitride material may be undoped, so that the second region is not porosified during electrochemical porosification of the n-doped first region.

The surface of the wafer may be selectively masked with a masking layer prior to through- surface electrochemical porosification, so that the regions of the wafer underneath the masking layer are not porosified.

In some preferred embodiments, the charge carrier density of the n-type second region may be the same as a charge carrier density of the n-type first region which becomes the first porous region, but the surface area of the wafer is selectively masked during porosification so that the n-type second region remains non-porous. The use of the masking layer may thus enable the selective porosification of the first porous regions.

Alternatively, the charge carrier density of the n-type second region may be different from a charge carrier density of the n-type first region which becomes the first porous region. As porosification depends in large part on the conductivity of a given region of material, this difference in charge carrier density may lead to different porosity characteristics in the first and second porous regions after both have been porosified.

The method of manufacturing the template wafer may comprise the step of controlling the charge carrier concentration of the regions to be porosified by ion implantation or doping specific regions to decrease or increase the conductivity of those regions. Regions of Ill- nitride material with higher n-type conductivity are more porosifiable, so selectively controlling the conductivity of individual regions means that the regions to be porosified can be individually positioned, and the desired porosity characteristics can be determined in advance. Differences in doping levels in different regions may advantageously mean that, even if the different regions are porosified simultaneously, or separately using the same etching conditions, the resulting porosity characteristics will be different in these different regions.

The method may comprise the step of doping regions of the wafer with nitrogen or magnesium to reduce the n-type conductivity of those regions. The method may comprise the step of doping regions of the wafer with Si, Ca or O to increase n-type conductivity of those regions.

The first region preferably occupies a portion of a layer of semiconductor material in the wafer, and the n-type first region is preferably porosified by etching through the surface layer. The second region preferably also occupies a portion of a layer of semiconductor material in the wafer. Particularly preferably the second region is positioned in the same wafer layer as the first region.

The method may comprise a step of masking the surface layer of the wafer with a masking layer prior to porosification, patterning the masking layer to expose an array of first device areas, and porosifying an array of first porous regions through the exposed first device areas on the surface layer. By selectively patterning the masking layer to expose predetermined areas on the wafer surface, the lateral dimensions of the sub-surface regions to be porosified can be defined. This allows specific first and/or second porous regions to be formed in the wafer in desired lateral positions in the wafer.

In preferred embodiments, the first porous region and the second porous region are porosified one at a time, by masking the surface area over a given n-type region while the other n-type region is porosified.

A second device area of the surface layer, positioned above the second region of Ill-nitride material, may be masked with a masking layer during porosification of the first porous region, so that the second region is not porosified during porosification of the first porous region.

A first device area of the surface layer, positioned above the first region of Ill-nitride material, may be masked with a masking layer during porosification of the second porous region, so that the first region under the first device area is not porosified during porosification of the second porous region.

Prior to porosification, the surface layer is preferably masked with a masking layer of photoresist material, or a layer of dielectric material (for example SiO ₂ or SiN _x or other dielectrics), or a layer of polymer (both negative or positive). Preferably the masking layer thickness is at least 10nm, or at least 50nm, or at least 100 nm, or at least 200 nm, or at least 1 pm, or at least 2 pm, or at least 5 pm, or at least 10 pm. In order to introduce different porosity characteristics in the second region, the second porous region may be porosified using different etching conditions from those used to porosity the first porous region. For example the second porous region may be porosified using a different etching electrolyte to the electrolyte used during porosification of the first porous region. The electrolyte used during porosification of the first and/or second porous regionsis preferably selected from the list: Oxalic acid, KOH, NaOH, HF, nitric acid, HCL

At least one of the first and/or second porous regions is porosified using photoelectrochemical etching under illumination, for example UV or white light illumination. Different illumination is used during porosification of the first and second porous regions, or illumination may be used during porosification of only one of the first or second porous regions.

Porosification of the second porous region may be carried out at a different temperature to porosification of the first porous region. For example porosification may be carried out at a temperature in the range of -150 ^e C to +150 ^e C.

Porosification of the second porous region may be carried out at a different pressure to porosification of the first porous region. For example the pressures during porosification may be in the range from atmospheric pressure of 760 Torr, to low vacuum 10 ^-3 Torr, to medium vacuum 10 ³ -10 ⁵ Torr.

The second porous region may have a second thickness different from the thickness of the first porous region. The thickness of the porous region(s) is not particularly limited, but may be greater than 1 nm, more preferably greater than 10 nm, particularly preferably at least 40 nm or 50 nm or 100 nm

The first region may be a different size and/or shape and/or geometry to the second region. For example in some embodiments the first porous region may have larger lateral dimensions than the second region, so that the first device area formed over the first porous region may be made larger than the second device area formed over the second region.

The porosity of the porous region(s) is preferably controlled by the electrochemical etching process carried out to porosity said porous region. The porosity of the first porous region and/or the second porous region may be between 1 %-99 % porosity, preferably between 20% to 90% porosity or between 30% - 80% porosity. The porous region(s) may comprise a continuous layer section of porous Ill-nitride material, which occupies a portion of a wafer layer of otherwise non-porous Ill-nitride material. The porous region(s) may comprise a single layer section of porous GaN, or a single layer section of porous InGaN, or a stack comprising one or more layers of porous GaN and/or one or more layers of porous InGaN.

In a particularly preferred embodiment, the wafer comprises a plurality of first regions of Ill- nitride material beneath the surface layer, and a plurality of second regions of Ill-nitride material beneath the surface layer. The plurality of first regions are preferably porosified simultaneously. The areas of the surface layer positioned above the second regions may be masked with a masking layer during porosification of the first regions. The plurality of first regions preferably form an array of discrete “islands” of first regions occupying separate lateral positions in a sub-surface layer. The plurality of second regions preferably form an array of discrete “islands” of second regions occupying separate lateral positions in a sub-surface layer.

Following porosification, the wafer is preferably patterned with a plurality of first porous regions, and a plurality of second regions, which are optionally second porous regions. The wafer may be patterned with further porous regions having different structures, porosity characteristics or dimensions.

Method of Manufacturing an Array of Semiconductor Devices

In a fifth aspect, the present invention provides a method of manufacturing a monolithic array of semiconductor devices on a wafer, the method comprising the steps of: providing a first device area on the wafer above a first porous region in the wafer, the first porous region having a first structure, first porosity and first dimensions; forming a first semiconductor device by depositing a semiconductor device structure over the first device area; and forming a second semiconductor device by depositing the same semiconductor device structure over a second device area on the wafer; in which the second device area is not positioned over a porous region having the same structure, porosity and dimensions as the first porous region.

The first and second semiconductor devices have the same device structure but respond differently in response to the same driving conditions. The method of the fifth aspect may comprise any of the steps of manufacturing the wafer according to the fourth aspect of the invention. Alternatively, the template wafer of the fourth aspect may be designed and produced separately, and the method of the fifth aspect may comprise the steps of forming semiconductor devices on the wafer.

The method of the fifth aspect is preferably a method of manufacturing a monolithic array of semiconductor devices according to the first aspect of the invention described above. Features of the wafer and the monolithic array which are described above may apply equally to the method of the fifth aspect of the invention.

The first semiconductor device is overgrown on the first device area with the porous region underneath. By overgrowing the first semiconductor device over the first porous region, the present inventors have found that the first semiconductor device will be affected by the underlying first porous region, as the crystal structure of the first semiconductor device inherits certain properties from the underlying porous material which affect the performance of the first semiconductor device. Porous region characteristics including the first porosity and first dimensions (thickness and/or lateral dimensions) of the first porous region affect the crystal structure of the overgrown first semiconductor device, and thus affect the behaviour of the first semiconductor device.

The second semiconductor device, however, is not overgrown over a porous region having the same properties as the first porous region.

The semiconductor devices are formed using conventional semiconductor deposition techniques known in the art.

In a first preferred embodiment, the second semiconductor device may be formed over a second porous region which is not identical to the first porous region - for example a second porous region having a porosity and/or dimensions that are different from those of the first porous region. In this case, the different porosity and/or dimensions of the second porous region will affect the overgrown second semiconductor device differently to the effect of the first porous region on the first semiconductor device. The electronic and/or optical characteristics of the second semiconductor device will therefore be different from those of the first semiconductor device, even though the device structures are identical.

Alternatively, in a second preferred embodiment, the second semiconductor device may not be positioned over a porous region. In other words, the wafer may be entirely non- porous underneath the second device area. In this embodiment, the second semiconductor device is overgrown over a non-porous section of wafer with no porous material underlying the second device area, so the electronic and/or optical characteristics of the second semiconductor device are not affected by the presence of any porous region under the device. The electronic and/or optical characteristics of the second semiconductor device will therefore be different from those of the first semiconductor device, even though the device structures are identical, because the first semiconductor device is affected by underlying porous material while the second semiconductor device is not.

In a first preferred embodiment, the second device area is formed over a second porous region of the wafer, the second porous region having a second porosity different from the first porosity, and/or dimensions different from the first dimensions.

The method may preferably comprise the step of forming an array of first device areas on the surface of the wafer, above a corresponding array of first porous regions in the wafer, and forming an array of second device areas on the wafer, above a corresponding array of second porous regions in the wafer.

In a second preferred embodiment, the second semiconductor device is not positioned over a porous region. In other words, the footprint of the wafer that is directly underneath the second device area is non-porous through its entire thickness. There may be no porous semiconductor material positioned directly between the substrate of the wafer and the second semiconductor device.

In this embodiment, the second semiconductor device is overgrown over a non-porous section of wafer with no porous material underlying the second device area, so the electronic and/or optical characteristics of the second semiconductor device are not affected by the presence of any porous region under the device. The electronic and/or optical characteristics of the second semiconductor device will therefore be different from those of the first semiconductor device, even though the device structures are identical, because the first semiconductor device is affected by underlying porous material while the second semiconductor device is not.

The first device area and/or the second device area may be defined by an exposed area of the wafer surface where the masking layer has been removed. The method may comprise the step of forming an array of first device areas on the wafer, above a corresponding array of first porous regions in the wafer, and forming an array of second device areas on the wafer, in which the second device areas are not positioned over porous regions of the wafer. The method may comprise the step of forming, on the array of first device areas and second device areas, respective arrays of first and second semiconductor devices having the same device structure. The arrays of first and second semiconductor devices are preferably formed simultaneously using a single epitaxial growth process.

The first device area may be a different size and/or shape and/or geometry to the second device area. In one preferred embodiment, the first device area is larger than the second device area. The first semiconductor device and second semiconductor devices are preferably formed to fill their respective device areas, so this allows the first semiconductor device to be grown with larger lateral dimensions (a larger area, or footprint) than the second semiconductor device.

The first and second device areas are preferably formed on a non-porous surface layer of the wafer.

The first and second semiconductor devices are preferably formed simultaneously by depositing the semiconductor device structure on a plurality of device areas on the wafer. All of the semiconductor devices may be deposited in a single device epitaxy.

The method may comprise the steps of forming electrical contacts which are operatively coupled to the first and second semiconductor devices, such that the first and second semiconductor devices are independently driveable.

As described above in relation to the first aspect, the semiconductor devices may be a variety of different semiconductor device types.

In a preferred embodiment, the semiconductor device structure is an optoelectronic device structure, such as a light-emitting diode (LED) or a vertical cavity surface emitting laser (VCSEL), so that both the first and second semiconductor devices are optoelectronic devices.

Alternatively the semiconductor device structure may be an electronic or electrical component, such as a high electron mobility transistor (HEMT) or a radio frequency (RF) device. The semiconductor device structure may be a high electron mobility transistor (HEMT), such that the first and second semiconductor devices are both HEMTs. Or the semiconductor device structure may be a radio frequency device, such that the first and second semiconductor devices are both radio frequency devices.

Particularly preferably the semiconductor device structure is an LED structure, for example a mini-LED, micro-LED or nano-LED structure.

Preferably the first semiconductor device and the second device are each LED subpixels, such that the first and second semiconductor devices form a device pixel.

Method of Manufacture of Variable-Wavelength LED

As described above, in a preferred embodiment of the present invention the semiconductor devices formed on the wafer may be variable-wavelength LEDs.

The method of manufacturing a monolithic array of semiconductor devices on a wafer may thus comprise forming variable-wavelength LEDs. The method may comprise the steps of forming a variable-wavelength LED by depositing a variable-wavelength LED device structure over the first device area; and forming a second variable-wavelength LED by depositing the same variable-wavelength LED device structure over a second device area on the wafer.

Forming a variable-wavelength LED may comprise the step of growing: an n-doped portion; a p-doped portion; and a light-emitting region located between the n-doped portion and a p-doped portion, the light-emitting region comprising a light-emitting layer which emits light at a peak emission wavelength under electrical bias thereacross.

The method may comprise the step of overgrowing the n-doped portion, the p-doped portion and the light-emitting region over a porous region of Ill-nitride material.

The method may comprise the step of forming a porous region of Ill-nitride material in at least one of the n-doped portion or the p-doped portion, and forming the light-emitting region over a porous region of Ill-nitride material. The light-emitting layer may emit light at a peak emission wavelength between 400 and 800 nm, or between 450-800nm, or between 500 and 800 nm, or between 550 and 800 nm, or between 610 and 800 nm under electrical bias thereacross.

The method may comprise the step of connecting the variable-wavelength LEDs to a variable power supply.

The method may comprise the step of connecting the variable-wavelength LEDs to an LED driver configured to provide a variable power supply to the LED. The LED driver may be configured to control the power or the current or the voltage of the power supply to the LED. The LED driver may be configured to provide a pulsed, or CW, or quasi-CW power supply to the LED.

The variable-wavelength LED structure, including the n-doped portion, the p-doped portion, and the light-emitting region, may be an LED structure for emitting at a wavelength lower than the peak emission wavelength of the LED, so that the porous region of Ill-nitride material red-shifts the emission wavelength of the light-emitting region to the peak emission wavelength.

The n-doped portion, the p-doped portion and the light-emitting region are preferably formed from Ill-nitride semiconductor material.

In a preferred embodiment, the light-emitting region may comprise a light-emitting indium gallium nitride layer for emitting at a peak wavelength of 500 nm - 550nm or 550 nm - 600 nm, wherein overgrowth on the porous region of Ill-nitride material shifts the emission wavelength of the light-emitting region to a peak wavelength between 600 and 750 nm under electrical bias.

The light-emitting region may comprise a light-emitting indium gallium nitride layer for emitting at a peak wavelength of 500 - 550 nm, or 500-580 nm, or 510 to 570 nm, or 530 nm to 560 nm, or 550 nm to 600 nm. The light-emitting indium gallium nitride layer may be one or more layers known to emit at these wavelengths when grown in conventional LEDs, for example on non-porous GaN substrates. However, the inventors have found that growing conventional yellow or green LED structures over a porous Ill-nitride layer leads to an LED that emits at a peak wavelength between 600 and 750 nm under electrical bias.

The method may comprise the step of growing a yellow or green LED structure over a porous region of Ill-nitride material. In preferred embodiments, the light emitting layer is a light-emitting indium gallium nitride layer. The LED preferably also comprises a region of GaN material. Due to the lattice mismatch between GaN and InGaN, the stress relaxation effect created by the porous region is particularly advantageous.

The method may comprise the step of forming the light emitting active region with carrier localisation centres in the quantum wells (which are preferably InGaN QWs). such as multiple types of QW region with different Indium composition and well width and quantum barriers, non-uniform, or fragmented, or broken, or gappy, or discontinuous quantum wells which would result in fluctuation in the well width, InGaN quantum dots or nanostructures, quantum wells formed on polar, semi-polar or non-polar facets.

The method may comprise the step of forming a plurality of quantum wells (QWs), in which the quantum wells are non-uniform, fragmented, or discontinuous.

The plurality of QWs may comprise fluctuations in indium composition, and/or well width fluctuations.

The method may comprise the step of forming one or more v-shaped pits in each variablewavelength LED structure, so that the v-shaped pit extends through the thickness of the light-emitting region. Preferably the method comprises the step of forming at least 0.1 v- shaped pits per square micrometre, or at least 1 v-shaped pits per square micrometre, or at least 2 v-shaped pits per square micrometre. Preferably the method comprises the step of forming a density of v-shaped pits in the light-emitting region of at least 1 x 10 ⁷ /cm ² , for example at least 5 x 10 ⁷ /cm ² or at least 1 x 10 ⁸ /cm ² , for example a density of v-shaped pits of 1 x 10 ⁷ /cm ² to 5 x 10 ⁹ /cm ² . Preferably the method comprises the step of forming a density of v-shaped pits in the light-emitting region of less than 5 x 10 ⁹ /cm ² , for example a density of v-shaped pits of less than 1 x 10 ⁹ /cm ² or less than 5 x 10 ⁸ /cm ² .

V-shaped pits are a phenomenon known in the art of epitaxial semiconductor growth, and methods of growing v-shaped pits in semiconductor structures are known in the art. For example, v-shaped pits and their growth are described in the prior art in The effect of nanometre-scale V-pits on electronic and optical properties and efficiency droop of GaN- based green light-emitting Diodes; Zhou et al; Scientific Reports | (2018) 8:11053 | DOI:10.1038/S41598-018-29440-4. V-shaped pits may be grown in the semiconductor structure so that they terminate in a layer below the active light-emitting region. This means that the v-shaped pits must extend through the thickness of the active light-emitting region.

V-shaped pits may be grown from threading dislocations in the semiconductor structure by controlling the growth conditions during epitaxial deposition of layers above a layer containing a threading dislocation. The threading dislocations are perpetuated upwards through the structure as additional layers are grown over layers containing a threading dislocation, and by controlling growth conditions the dislocation is widened into a v-shaped pit.

V-shaped pits can alternatively be grown using 3-dimensional epitaxial growth modes. 3D epitaxial deposition techniques are known in the art and are typically used to grow “islands” or “pyramids” of semiconductor material on a template. By controlling deposition of the LED structure using 3D epitaxial deposition techniques, v-shaped pits can be artificially grown in desired locations, with no need for a threading dislocation to be present to “seed” the formation of the v-shaped pit. By using this deposition control, the bottom (nadir) of the pit may be created at a desired location in the structure - both a desired lateral position and a desired height in the structure, for example in a particular layer of the semiconductor structure below the active light-emitting region.

The bottom of the v-shaped pit may be located in the connecting layer of the semiconductor structure. The connecting layer may be positioned between the porous region and the n-doped portion.

The bottom of the v-shaped pit may be located in a pre-strain layer of the semiconductor structure. The pre-strain layer may be positioned above the n-doped portion and below the light-emitting region.

Preferably each variable-wavelength LED comprises a plurality of v-shaped pits which extend through the active light-emitting region.

Both the density and size (the depth) of the v-shaped pits may be controlled. The size of the V-pits can be controlled by the position and the growth conditions of the pre-strain layer and the low-temperature nGaN layer where the pits started. Quantum wells (QWs) in the active light-emitting region may be deposited so that the quantum wells are continuous and/or of uniform thickness. Alternatively quantum wells (QWs) in the active light-emitting region may be deposited so that the quantum wells are fragmented, or discontinuous.

Manufacturing Steps - Variable Wavelength LED

The n-type region, the light-emitting region and the p-type region (which may be called the LED structure) are preferably grown over a semiconductor wafer template which contains at least the first porous region, and optionally further porous regions having different porosity characteristics. The semiconductor wafer template may also contain a number of layers of semiconductor material arranged to provide a suitable substrate for the overgrowth of the LED structure.

The method may comprise the first step of electrochemically porosifying a layer of Ill-nitride material, to form the porous region of Ill-nitride material. This may be achieved using a wafer scale porosification process as set out in international patent applications PCT/GB2017/052895 (published as WQ2019/063957) and PCT/GB2019/050213 (published as WQ2019/145728).

The method may preferably comprise the step of forming the porous region of Ill-nitride material by electrochemical porosification through a non-porous layer of Ill-nitride material, such that the non-porous layer of Ill-nitride material forms a non-porous intermediate layer. The non-porous intermediate layer may advantageously provide a smooth surface for overgrowth of further layers, such as one or more connecting layers of Ill-nitride material.

The porous region may be formed by porosifying one or more layers or regions of Ill-nitride material on a substrate. The substrate may be Silicon, Sapphire, SiC, p-Ga2O3. The crystal orientation of the substrates can be polar, semi-polar or non-polar orientation. The substrate thickness may typically vary between 100 pm and 1500 pm.

The porous region may be a porous layer, such that the method comprises the step of overgrowing, over a porous layer of Ill-nitride material: an n-doped portion; a p-doped portion; and an LED light-emitting region. Preferably the porous region may be a porous layer that is continuously porous, for example formed from a continuous layer of porous Ill- nitride material. The porous region may comprise a plurality of porous layers, and optionally a plurality of non-porous layers. In preferred embodiments of the invention, the porous region is a stack of alternating porous and non-porous layers, with the top surface of the stack defining the top of the porous region, and the bottom surface of the stack defining the bottom of the porous region.

Alternatively the porous region may be a layer of Ill-nitride material that contains one or more porous regions, for example one or more porous regions in an otherwise non-porous layer of Ill-nitride material.

In preferred embodiments, the porous region, or porous layer, may have a lateral dimension (width or length) equivalent to that of the substrate on which the porous layer or region is grown. For example, conventional substrate wafer sizes may have a variety of sizes, such as 1 cm ² , or 2 inch, 4 inch, 6 inch, 8 inch, 12 inch, or 16 inch diameter. By patterning one or more layers and/or depositing regions of different charge carrier concentrations in the same layer, however, smaller porous regions can be formed that do not span the entire substrate. The lateral dimensions of the porous layer or region may therefore vary from around 1/10 of a pixel (for example 0.1 pm), up to the lateral dimensions of the substrate itself.

Prior to the porosification step, a doped region of n-doped Ill-nitride semiconductor material, preferably containing a layer, or stack of layers, may be deposited on a substrate. The Ill-nitride layer(s) may contain one or a combination of these elements: Al, Ga, In (ternary of quaternary layer). The thickness of the Ill-nitride stack is preferably between I Q- 4000 nm. The Ill-nitride region may have a doping concentration between 1 x10 ¹⁷ cm ^-3 - 5x10 ²⁰ cm' ³ .

Preferably an intermediate layer of undoped Ill-nitride material is deposited over the doped material before it is porosified. The intermediate layer preferably has a thickness of between 1 nm and 3000 nm, preferably between 5 nm and 2000 nm. As the intermediate layer is undoped, it remains non-porous after the porosification step, which advantageously provides a good surface for epitaxial overgrowth of further layers of semiconductor.

In preferred embodiments, the doped region consists of an alternating stack of doped and undoped layers. In preferred embodiments the stack contains between 5-50 pairs of layers. The thickness of each highly doped layer may vary between 10 nm - 200 nm and low- doped or undoped layers may have a thickness of between 5-180 nm. As is known in the art, electrochemical porosification removes material from n-type doped regions of Ill-nitride materials, and creates empty pores in the semiconductor material.

In preferred embodiments, the LED structure is formed over a stack of multiple porous layers of Ill-nitride material. Thus, rather than being a single porous layer of Ill-nitride material, the porous region may be a stack of layers of Ill-nitride material in which at least some layers are porous. The stack of porous layers may preferably be a stack of alternating porous and non-porous layers.

The method may preferably comprise the step of depositing one or more connecting layers of Ill-nitride material on the surface of the intermediate layer of Ill-nitride material prior to overgrowing the n-doped region, the LED light-emitting region and the p-doped region on the connecting layer.

Alternatively, where there is no non-porous intermediate layer over the porous region, the method may comprise the step of depositing a connecting layer of Ill-nitride material onto the surface of the porous region of Ill-nitride material.

The method may comprise the further step of overgrowing the n-doped region, the LED light-emitting region and the p-doped region on the connecting layer.

The variable-wavelength LEDs produced by the method of manufacture are preferably variable-wavelength LEDs as described above in relation to the first aspect.

Manufacturing a Display Device

In a sixth aspect, the invention may provide a method of manufacturing a display device, comprising manufacturing an array of semiconductor devices on a wafer according the fifth aspect of the invention described above. In the method of the sixth aspect, the first and second semiconductor devices are each LED subpixels, such that the first and second semiconductor devices form a device pixel, and the method comprises forming an array of multiple device pixels on the wafer.

As all of the aspects of the invention described above are interrelated, any features described in relation to one aspect of the invention may equally be applied to any of the other aspects of the invention. It should also be understood that the methods and structures of the present invention are not limited to the particular examples described herein, but can be implemented in other examples without departing from the scope of the disclosure.

Brief Description of the Drawings

Specific embodiments of the invention will now be described with reference to the figures, in which:

Figure 1 is a schematic side-on cross-section of a template wafer according to an aspect of the present invention;

Figure 2 is a schematic side-on cross-section of a monolithic array of two semiconductor devices, according to an aspect of the present invention;

Figure 3 is a schematic side-on cross-section of a monolithic array of three semiconductor devices, according to an aspect of the present invention;

Figure 4 is a schematic side-on cross-section of the device of Figure 3, processed into a display device;

Figure 5A is a schematic plan view of a semiconductor wafer according to an embodiment of the present invention, prior to porosification;

Figure 5B is a schematic plan view of the semiconductor wafer of Figure 5A, following porosification of the first porous regions;

Figure 6A is a schematic plan view of a semiconductor wafer according to an embodiment of the present invention, prior to porosification;

Figure 6B is a schematic plan view of the semiconductor wafer of Figure 6A, following porosification of the first and second porous regions;

Figure 6C is a schematic plan view of the semiconductor wafer of Figure 6B, following overgrowth of an array of first semiconductor devices and an array of second semiconductor devices according to a preferred embodiment of the present invention;

Figure 7 is a schematic plan view of a monolithic array of semiconductor devices of two different types on a wafer, according to a preferred embodiment of the present invention; Figure 8 is a schematic plan view of a wafer template comprising an array of first porous regions and second non-porous regions, according to a preferred embodiment of the present invention;

Figure 9 is a schematic plan view of the semiconductor wafer of Figure 8, following overgrowth of an array of first semiconductor devices over the first porous regions and an array of second semiconductor devices over the second non-porous regions according to a preferred embodiment of the present invention;

Figure 10 is a schematic plan view of a wafer template comprising an array of first porous regions and second non-porous regions, according to a preferred embodiment of the present invention;

Figure 11 is a schematic plan view of the semiconductor wafer of Figure 10, following overgrowth of an array of first semiconductor devices over the first porous regions and an array of second semiconductor devices over the second non-porous regions according to a preferred embodiment of the present invention;

Figure 12A is a plan view optical microscopy image of a semiconductor wafer prior to porosification;

Figure 12B is a plan view image of the semiconductor wafer of Figure 12B after porosification;

Figure 13 is a plan view optical microscopy image of a patterned semiconductor wafer in which a cross-shaped porous region has been formed in a specific wafer layer, surrounded by non-porous semiconductor material;

Figure 14 illustrates the different emission wavelengths produced by the same epitaxial LED structure positioned over a porous region of semiconductor wafer, and by contrast over a non-porous region of semiconductor wafer;

Figure 15 is a series of five EL images of the same MicroLED pixel being driven at different currents in constant wave mode (CW), showing five different colours of emission;

Figure 16A is an emission wavelength vs current density plot for a 25 pm x 25 pm 100 x 100 variable-wavelength LED pixel array driven in pulsed mode with a 100 ps pulse at 1% duty cycle; Figure 16B is an emission wavelength vs current density plot for a 30 pm x 30 pm 100 x 100 variable-wavelength LED pixel array driven in pulsed mode with a 100 ps pulse at 1% duty cycle;

Figure 17 is a plot of intensity vs wavelength for a single variable-wavelength LED driven at different currents in pulsed driving mode with a 100 ps pulse at 1% duty cycle;

Figures 18A-G illustrate alternative embodiments of non-uniform, fragmented or discontinuous light-emitting regions of variable-wavelength LEDs usable in preferred embodiments of the present invention;

Figure 19A is a TEM image of a cross-section of a conventional non-variable-wavelength LED;

Figure 19B is a TEM image of the light-emitting region of a variable-wavelength LED comprising v-shaped pits, usable in embodiments of the present invention;

Figure 19C is a TEM image of the variable-wavelength LED of Figure 19B, showing a porous region and a light-emitting region comprising a plurality of v-shaped pits, usable in a preferred embodiment of the present invention;

Figure 20A is a graph of peak emission wavelength vs driving current density for a conventional non-variable wavelength LED;

Figure 20B is a graph of peak emission wavelength vs driving current density for a variablewavelength LED according to an embodiment of the present invention;

Figure 20C is a graph of peak emission wavelength vs driving current density for a variable-wavelength LED according to another embodiment of the present invention;

Figure 21 A is a graph of peak emission wavelength vs driving current density for another variable-wavelength LED usable in embodiments of the present invention; Figures 21 B-D are photographs of the variable-wavelength LED of Figure 21 A, with inset emission spectra showing the different peak emission wavelengths at different driving current densities.

Figure 1 illustrates a porous template wafer 10 suitable for processing into a monolithic array of semiconductor devices according to the present invention.

The porous template comprises a porous region of Ill-nitride material occupying part of a layer of otherwise non-porous Ill-nitride material on a substrate. A non-porous buffer layer 20 is positioned between the substrate and the layer containing the porous region, and a non-porous surface layer 30 of Ill-nitride material is arranged over the top surface of the porous region. Optionally there may be further layers of Ill-nitride material between the substrate and the porous region, and between the porous region and the surface of the wafer 10.

The porous region may be created by epitaxially growing a layer of Ill-nitride material over the substrate, in which a section of the layer is formed from n-doped Ill-nitride material, and another section of the same layer is formed from undoped Ill-nitride material. An undoped layer of Ill-nitride material is then deposited over the top of the layer containing the n-doped material. The porous region is then formed by porosifying the n-doped region using the porosification process as set out in international patent applications PCT/GB2017/052895 (published as WO2019/063957) and PCT/GB2019/050213 (published as WO2019/145728), while the undoped material in the template wafer remains non-porous.

As described above, this porosification leads to strain relaxation in the crystal lattice, which means that subsequent overgrowth of further semiconductor layers benefit from reduced compressive strain in their lattices.

Following the porosification step, the wafer 10 contains a porous region which remains where there was previously n-doped Ill-nitride material, and a non-porous surface layer 30 overlying the porous region.

The degree of porosity of the porous region is controlled by the electrochemical etching process and the initial doping level of the n-type Ill-nitride material which is porosified. The porosity of the porous region may be controlled to be between 1 %-99 % porous, preferably between 20% to 90% porous or between 30% - 80% porous, though lesser or greater porosities could also be employed.

The thickness of the porous region following porosification depends on the starting structure of the n-type Ill-nitride material which is porosified. The thickness of the porous region is preferably greater than 1 nm, more preferably greater than 10 nm, particularly preferably at least 40 nm or 50 nm or 100 nm. However, the thickness of material required to obtain the strain relaxation benefit provided by the porous region may vary depending on the type of Ill-nitride material from which the porous region is made.

The porous region created by the porosification process may be a bulk layer of a Ill-nitride material having a uniform composition and a uniform porosity throughout the porous region. Alternatively the porous region may comprise multiple layers of porous material of different compositions and/or porosities, forming a porous stack of Ill-nitride material. For example the porous region may be a continuous layer of porous GaN, or a continuous layer of porous InGaN, or a stack comprising one or more layers of porous GaN and/or one or more layers of porous InGaN. The inventors have found that the strain relaxation benefit of the porous region for overgrowth is obtainable across a wide range of porous regions having different thicknesses, compositions, and layered stacks.

In the embodiment illustrated in the Figures, the porous region occupies a part of a single layer of the wafer 10.

The undoped cap layer 30 of Ill-nitride material over the doped region and the undoped region in the same layer as the porous region remain non-porous following through-surface porosification of the n-doped region. The thickness of the non-porous cap layer 30 may preferably be at least 2 nm, or at least 5 nm, or at least 10 nm, preferably 5-3000 nm. Providing an undoped cap layer over the doped region advantageously leads to a non- porous layer of Ill-nitride material covering the porous region following porosification. This non-porous cap layer may advantageously allow better overgrowth of further material above the porous region.

The porous region may comprise one or more layers of one or more Ill-nitride materials, and may have a range of thicknesses, all while still providing the strain relaxation benefit that affects the electronic and/or optoelectronic properties of semiconductor devices overgrown above the porous region. For example the presence of the porous region beneath an overgrown LED may shift the peak emission wavelength of InGaN light emitting layers overgrown above the porous region. In preferred embodiments, the porous region may for example comprise GaN and/or InGaN.

A variety of semiconductor device structures may be overgrown over the template wafer illustrated in Figure 1 . Although other electronic or optoelectronic semiconductor devices may be used in the present invention, the invention is illustrated in the Figures by reference to LEDs.

In particular, LED structures containing InGaN light emitting layers, which are known in the art for the manufacture of yellow or green LEDs, may be overgrown on the porous template using standard LED manufacturing steps. When grown over the porous region of the template, however, an LED device structure which normally emits at a first wavelength, will emit at a red-shifted longer wavelength.

In this way, the presence of a porous region of Ill-nitride material as a template or pseudosubstrate for overgrowth of known InGaN LED structures allows longer-wavelength LEDs to be manufactured in a straightforward manner.

In the present invention, unlike in the prior art, not all semiconductor devices on the wafer are formed over the same porous region. As shown in Figure 1 , in the present invention the porous region occupies only a portion of the lateral area of the wafer, so only a portion of the wafer’s surface layer is positioned over a porous region, while another portion of the surface layer is not positioned over a porous region.

Figure 2 illustrates a monolithic array 100 of two LED devices formed on the wafer 10 by a single epitaxy. A first LED device 150A has been formed in a first device area over the porous region, and an identical second LED device 150B, having the same epitaxial structure as the first LED device, has been formed in a second device area over the section of the wafer which does not contain a porous region. As the first LED 150A has been overgrown over a porous region of Ill-nitride material, the peak emission wavelength of the first LED 150A will be red-shifted relative to the identical second LED 150B which has not been overgrown over any porous material. Even though the two LEDs 150A, 150B are identical, and were formed monolithically in a single epitaxy, the optical emission properties of the two LEDs are therefore different. This enables monolithic integration of different colours of LED using a single device epitaxy. The properties of the porous region may be varied to tune the red-shift imparted on the overgrown LED. For example the doping level of the n-doped material to be porosified may be varied to give a different resulting porous region. The electrolyte type, or the electrolyte concentration, used during porosification may be varied to alter the properties of the resulting porous region. The etching voltage and/or current used during porosification may be varied to alter the properties of the resulting porous region. The dimensions and structure of the porous region may also be varied by varying the dimensions and structure of the n-doped Ill-nitride material deposited on the substrate. By varying these factors a wide range of porous regions may be formed, which may in turn impart a wide range of wavelength shifts on overgrown optoelectronic devices.

In some embodiments, multiple separate porous regions may be provided in a single wafer.

The separate porous regions may be formed simultaneously with the same porosification step, for example by forming two separate regions having different doping levels.

Alternatively, the separate porous regions may be formed one at a time by masking the surface layer of the wafer 10, lithographically patterning the masking layer to expose certain device areas, and then performing through-surface porosification via the exposed device areas to porosity n-doped regions beneath the exposed device areas. The exposed device areas may then be masked before exposing a seconds set of device areas and then performing through-surface porosification via the second set of exposed device areas to porosity n-doped regions beneath the second set of exposed device areas. Using this process, different porosification techniques (for example different electrolytes and etching parameters) can be carried out on the two device areas to obtain different resulting porous regions.

Figure 3 illustrates an alternative embodiment of a monolithic array 200 of three LEDs on a wafer, in which the wafer contains three separate regions each having different porosity characteristics: a first porous region, over which a first LED 150A has been overgrown; a second porous region, over which a second LED 150B has been overgrown; and a third porous region, over which a third LED 150C has been overgrown. As is the case in Figure 2, all of the LED structures are identical, as the LEDs are deposited on the wafer in a single epitaxial growth step which forms all three LEDs simultaneously. The separate LEDs 150A, 150B, 150C may be formed by masking the surface layer of the template wafer using a dielectric masking layer (not shown), and removing areas of the masking layer for example by photolithography, to expose first, second and third device areas on the surface layer. With these device areas exposed and the rest of the wafer surface masked with dielectric, the epitaxial layers of the LED structures may be deposited only in unmasked areas of the wafer’s surface layer. The first, second and third LEDs may thus be grown simultaneously by the same epitaxial deposition steps.

The porosity characteristics, such as the % porosity, the average pore size, and the dimensions of the porous regions, differ between the three porous regions. The structure of the porous regions may also differ between porous regions - for example one porous region may be a continuous layer of uniform porosity, while another porous region may comprise multiple layers of porous material. The porosity characteristics of an underlying porous region has an effect on the crystal structure of an overgrown semiconductor device. For example the % porosity of the porous region may affect the strain experienced by the overgrown semiconductor structure. Differences in the porosity characteristics of the three porous regions mean that the first, second and third LEDs overgrown over the first, second and third porous regions inherit different properties from their underlying porous regions. Even though the first, second and third LEDs are grown simultaneously with identical epitaxial structures, the different underlying porous regions will therefore create differences between the electronic/optoelectronic properties of the three LED devices.

Figure 4 illustrates the monolithic array of Figure 3, following additional processing steps which isolate the three LEDs and provide electrical contacts which allow the three LEDs to be separately controlled by providing a separate driving current to each of the LEDs on the wafer.

The present invention is not limited to any precise structure of LED device. In the schematic illustrations of the Figures, however, the layers of the LED devices are as follows:

1 - Connecting layer 1 of Ill-nitride material

2 - n-doped layer of Ill-nitride material

3 - light-emitting region

4 - non-doped cap layer

5 - electron blocking Ill-nitride layer (EBL) 6 - p-doped layer

7 - transparent conducting layer

8 - passivation layer

9 - electrical p-contacts

10 - electrical n-contacts

11 - device backplane/microdriver circuit board

The thicknesses and compositions of these layers may be varied, as is known in the art. Techniques for depositing these layers and processing the LEDs into the device of Figure 4 are well known in the art.

Figure 5A is a schematic plan view of a semiconductor wafer according to an embodiment of the present invention, prior to porosification. Figure 5B shows the same wafer, following porosification of the n-doped portions of the wafer into first porous regions. Figure 5C shows the same wafer, following overgrowth of an array of first semiconductor devices over the porous regions, and overgrowth of an array of second semiconductor devices over the non-porous regions.

In the plan views of the Figures, non-porous surface layers, which in reality are positioned above the n-doped/porous regions, are omitted for the purposes of illustration, so that the lateral footprints of the various regions within the wafer are visible.

The wafer 500 of Figure 5C is prepared by selectively doping an array of first regions 50 with n-type dopant during epitaxial growth. The wafer is patterned with first regions spaced across the wafer. This increases the charge carrier concentration in the selected n-doped first regions, while an array of second regions 60 is left undoped.

Prior to electrochemical porosification, the upper surface of the wafer is covered with a masking layer. The masking layer is then patterned and an array of selected areas of the masking layer are removed, to expose the areas of the surface layer which are positioned above the array of first regions 50. Through-surface electrochemical porosification is then carried out on the wafer 500, so that the n-type first regions 50 are porosified into an array of porous regions 55. As the rest of the wafer is undoped and masked, the rest of the wafer 500 remains non-porous after the porosification process, as shown in Figure 5B. The undoped second regions 60 are unchanged following porosification, and thus form non- porous second regions 60 of the wafer. The porous regions can be given different porous properties, e.g. by controlling the etching conditions/ambient conditions, the porosity, thickness of porous, pore size, etc can all be controlled and manipulated.

This masking and covering process can be done in one go or can be repeated several times.

The patterned areas can be of any shape/geometry/combination/configuration - i.e. any size, shape, pattern can be achieved.

The resolution of the porous patterning process can be very high, in nanometer scales, for example 1 nm, 10nm, 10Onm, 200nm, 500nm, 1 urn, 2um, 5um, 10um, 10Oum or more, this patterning resolution/definition is not limited because of the lithography techniques are much precise than this, and we have a few different ways to control/improve the resolution, i.e. etching conditions, illumination, epitaxy design of different layers, as well as implantation to enhance the etching selectivity.

As shown in Figure 5C, semiconductor devices can then be overgrown on the wafer 500.

The area of the wafer surface which is positioned above each of the porous regions 55 forms array of first device areas on which a first set of devices may be overgrown. All of the devices grown on those first device areas will experience the same porous region underneath them, so identical devices grown over the array of porous regions 55 will all perform in the same way. In Figure 5C, an array of first semiconductor devices is overgrown over the array of porous regions 55. A separate array of second semiconductor devices is overgrown over the array of non-porous regions 60.

The first and second semiconductor devices are deposited in the same device epitaxy and are thus compositionally and structurally identical to one another. However, as the first devices are overgrown above porous regions 55, while the second devices are overgrown above non-porous regions 60, the two sets of devices will exhibit different electron ic/optoelectronic characteristics.

Figures 6A-6C illustrate an alternative embodiment of the present invention, in which the second regions are n-doped regions 70 instead of undoped regions. As shown in Figure 6B, the n-doped second regions are porosified into second porous regions 75 in this embodiment - this may be done simultaneously to the porosification of the first porous regions (if the second n-doped regions 70 have a different charge carrier density to the first n-doped regions 50), or alternatively this may be done in a separate porosification step during which the first device areas are masked.

The porosity characteristics of the first porous regions 55 and the second porous regions 75 are not the same. By doping these regions to different extents, or by varying the etching parameters used to porosity the respective regions, factors such as the dimensions, layer structure, % porosity, and average pore size can be varied, so that the second porous regions are not identical to the first porous regions.

As porosification of the sub-surface n-doped regions takes place through the surface layer of the wafer 500, masking layers of electrically-insulating material can be deposited on the surface layer and patterned to expose selected areas of the wafer’s surface layer. Through- surface porosification may then take place through the exposed areas to porosity any n- doped sub-surface material beneath the exposed area, while regions of material positioned below the masked sections of the surface layer remain non-porous regardless of their conductivity.

By masking the surface layer over the first regions while the second regions are porosified through exposed areas on the surface layer above the second regions, and vice versa, different etching parameters can be used to etch the first regions and the second regions. For example different etching voltages and/or currents may be used, or different electrolytes may be used. This may advantageously allow the porosity characteristics of these regions to be varied to a greater extent than may be possible by varying the charge carrier density of these regions alone.

As shown in Figure 6C, similarly to Figure 5C, an array of first semiconductor devices is overgrown over the array of porous regions 55, and a separate array of second semiconductor devices is overgrown over the array of second porous regions 75. In Figure 6C, however, the second semiconductor devices are overgrown over porous material, so the performance of the second devices will be different from the same device in the embodiment of Figure 5C.

The first and second semiconductor devices in Figure 6C are deposited in the same device epitaxy and are thus compositionally and structurally identical to one another. However, as the first devices are overgrown above first porous regions 55, while the second devices are overgrown above second porous regions 75 with different porosity characteristics, the two sets of devices will exhibit different electron ic/optoelectronic characteristics. Figure 7 is a schematic plan view of a monolithic array of semiconductor devices of two different types on a wafer, according to a preferred embodiment of the present invention.

A variety of different semiconductor devices may be overgrown on the wafer, as described above. Regardless of what type of device structure is overgrown, if the template wafer contains localised patterned porous and non-porous regions underneath the devices, the optical and electrical characteristics of the devices will be different depending on which region of the wafer they are formed.

Before devices are overgrown on the wafer, the surface layer may be masked, and then lithographically patterned to expose arrays of first and second device areas. The first device areas are positioned above the first porous regions 55, while the second device areas are positioned above the second regions 60 (or second porous regions 75). Devices may be overgrown on the wafer by known epitaxial deposition techniques, such that layers of device structures are deposited only in the exposed areas of the wafer surface which are not masked. In this way the lateral size and shape of the devices may be controlled. Thus mini-LED, micro-LED (pLED) or even nano-LED pixels may be grown by varying the size of the exposed areas patterned into the masking layer before overgrowth, so that the pixels or subpixels are aligned over the porous/non-porous regions.

In a particularly preferably embodiment, LEDs may be formed on the wafers. As described above, the LEDs may be single colour LEDs, in which the peak emission wavelength of LEDs over porous material are red-shifted relative to the same device structure over non- porous wafer sections. Alternatively variable-wavelength LEDs may be formed on the wafer, such that the peak emission wavelength of the variable-wavelength LEDs are tuneable over a wide wavelength range by varying the driving current provided to the variable-wavelength LED.

In the illustrated embodiment of Figure 7, arrays of two types of variable-wavelength LED devices are formed over a wafer like that of Figure 5B or 6B. As described above, the variable-wavelength LEDs are preferably formed over porous regions of Ill-nitride material, with discontinuities in their light-emitting regions (for example a high density of v-pits extending through the light-emitting region) which enable light emission across a wide wavelength range.

In Figure 7, red-green variable-wavelength LEDs are shown overgrown over the first porous regions 55, and green-blue variable-wavelength LEDs are shown formed over the second porous regions 75. The different emission wavelength ranges of the two LED types may be determined by the different properties of the first and second porous regions, respectively. The peak emission wavelength of each LED may then be individually controlled within its given wavelength range, by varying the driving conditions provided to that LED.

From a single LED structure epitaxy, it is thus possible to form a first array of pixels that can emit red-green due to the underlying first porous region 55, and a second array of pixels that can emit green/blue due to the underlying second porous region 75. This advantageously allows the two arrays of LEDs, formed on a monolithic single wafer from a single device epitaxy, to emit a wide range of wavelengths.

Although the Figures illustrate regular square arrays of LEDs, alternative arrangements are of course possible.

Figure 8 is a schematic plan view of a wafer template comprising an array of first porous regions and second non-porous regions, according to a preferred embodiment of the present invention.

By controlling the charge carrier concentration of the sub-surface n-type regions, and optionally the exposed areas formed in the masking layer prior to porosification, the size and shape of the porous regions and the non-porous regions can be controlled. The porous region can be controlled to be equal, bigger or smaller, or a different shape, than the non- porous region.

In Figure 8, first device areas are positioned on the surface area directly over the porous regions, while second device areas are positioned on the surface area directly over the non-porous regions. These first device areas are a different size from the second device areas positioned over the non-porous regions. LEDs overgrown on the first device areas will thus have larger lateral dimensions than LEDs overgrown over non-porous material on the second device areas. By overgrowing LEDs of different lateral sizes, the emitting area of the LEDs may be varied, which may in turn determine the brightness of the emitted light.

Figure 9 is a schematic plan view of the semiconductor wafer of Figure 8, following overgrowth of an array of first semiconductor devices over the first porous regions and an array of second semiconductor devices over the second non-porous regions according to a preferred embodiment of the present invention. Figure 9 illustrates a particularly preferred embodiment, in which a conventionally green LED structure is overgrown on the wafer. The porous regions of Figure 9 underlie the first LEDs, which creates a red-shift in the peak emission wavelength of those LEDs, while the second LEDs are formed over non-porous sections of wafer which does not shift their emission wavelength. This difference in emission wavelength, caused by the porous regions in the wafer, means that the first LEDs emit peak emission wavelengths which are red, while the identical second LEDs emit peak emission wavelengths which are green/blue.

As red LEDs typically emit light at a lower brightness than green/blue LEDs, the larger lateral size of the first (red) LEDs may advantageously help to provide brightness compensation.

The ratio of the lateral areas occupied by the porous/non-porous regions can be controlled to be greater, smaller or equal to one another. For example the porous region underlying the red LED may have a lateral area that is 2 times larger than the lateral area of the non- porous region underlying the green/blue LED.

In the embodiment of Figure 9, each LED forms a subpixel, and each pair of subpixels (one red, plus one green/blue) forms a device pixel.

LEDs of different colours may alternatively be formed on the wafer in a corresponding manner.

Figure 10 is a schematic plan view of a wafer template comprising an array of first porous regions and second non-porous regions, according to a preferred embodiment of the present invention.

In the embodiment of Figure 10, an array of porous regions are formed in the wafer, interspersed with an array of non-porous regions. The arrays of porous and non-porous regions are positioned relative to one another to form pairs of porous and non-porous regions, with additional porous regions positioned between adjacent pairs. The lateral size of the porous regions is larger than the lateral size of the non-porous regions.

The arrangement of the porous and non-porous regions in the template wafer of Figure 10 is selected to provide a template for overgrowth with LEDs in order to produce a monolithic array of LEDs as shown in Figure 11 . Figure 11 is a schematic plan view of the semiconductor wafer of Figure 10, following overgrowth of an array of first LEDs over the porous regions and an array of second LEDs over the non-porous regions according to a preferred embodiment of the present invention.

As in Figure 9, in this embodiment, the porous region is bigger and a different shape than the non-porous regions in the wafer, and the first LEDs overgrown over the porous regions are therefore also bigger and a different shape than the second LEDs overgrown over the non-porous regions. In a preferred embodiment, the first LEDs are red LEDs, either singlewavelength red LEDs, or variable-wavelength LEDs intended to emit red light in use in a display device.

In variable-wavelength LEDs as described above, red light is emitted in response to low driving currents, so the brightness of the emitted red light is lower than the brightness of a green LED of equivalent emitting area.

In the embodiment of Figure 11 , the arrays of first red LEDs and second green/blue LEDs are arranged as the subpixels of an array of display pixels, and the additional red LEDs formed over the additional porous regions act as “shared” red pixels, which may be operated in use to add red light to that emitted by the red subpixels on either side.

Alternative pixel arrangements and LED colours may also be used.

Figure 12A is a plan view optical microscopy image of a semiconductor wafer prior to porosification, while Figure 12B is a plan view image of the semiconductor wafer of Figure 12B after porosification. In this example, the wafer is not patterned with regions of different charge carrier concentrations, and no masking layer is used to mask regions of the surface layer during porosification. This means that Figure 12B shows uniform porosity in the wafer after porosification.

Figure 13 is a plan view optical microscopy image of a patterned semiconductor wafer in which a cross-shaped porous region has been formed in a specific wafer layer, surrounded by non-porous semiconductor material. This illustrates how porous regions of precise shapes and sizes can be produced by masking predetermined areas of the wafer surface before porosification takes place. The resolution and selectivity of the porosification process can be improved by doping the regions intended for porosification, for example using ion-implantation. Figure 14 illustrates the different emission wavelengths produced by the same epitaxial LED structure positioned over a porous region of semiconductor wafer, and by contrast over a non-porous region of semiconductor wafer. In this wafer, a region around the perimeter of the wafer has been masked during porosification so that the etching electrolyte cannot contact the wafer surface or the wafer edges in this region. The sub-surface n-type material in this masked region is thus not porosified.

Figure 14 shows photoluminescence (PL) wavelength mapping which compares the porous and non-porous regions on the same wafer after LED epitaxy of a single continuous LED epitaxial structure across the entire wafer. The PL wavelength mapping illustrates clearly that the peak emission wavelength (545.2 nm) of the LED structure in the non-porous region of the wafer is much shorter in wavelength compared to the peak emission wavelength (572.2 nm) of the same LED structure overgrown on the porous region, with very clear boundaries in the emission behaviour between porous/non-porous regions of the wafer. As described above, this can be transferred onto a mini-, micro- or nano- scale by selective doping and masking of different regions of the wafer, so that the wafer can be pre-patterned to turn a single LED epitaxy into arrays of semiconductor devices having different electronic and/or optoelectronic properties.

In some preferred embodiments of the present invention, the first and second semiconductor devices are LEDs. In particular, the first and/or second semiconductor devices may be variable-wavelength LEDs which can be tuned to emit peak emission wavelengths over a wavelength range of greater than 40 nm. For example, all of the LED devices on the wafer may be variable-wavelength LEDs formed over porous regions of the wafer, or the first semiconductor devices may be variable-wavelength LEDs formed over first porous regions, while the second semiconductor devices are “single-wavelength” (nonvariable-wavelength) LEDs which have the same structure as the first LEDs, but are not overgrown over a porous region.

Figure 15 is a series of five EL images of the same variable-wavelength MicroLED InGaN pixel being driven at different currents in constant wave mode (CW), showing five different colours of emission. In the left-hand image, the micro-LED emission colour is seen to be red at a driving current of 50 pA. In the second image from the left, the micro-LED emission colour is seen to be red-orange at a driving current of 100 pA. In the third image from the left, the micro-LED emission colour is seen to be orange at a driving current of 1 mA. In the fourth image from the left, the micro-LED emission colour is seen to be yellow-green at a driving current of 10 mA. In the right-hand image, the micro-LED emission colour is seen to be green at a driving current of 20 mA.

By varying the driving current between 50 pA to 20 mA, the same micro-LED is therefore capable of emitting at wavelengths ranging from red to green. The spectral width of this emission wavelength range is on the order of 90 nm (from around 570 nm to around 660 nm). This is a far greater range of emission wavelengths than has ever been achievable with a single LED in the prior art.

Figure 16A is an emission wavelength vs current density plot for a 25 pm x 25 pm InGaN LED pixel array (100 x 100 array, containing 10,000 pixels) driven in pulsed mode with a 100 ps pulse at 1% duty cycle. Figure 16B is an emission wavelength vs current density plot for a 30 pm x 30 pm InGaN LED pixel array (100 x 100 array, containing 10,000 pixels) driven in pulsed mode with a 100 ps pulse at 1% duty cycle.

Both of these plots show the controllability of the peak emission wavelength with a pulse driven power supply. In particular, the wavelength is linearly dependent on the current density (plotted on a logarithmic scale). This linearity can equally be manipulated when driving with a pulsed voltage power supply. The variable emission wavelengths of the LED can therefore be controlled with either voltage or current driving schemes in either CW or pulsed mode, all of which are standard ways of display driver IC.

This linear relationship between the driving current density and the resulting emission wavelength is highly advantageous for the purposes of LED display design, as it enables accurate control of the emission wavelengths by varying the current density of the power supply.

Figure 17 is a plot of intensity vs wavelength for a variable-wavelength InGaN LED driven at different DC currents. The power supply is operated in pulsed driving mode with a 100 ps pulse at 1% duty cycle.

Figure 17 again reflects a gradual, continuous transition of the peak emission wavelength of the LED as the current of the power supply is varied. At a driving current of 200 mA, the peak emission wavelength is around 575 nm, with an intensity of around 10 pW/nm. As the driving current is reduced, however, the peak emission wavelength moves gradually to longer wavelengths, and to lower emission intensities. When the driving current reaches 7 mA, the peak emission wavelength is approximately 675 nm, with an intensity of around 0.1 pW/nm.

Figures 18A-G illustrate alternative embodiments of light-emitting regions of variablewavelength LEDs which can be used as semiconductor devices in embodiments of the present invention.

Examples of MQWs:

1. Continuous MQWs

2. V-pits

3. Broken QWs, gappy QWs, fragmented QWs

4. QDs

5. Well-width fluctuation

6. Alloy composition

7. Different combinations of MQWs and underlayers

These structural characteristics can be identified and examined by standard material characterisation techniques, such as cross-sectional transmission electron microscopy (TEM), X-ray diffraction (XRD), Energy Dispersive X-ray Spectroscopy (EDX or EDS), 3D atom probe (3DAP).

Figure 18A shows a continuous MQW light-emitting region of an LED, in which three identical QWs are provided between four identical quantum barriers (QBs).

Figure 18B shows the continuous MQW of Figure 18A, with a V-shaped pit propagating through the light-emitting region. The v-shaped pit terminates in a threading dislocation, and has QWs on its semi-polar facets.

Figure 18C shows a MQW in which the QW layers comprise discontinuities or gaps in the semiconductor material.

Figure 18D shows a MQW in which quantum dots (QDs) create non-uniformities in the MQW. QDs may be provided on or in the QB or QW layers, for example in gaps in the QW structure. Figure 18E shows a MQW with well-width fluctuation, in which the thicknesses of the QW layers are not uniform across the light-emitting region. The QWs may have different widths from each other, and also varying widths within a single QW.

Figure 18F shows a MQW with fluctuations in alloy composition in the light-emitting region. The compositions of the QBs and the QWs differ from layer to layer. In particular, the indium ln% composition is varying within the same QWs, i.e. in QW2, ln% is varying between 10-12% or 10-15%, or 10-25%, or 10-35%.

Figure 18G shows a MQW containing different combinations of MQWs and underlayers. In% composition is different across different QWs. For example ln% in QW1 is 15%, ln% in QW2 is 25%, and ln% in QW3 is 30%. In embodiments of the present invention, the lower ln% QW is preferably positioned at the bottom of the MQW, due to its strain and thermal effect, while the high ln% QWs is preferred to be on the top. In a preferred embodiment, for example, QW1 is a blue emitting QW, QW2 is a green emitting QW, QW3 is a red emitting QW.

Figure 19A is a TEM image of a cross-section of a conventional non-variable-wavelength LED. In this non-variable-wavelength LED, the MQWs are uniform and smooth in both upper and lower interface (5 MQWs shown here).

Figures 19B and 19C are TEM images a variable-wavelength LED comprising v-shaped pits, usable in an embodiment of the present invention. In this variable-wavelength LED, the MQWs are non-uniform. This non-uniformity can be induced by various methods, one example is v-pits and the semi-polar facets which would incorporate more indium and thinner QWs. Another example is also shown in Figure 19B, that the MQWs are not uniform, in terms of broken QWs, discontinuous QWs, fragmented QWs, QWs with wellwidth or In composition fluctuation.

Figure 19C shows a cross section of the variable-wavelength LED of Figure 19B, showing a porous region and a light-emitting region comprising a plurality of v-shaped pits, usable in a preferred embodiment of the present invention.

In this structure, the light-emitting region contains multiple emission wavelength regions that are deliberately introduced such as multiple types of QW region with v-shaped pits extending through the light-emitting region. V-shaped pits (V-pits) are actually hexagonal pits looking from the above, v-shape is when looking at the cross-section. V-pits can be initialize at each site of dislocations under special epitaxy growth conditions during the growth of InGaN, GaN, InGaN/lnGaN superlattice, or InGaN/GaN superlattice structures underlying the MQWs, such as low growth temperature (e.g. <1000 ^e C, or <900 ^e C, or <800 ^e C, or <700 ^e C) and nitrogen ambient.

Figure 20A is a graph of peak emission wavelength vs driving current density for a conventional non-variable wavelength LED. By varying the driving current density applied to the LED, the emission wavelength can be slightly varied, across an emission wavelength range of around 15 nm.

Figure 20B is a graph of peak emission wavelength vs driving current density for a variablewavelength LED usable as a first or second semiconductor device in embodiments of the present invention. In the variable-wavelength LED, varying the current density of the driving power supply creates a much larger variation in the peak emission wavelengths (WLP) emitted by the LED. In this embodiment, varying the driving current density between roughly 0.1 and 100 A/cm ² varies the peak emission wavelength from around 635 nm to around 550 nm - an emission wavelength range of around 85 nm.

Figure 20C is a graph of peak emission wavelength vs driving current density for a variable-wavelength LED according to another embodiment of the present invention. In this embodiment, varying the driving current density varies the peak emission wavelength from around 720 nm to around 580 nm - an emission wavelength range of around 140 nm.

Figure 21 A is a graph of peak emission wavelength vs driving current density for another variable-wavelength LED according to the present invention. In this embodiment, varying the driving current density between roughly 0.1 and 200 A/cm ² varies the peak emission wavelength from 615 nm to 508 nm - an emission wavelength range of around 100 nm. The data for this graph only goes to 514.5nm due to a limitation on the testing capabilities. , The current density for 508nm is therefore estimated. However, the obtainable range of emission wavelengths can be pushed either way significantly.

Figures 21 B-D are photographs of the variable-wavelength LED of Figure 21 A, showing the same variable-wavelength LED emitting at four different wavelengths across its emission wavelength range. The inset emission spectra show the different peak emission wavelengths at different driving current densities. This shows the same variablewavelength LED emitting at peak emission wavelengths in the orange (615 nm), yellow (556 nm), green (534 nm) and blue (508 nm) in response to different driving current densities.