Title:
MOUNTING STRUCTURE AND MOUNTING METHOD FOR SEMICONDUCTOR CHIP
Document Type and Number:
WIPO Patent Application WO/2002/093638
Kind Code:
A1
Abstract:
A semiconductor chip having a large number of pins is connected reliably to terminals on a substrate. A mounting structure of a semiconductor chip includes bonds formed by ultrasonic welding and pressure welding, respectively. Thus, a semiconductor chip having a large number of pins can be connected reliably using the two types of welding, i.e., ultrasonic welding and pressure welding.
Inventors:
KIRA HIDEHIKO (JP)
KOBAE KENJI (JP)
KAINUMA NORIO (JP)
KOBAYASHI HIROSHI (JP)
KOBAE KENJI (JP)
KAINUMA NORIO (JP)
KOBAYASHI HIROSHI (JP)
Application Number:
PCT/JP2001/004089
Publication Date:
November 21, 2002
Filing Date:
May 16, 2001
Export Citation:
Assignee:
FUJITSU LTD (JP)
KIRA HIDEHIKO (JP)
KOBAE KENJI (JP)
KAINUMA NORIO (JP)
KOBAYASHI HIROSHI (JP)
KIRA HIDEHIKO (JP)
KOBAE KENJI (JP)
KAINUMA NORIO (JP)
KOBAYASHI HIROSHI (JP)
International Classes:
H01L21/60; (IPC1-7): H01L21/60; H01L21/607
Foreign References:
| JPH09232506A | 1997-09-05 | |||
| US6193136B1 | 2001-02-27 | |||
| JPH10303249A | 1998-11-13 | |||
| JPH0964101A | 1997-03-07 | |||
| JP2000353766A | 2000-12-19 |
Attorney, Agent or Firm:
Watanuki, Takao (12-9 Nakagosho 3-chom, Nagano-shi Nagano, JP)
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