[0001] This application claims the benefit of U.S. provisional patent application number 62/886,586, filed on August 14, 2019, the disclosure of which is incorporated herein by reference in its entirety.

Field of the Disclosure

[0002] The technology of the disclosure relates generally to an envelope tracking (ET) amplifier apparatus in a wireless communication device.

Background

[0003] Mobile communication devices have become increasingly common in current society. The prevalence of these mobile communication devices is driven in part by the many functions that are now enabled on such devices. Increased processing capabilities in such devices means that mobile communication devices have evolved from being pure communication tools into sophisticated mobile multimedia centers that enable enhanced user experiences.

[0004] The redefined user experience requires higher data rates offered by wireless communication technologies, such as long-term evolution (LTE) and fifth-generation new-radio (5G-NR). To achieve the higher data rates in mobile communication devices, sophisticated power amplifiers may be employed to increase output power of radio frequency (RF) signals (e.g., maintaining sufficient energy per bit) communicated by mobile communication devices. Flowever, the increased output power of RF signals can lead to increased power consumption and thermal dissipation in mobile communication devices, thus compromising overall performance and user experiences.

[0005] Envelope tracking (ET) is a power management technology designed to improve efficiency levels of power amplifiers to help reduce power consumption and thermal dissipation in a mobile communication device. In an ET system, an ET power amplifier(s) amplifies an RF signal(s) based on time- variant voltages generated in accordance to time-variant amplitudes of the RF signal(s). The time-variant voltages increase as the time-variant amplitudes rise and decrease as the time-variant amplitudes fall. As such, the time-variant voltages correspond to a time-variant voltage envelope that tracks a time-variant power envelope associated with the time-variant signal amplitudes of the RF signal(s). Notably, the better the time-variant voltage envelope tracks the time- variant power envelope, the higher efficiency can be achieved in the ET power amplifier(s). In this regard, it may be necessary for the ET system to constantly adjust the time-variant voltages applied to the ET power amplifier(s) to ensure that the ET power amplifier(s) can consistently operate at a desired efficiency for any given instantaneous power requirement of the RF signal(s).

[0006] Aspects disclosed in the detailed description include a multi-amplifier envelope tracking (ET) apparatus. The multi-amplifier ET apparatus includes an ET integrated circuit (ETIC). In a non-limiting example, the ETIC is configured to provide a first ET voltage and a second ET voltage to at least two power amplifier circuits for amplifying a radio frequency (RF) signal(s). The ETIC includes a first voltage circuit that generates the first ET voltage based on a first supply voltage and a first time-variant target voltage. The ETIC also includes a second voltage circuit that generates the second ET voltage based on a second supply voltage and a second time-variant target voltage. In embodiments disclosed herein, the ETIC is configured to determine the first supply voltage and the second supply voltage in accordance to the first time-variant target voltage and the second time- variant target voltage, respectively. As a result, both the first and the second voltage circuits can operate with optimal efficiency, thus helping to improve overall operating efficiency of the multi-amplifier ET apparatus.

[0007] In one aspect, a multi-amplifier ET apparatus is provided. The multi amplifier ET apparatus includes an ETIC. The ETIC includes a first voltage circuit configured to generate a first ET voltage based on a first supply voltage and a first time-variant target voltage. The ETIC also includes a second voltage circuit configured to generate a second ET voltage based on a second supply voltage and a second time-variant target voltage. The ETIC also includes a supply voltage circuit configured to generate a plurality of supply voltages. The ETIC also includes a control circuit coupled to the supply voltage circuit. The control circuit is configured to dynamically select the first supply voltage from the plurality of supply voltages based on the first time-variant target voltage. The control circuit is also configured to provide the selected first supply voltage to the first voltage circuit. The control circuit is also configured to dynamically select the second supply voltage from the plurality of supply voltages based on the second time-variant target voltage. The control circuit is also configured to provide the selected second supply voltage to the second voltage circuit.

[0008] Those skilled in the art will appreciate the scope of the disclosure and realize additional aspects thereof after reading the following detailed description in association with the accompanying drawings.

Brief Description of the Drawings [0009] The accompanying drawings incorporated in and forming a part of this specification illustrate several aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0010] Figure 1 is a schematic diagram of an exemplary existing ET apparatus that may suffer an efficiency degradation when a pair of power amplifier circuits are operating concurrently to amplify a pair of RF signals;

[0011] Figure 2 is a schematic diagram of an exemplary multi-amplifier ET apparatus configured according to one embodiment of the present disclosure to achieve improved operating efficiency over the existing ET apparatus of Figure 1 ; [0012] Figure 3 is a schematic diagram providing an exemplary configuration of a supply voltage circuit provided in the multi-amplifier ET apparatus of Figure 2;

[0013] Figure 4 is a schematic diagram of an exemplary multi-amplifier ET apparatus configured according to another embodiment of the present disclosure; and [0014] Figure 5 is a schematic diagram providing an exemplary configuration of a supply voltage circuit provided in the multi-amplifier ET apparatus of Figure 4.

[0015] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

[0016] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. [0017] It will be understood that when an element such as a layer, region, or substrate is referred to as being "on" or extending "onto" another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being "over" or extending "over" another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly over" or extending "directly over" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0018] Relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

[0019] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and/or "including" when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

[0020] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0021] Aspects disclosed in the detailed description include a multi-amplifier envelope tracking (ET) apparatus. The multi-amplifier ET apparatus includes an ET integrated circuit (ETIC). In a non-limiting example, the ETIC is configured to provide a first ET voltage and a second ET voltage to at least two power amplifier circuits for amplifying a radio frequency (RF) signal(s). The ETIC includes a first voltage circuit that generates the first ET voltage based on a first supply voltage and a first time-variant target voltage. The ETIC also includes a second voltage circuit that generates the second ET voltage based on a second supply voltage and a second time-variant target voltage. In embodiments disclosed herein, the ETIC is configured to determine the first supply voltage and the second supply voltage in accordance to the first time-variant target voltage and the second time- variant target voltage, respectively. As a result, both the first and the second voltage circuits can operate with optimal efficiency, thus helping to improve overall operating efficiency of the multi-amplifier ET apparatus.

[0022] Before discussing the multi-amplifier ET apparatus according to the present disclosure, starting at Figure 2, a brief discussion of an existing multi amplifier ET apparatus is first provided with reference to Figure 1.

[0023] Figure 1 is a schematic diagram of an exemplary existing ET apparatus 10 that may suffer an efficiency degradation when a first power amplifier circuit 12 and a second power amplifier circuit 14 are operating concurrently to amplify a first RF signal 16 and a second RF signal 18. In a non limiting example, the first power amplifier circuit 12 is configured to amplify the first RF signal 16 to a first power P _A based on a first ET voltage V _C CA and the second power amplifier circuit 14 is configured to amplify the second RF signal 18 to a second power level PB based on a second ET voltage VCCB- Understandably, the first RF signal 16 and the second RF signal 18 can each correspond to a respective time-variant power envelope bounded by a peak (highest power) and a bottom (lowest power). Flerein, the first power P _A and the second power PB refer to a root-mean-square (RMS) power of the first RF signal 16 and the second RF signal 18, respectively.

[0024] The existing ET apparatus 10 includes an ETIC 20 configured to generate the first ET voltage V _C CA and the second ET voltage V _C CB- More specifically, the ETIC 20 includes a first voltage amplifier 22A (denoted as “VPA- A”) and a second voltage amplifier 22B (denoted as “VPA-B”). The first voltage amplifier 22A is configured to generate the first ET voltage V _C CA based on a first supply voltage VSUPA and a first time-variant target voltage VJGTA· By generating the first ET voltage VCCA based on the first time-variant target voltage VJGTA, the first ET voltage V _C CA will correspond to a first time-variant voltage envelope that tracks (rises and falls) the first time-variant target voltage V _TG TA· The second voltage amplifier 22B is configured to generate the second ET voltage VCCB based on a second supply voltage VSUPB and a second time-variant target voltage V _TG TB· By generating the second ET voltage V _C CB based on the second time-variant target voltage V _TG TB, the second ET voltage V _C CB will correspond to a second time-variant voltage envelope that tracks (rises and falls) the second time-variant target voltage VJGTB-

[0025] For the first power amplifier circuit 12 to operate at optimal efficiency and linearity, the first ET voltage V _C CA needs to track closely the time-variant power envelope of the first RF signal 16. In this regard, the first ET voltage VCCA varies between a first maximum ET voltage VCCA-MAX, which corresponds to the highest power (peak) of the first RF signal 16, and a first minimum ET voltage VCCA-MIN that corresponds to the lowest power (bottom) of the first RF signal 16. Likewise, for the second power amplifier circuit 14 to operate at optimal efficiency and linearity, the second ET voltage VCCB also needs to track closely the time- variant power envelope of the second RF signal 18. Similarly, the second ET voltage V _C CB varies between a second maximum ET voltage V _C CB-MAX, which corresponds to the highest power (peak) of the second RF signal 18, and a second minimum ET voltage VCCB-MIN that corresponds to the lowest power (bottom) of the second RF signal 18.

[0026] The ETIC 20 includes a supply voltage circuit 24 configured to generate a supply voltage VSUP based on a battery voltage VBAT- The supply voltage circuit 24 provides the supply voltage VSUP to the first voltage amplifier 22A as the first supply voltage V _S UPA and to the second voltage amplifier 22B as the second supply voltage V _S UPB- The first supply voltage V _S UPA and the second supply voltage VSUPB may be used to drive respective output states (not shown) of the first voltage amplifier 22A and the second voltage amplifier 22B. In this regard, for the first voltage amplifier 22A to operate with optimal efficiency, the first supply voltage VSUPA should equal the first maximum ET voltage VCCA-MAX plus a headroom (VSUPA = VCCA-MAX + Headroom). Likewise, for the second voltage amplifier 22B to operate with optimal efficiency, the second supply voltage V _S UPB should equal the second maximum ET voltage V _C CB-MAX plus a headroom (V _S UPB = V _C CB-MAX + Headroom).

[0027] In some cases, the first RF signal 16 and the second RF signal 18 may correspond to different time-variant power envelopes. For example, the first maximum ET voltage VCCA-MAX is consistently higher than the second maximum ET voltage V _C CB-MAX (VCCA-MAX > VCCB-MAX)· However, since the supply voltage circuit 24 can only provide the supply voltage VSUP as both the first supply voltage V _S UPA and the second supply voltage V _S UPB, the supply voltage circuit 24 needs to generate the supply voltage V _S UP based on the higher maximum ET voltage (e.g., VCCA-MAX) among the first maximum ET voltage VCCA-MAX and the second maximum ET voltage VCCB-MAX to avoid amplitude clipping. As a result, the second voltage amplifier 22B will receive a higher than optimal supply voltage, which can cause the second voltage amplifier 22B to suffer an efficiency degradation. Although it may be possible to employ two separate supply voltage circuits in the ETIC 20 for generating the first supply voltage VSUPA and the second supply voltage V _S UPB, doing so would inevitably lead to an increased footprint, cost, and power consumption of the ETIC 20. Thus, it may be desirable to improve operating efficiency of the ETIC 20 without increasing footprint, cost, and power consumption.

[0028] In this regard, Figure 2 is a schematic diagram of an exemplary multi amplifier ET apparatus 26 configured according to one embodiment of the present disclosure to achieve improved operating efficiency over the existing ET apparatus 10 of Figure 1. The multi-amplifier ET apparatus 26 includes an ETIC 28. The ETIC 28 includes a first voltage circuit 30A, a second voltage circuit 30B, a supply voltage circuit 32, and a control circuit 34, which can be any type of microcontroller or a field-programmable gate array (FPGA), as an example. It should be appreciated that the ETIC 28 can support additional voltage circuits based on the operational principles discussed hereinafter. [0029] The first voltage circuit 30A is configured to generate a first ET voltage VCCA based on a first supply voltage VSUPA and a first time-variant target voltage VJGTA- In a non-limiting example, the first voltage circuit 30A can receive the first time-variant target voltage V _TG TA from a transceiver circuit (not shown). By generating the first ET voltage VCCA based on the first time-variant target voltage VJGTA, the first ET voltage VCCA will correspond to a first time-variant voltage envelope that tracks (rises and falls) the first time-variant target voltage VJGTA- Similar to the first ET voltage V _C CA in Figure 1 , the first ET voltage V _C CA in Figure 2 is also bounded by a first maximum ET voltage VCCA-MAX and a first minimum ET voltage VCCA-MIN-

[0030] The second voltage circuit 30B is configured to generate a second ET voltage V _C CB based on a second supply voltage V _S UPB and a second time-variant target voltage VJGTB- In a non-limiting example, the first voltage circuit 30A can receive the first time-variant target voltage VJGTA from the same transceiver circuit (not shown). By generating the second ET voltage V _C CB based on the second time-variant target voltage VJGTB, the second ET voltage V _C CB will correspond to a second time-variant voltage envelope that tracks (rises and falls) the second time-variant target voltage VJGTB- Similar to the second ET voltage VCCB in Figure 1 , the second ET voltage V _C CB in Figure 2 is also bounded by a second maximum ET voltage V _C CB-MAX and a second minimum ET voltage V _C CB-

MIN-

[0031] Notably, the first time-variant target voltage VJGTA can be identical to or different from the second time-variant target voltage VJGTB- Accordingly, the first time-variant voltage envelope of the first ET voltage V _C CA can be identical to or different from the second time-variant voltage envelope of the second ET voltage VCCB- AS a result, the first maximum ET voltage VCCA-MAX can be identical to or different from the second maximum ET voltage V _C CB-MAX- In examples discussed hereinafter, it is assumed that the first time-variant voltage envelope of the first ET voltage VCCA is different from the second time-variant voltage envelope of the second ET voltage VCCB and the first maximum ET voltage VCCA-MAX is higher than the second maximum ET voltage V _C CB-MAX- [0032] The supply voltage circuit 32 is configured to generate a low constant voltage VSUPL and a high constant voltage VSUPH greater than the low constant voltage V _S UPL (VSUPH = X*VSUPL, x > 1). The control circuit 34 is configured to selectively provide any of the low constant voltage V _S UPL and the high constant voltage VSUPH to any of the first voltage circuit 30A and the second voltage circuit 30B based on the first time-variant target voltage V GTA and the second time- variant target voltage V _TG TB· In a non-limiting example, the control circuit 34 provides the low constant voltage V _S UPL to the first voltage circuit 30A as the first supply voltage VSUPA if the first time-variant target voltage VJGTA is below (<) a first threshold voltage and provides the high constant voltage VSUPH to the first voltage circuit 30A as the first supply voltage V _S UPA if the first time-variant target voltage V _TG TA is above (>) the first threshold voltage. As such, the first supply voltage VSUPA toggles dynamically between the low constant voltage VSUPL and the high constant voltage VSUPH in response to rises and falls of the first time- variant target voltage V _TG TA· Notably, the control circuit 34 may also provide the low constant voltage V _S UPL or the high constant voltage V _S UPH to the first voltage circuit 30A as the first supply voltage VSUPA regardless of the first time-variant target voltage VJGTA-

[0033] Likewise, the control circuit 34 provides the low constant voltage V _S UPL to the second voltage circuit 30B as the second supply voltage V _S UPB if the second time-variant target voltage VTGTB is below (<) a second threshold voltage, which can be identical to or different from the first threshold voltage, and provides the high constant voltage V _S UPH to the second voltage circuit 30B as the second supply voltage V _S UPB if the second time-variant target voltage V _TG TB is above (>) the second threshold voltage. As such, the second supply voltage VSUPB toggles dynamically between the low constant voltage VSUPL and the high constant voltage V _S UPH in response to rises and falls of the second time-variant target voltage V _TG TB· Notably, the control circuit 34 may also provide the low constant voltage VSUPL or the high constant voltage VSUPH to the second voltage circuit 30B as the second supply voltage VSUPB regardless of the second time-variant target voltage V _TG TB· [0034] By dynamically adjusting the first supply voltage VSUPA and the second supply voltage VSUPB based on the first time-variant target voltage V GTA and the second time-variant target voltage V _TG TB, it is possible to improve operating efficiencies of the first voltage circuit 30A and the second voltage circuit 30B. As a result, it is possible to improve overall operating efficiency of the multi-amplifier ET apparatus 26.

[0035] In a non-limiting example, the first voltage circuit 30A includes a first voltage amplifier 36A (denoted as “VPA-A”), a first offset capacitor 38A, and a first feedback loop 40A. The first voltage amplifier 36A is configured to generate a first initial ET voltage VAMPA based on the first supply voltage VSUPA and the first time-variant target voltage V _TG TA· In a non-limiting example, the first supply voltage V _S UPA is applied to an output stage (not shown) of the first voltage amplifier 36A. The first offset capacitor 38A is configured to raise the first initial ET voltage VAMPA by a first offset voltage VOFFA (e.g., 0.8 V) to generate the first ET voltage V _G CA (VCCA = VAMPA + V ₀ FFA)· The first feedback loop 40A is configured to provide a feedback of the first ET voltage V _C CA to the first voltage amplifier 36A, thus making the first voltage circuit 30A a closed-loop ET voltage circuit.

[0036] Similarly, the second voltage circuit 30B includes a second voltage amplifier 36B (denoted as “VPA-B”), a second offset capacitor 38B, and a second feedback loop 40B. The second voltage amplifier 36B is configured to generate a second initial ET voltage VAMPB based on the second supply voltage VSUPB and the second time-variant target voltage V _TGT B. In a non-limiting example, the second supply voltage V _S UPB is applied to an output stage (not shown) of the second voltage amplifier 36B. The second offset capacitor 38B is configured to raise the second initial ET voltage VAMPB by a second offset voltage VOFFB (e.g., 0.8 V) to generate the second ET voltage V _C CB (VCCB = VAMPB + V ₀ FFB)· The second feedback loop 40B is configured to provide feedback of the second ET voltage VCCB to the second voltage amplifier 36AB, thus making the second voltage circuit 30B a closed-loop ET voltage circuit. [0037] The multi-amplifier ET apparatus 26 includes a first power amplifier circuit 42 and a second power amplifier circuit 44. The first power amplifier circuit 42 is configured to amplify a first RF signal 46 based on the first ET voltage V _C CA- The second power amplifier circuit 44 is configured to amplify a second RF signal 48 based on the second ET voltage VCCB- The first power amplifier circuit 42 and the second power amplifier circuit 44 can amplify the first RF signal 46 and the second RF signal 48 either concurrently or independently. The first RF signal 46 may be the same as or different from the second RF signal 48. In a non-limiting example, the first RF signal 46 and the second RF signal 48 are provided by the same transceiver circuit (not shown) that generates the first time-variant target voltage V _TG TA and the second time-variant target voltage V GTB- Notably, the multi-amplifier ET apparatus 26 can include additional power amplifier circuits for amplifying additional RF signals. Accordingly, the ETIC 28 may include additional voltage circuits to support the additional power amplifier circuit.

[0038] The ETIC 28 can include a multi-level charge pump (MCP) 50 and a power inductor 52. The MCP 50 is configured to generate a low-frequency voltage VDC that is proportional to a battery voltage VBAT (e.g., VDC = 0*VBAT, 1 *VBAT, or 2*VBAT)· The power inductor 52 is configured to induce a low- frequency current e based on the low-frequency voltage V _D c- The first power amplifier circuit 42 and the second power amplifier circuit 44 may be coupled to the power inductor 52 to receive the low-frequency current be- In this regard, the low-frequency current be can be adjusted by adjusting the low-frequency voltage VDC- In a non-limiting example, the control circuit 34 can cause the MCP 50 to adjust the low-frequency voltage VDC and, thus, the low-frequency current be based on rises and falls of the first ET voltage VCCA and/or the second ET voltage VCCB-

[0039] Figure 3 is a schematic diagram providing an exemplary configuration of the supply voltage circuit 32 in the multi-amplifier ET apparatus 26 of Figure 2. Common elements between Figures 2 and 3 are shown therein with common element numbers and will not be re-described herein. [0040] In a non-limiting example, the supply voltage circuit 32 includes a supply MCP 54, a supply power inductor 56, a lower voltage path 58, and a higher voltage path 60. The supply MCP 54 is configured to generate a low- frequency supply voltage V _D c-s that is proportional to the battery voltage V _B AT (e.g., VDC-S = 0*VBAT, 1 *VBAT, or 2*VBAT)· The supply power inductor 56 is configured to induce a low-frequency current bc-s based on the low-frequency supply voltage V _D c-s- The lower voltage path 58 is coupled to the supply power inductor 56 and configured to output the low-frequency supply voltage V _D c-s as the low constant voltage VSUPL- The higher voltage path 60 is coupled to the supply power inductor 56 and configured to boost the low-frequency supply voltage V _D c-s to generate the high constant voltage V _S UPH- [0041] In a non-limiting example, the higher voltage path 60 includes a first switch SW1 , a second switch SW2, a third switch SW3, and a fourth switch SW4. The first switch SW1 and the second switch SW2 are coupled in series. The third switch SW3 and the fourth switch SW4 are coupled in series and in parallel to the first switch SW1 and the second switch SW2. The higher voltage path 60 includes a fly capacitor 62 having one end coupled in between the first switch SW1 and the second switch SW2, and another end coupled in between the third switch SW3 and the fourth switch SW4.

[0042] In a non-limiting example, the supply voltage circuit 32 can be configured to generate the low constant voltage VSUPL that equals the low- frequency supply voltage VDC-S (VSUPL = VDC-S) and the high constant voltage VSUPH proportional to the low-frequency supply voltage V _D c-s (VSUPH = y ^* Voc-s, y > 1 ). To output the low constant voltage V _S UPL at the low-frequency supply voltage VDC-S, the switches SW1 , SW2, SW3, and SW4 are kept open.

[0043] To output the high constant voltage VSUPH at, for example, two times the low-frequency supply voltage V _D c-s (VSUPH = 2 ^* V _D c-s), the fly capacitor 62 is first charged by closing the first switch SW1 and the fourth switch SW4 and opening the second switch SW2 and the third switch SW3. Subsequently, the fly capacitor 62 can be discharged by opening the first switch SW1 and the fourth switch SW4 and closing the second switch SW2 and the third switch SW3. Accordingly, the higher voltage path 60 can output the high constant voltage VSUPH at 2XVDC-S- It should be appreciated that the supply voltage circuit 32 can be configured to include additional voltage paths to provide additional constant voltages.

[0044] Alternative to making the supply voltage circuit 32 generate the low- constant voltage VSUPL and the high constant voltage VSUPL, it is also possible to reconfigure the supply voltage circuit 32 to provide modulated supply voltages to the first voltage amplifier 36A and the second voltage amplifier 36B. In this regard, Figure 4 is a schematic diagram of an exemplary multi-amplifier ET apparatus 64 configured according to another embodiment of the present disclosure. Common elements between Figures 2 and 4 are shown therein with common element numbers and will not be re-described herein.

[0045] The multi-amplifier ET apparatus 64 includes an ETIC 66, which further includes a supply voltage circuit 68 and a control circuit 70. The supply voltage circuit 68 receives the first time-variant target voltage V _TG TA and the second time- variant target voltage V _TG TB (e.g., from the same transceiver circuit as in Figure 2). Accordingly, the supply voltage circuit 68 can generate a first modulated voltage VSUP-MODA that is modulated based on the first time-variant target voltage V QTA and a second modulated voltage V _S UP-MODB that is modulated based on the second time-variant target voltage V _TGT B. The control circuit 70 is configured to provide the first modulated voltage VSUP-MODA to the first voltage amplifier 36A as the first supply voltage VSUPA and provide the second modulated voltage VSUP- MODB to the second voltage amplifier 36B as the second supply voltage V _S UPB- [0046] Figure 5 is a schematic diagram providing an exemplary configuration of the supply voltage circuit 68 in the multi-amplifier ET apparatus 64 of Figure 4. Common elements between Figures 4 and 5 are shown therein with common element numbers and will not be re-described herein.

[0047] In a non-limiting example, the supply voltage circuit 68 includes a first amplifier 72A (denoted as “VPA-S1 ”), a first capacitor 74A, a first feedback path 76A, a second amplifier 72B (denoted as “VPA-S2”), a second capacitor 74B, and a second feedback path 76B. The first amplifier 72A is configured to generate a first initial modulated voltage VAMP-MODI based on a first voltage VSUPI and the first time-variant target voltage V GTA- The first capacitor 74A is configured to raise the first initial modulated voltage V _A MP-MODI by an offset voltage V ₀ FF-MODI to generate the first modulated voltage V _S UP-MODA (V _S UM-MODA = VAMP-MODI + VOFF-MOD-I)· The first feedback path 76A provides a copy of the first modulated voltage VSUP-MODA to the first amplifier 72A.

[0048] Similarly, the second amplifier 72B is configured to generate a second initial modulated voltage V _A MP-MOD2 based on a second voltage V _S UP2 and the second time-variant target voltage VJGTB- The second capacitor 74B is configured to raise the second initial modulated voltage V _A MP-MOD2 by an offset voltage V ₀ FF-MOD2 to generate the second modulated voltage V _S UP-MODB (VSUM- MODB = V _A MP-MOD2 + V0FF-MOD2)· The second feedback path 76B provides a copy of the second modulated voltage VSUP-MODB to the second amplifier 72B.

[0049] The supply voltage circuit 68 may include a supply MCP 78 (denoted as “MCP-S”), a supply power inductor 80, a first low-dropout (LDO) circuit 82A, a second LDO circuit 82B, and a controller 84. The supply MCP 78 is configured to generate a low-frequency supply voltage VDC-S that is proportional to the battery voltage VBAT. The supply power inductor 80 is configured to induce a low- frequency supply current IDC-S based on the low-frequency supply voltage V _D c-s- The first LDO circuit 82A is coupled to the supply power inductor 80 and configured to generate the first voltage VSUPI based on the low-frequency supply voltage VDC-S- The second LDO circuit 82B is coupled to the supply power inductor 80 and configured to generate the second voltage V _S UP2 based on the low-frequency supply voltage V _D c-s- The controller 84 is configured to provide a reference voltage VREF to the first LDO circuit 82A and the second LDO circuit 82B for generating the first voltage VSUPI and the second voltage VSUP2- [0050] In one embodiment, the controller 84 receives a first low target voltage VTGTA-L that corresponds to a minimum of the first time-variant target voltage VTGTA and a second low target voltage V GTB-L that corresponds to a minimum of the second time-variant target voltage VJGTB- Accordingly, the controller 84 generates the reference voltage V _RE F as a higher one of the first low target voltage V GTA-L and the second low target voltage V GTB-L (VREF = MAX [VJGTA-L, VTGTB-L])· Accordingly, the supply voltage circuit 68 can modulate each of the first modulated voltage V _S UP-MODA and the second modulated voltage V _S UP-MODB to toggle between the low constant voltage V _S UPL and the high constant voltage VSUPH- Notably, the controller 84 may generate the reference voltage VREF as a constant voltage or as a modulated voltage.

[0051] Those skilled in the art will recognize improvements and modifications to the embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.