Background of the Invention

This invention relates to a data signal processing method and apparatus and, more particularly, to such method and apparatus which are useful for functions such as signal bit code conversion and pre-equalization.

It is well known in the art to convert between digital signal codes employing different combinations of binary ONE and ZERO signal bits to represent the same information. One example, employing a magnetic core matrix, is the U.S.A. patent 3,011,165 to A. M. Angel et al. However, in these systems, individual bit signals are usually represented in the same way in both codes; that is, a binary ONE bit is represented in the same way in both codes, and a binary ZERO is represented in the same way in both codes.

Binary signal bits can be represented in different ways in both baseband and modulated formats. For example, in baseband, they may be represented in a pulse/no-pulse format, or a bipolar nonreturn-to-zero (NRZ) format, or a biphase Manchester format, or .other formats. Similarly, data bit signals in modulated arrangements may be represented in frequency or phase-shift keyed arrangements, amplitude modulation, or frequency modulation. Regardless of the bit representation format, it is sometimes useful to change the individual bit representation format, sometimes also called bit representation code or modulation. In the U.S.A. patent 4,100,541 to H. A. Quesnell, Jr., binary signal bits in an NRZ-type of format are converted to the Manchester format by a multiplexing technique. A D. Ξ. Curtis patent 3,774,178 employs a two-bit shift register and associated logic clocked at the bit rate to convert NRZ code to a Pouliart code with state transitions in mid-bit of ONES, and between adjacent ZEROs. "Digital Generation

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of Data Modulated Waveforms," by S. M. Bozic et al. in Microelectron. Reliab. , Vol. 22, No. 4, pp. 759-767, 1982, shows the clocking of each input data bit at a higher rate than the data to select one or the other of two forms of the same input bit state for application to a digital transversal filter which produces a modulator output.

In preparing a converted bit code for, e.g., radio transmission, certain undesired effects sometimes occur. Thus, in the Manchester bit encoder of FIG. 10 in "Advanced Mobile Phone Service - A Subscriber Set for the Equipment Test," by R. E. Fisher, Bell System Technical Journal, January 1979, pages 123-143, a Bessel low-pass filter is employed, following an exclusive ORing operation and integration. The filter maintains the phase relationships among the different components of the data signal and band-limits the signal to reduce the amplitude of frequency components thereof outside of the allotted radio frequency channel. However, such a filter has an output amplitude that is data-pattern sensitive. Such pattern sensitivity in output amplitude has been found to impact adversely the system error rate, and it also makes that error rate pattern-sensitive. Summary of the Invention

The present invention collects information on multiple data signal input bit states which determine the essential characteristics of the output signal wave configuration. Those states are utilized in conjunction with local clock signals at a rate substantially in excess of a rate twice the largest frequency component of the input data signal to control a combinatorial logic function for constructing the desired output signal wave.

Brief Description of the Drawing

A more complete understanding of the invention and the various features, objects, and advantages thereof, may be obtained from a consideration of the following

Detailed Description in connection with the appended claims and the attached drawings in which

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FIG. 1 is a schematic diagram of a signal processing circuit of the invention as applied to a data signal bit form converting arrangement;

FIG. 2 is a diagram of processing circuit output signal spectrum magnitudes illustrating certain improvements achieved by the invention as compared to the aforementioned Bessel-filtered technique; and

FIGS. 3-6 are diagrams of signal waveforms employed for performing signal processing in FIG. 1. Detailed Description

In FIG, 1 , the signal processing circuit is arranged for converting an NRZ input data signal, which is unbalanced with respect to ground, into a Manchester output data signal, which is balanced with respect to ground. In the Manchester or split-phase coding system binary states are coded by transitions, rather than by amplitude or polarity. Conventionally, the 1 bit is represented by a negative-going transition and the 0 bit, by a positive- going transition. The dc component is thereby eliminated. The latter signal is conveniently adapted for application, for example, to modulate a radio transmitter (not shown) output signal. The intermediate signal processing, accomplished between the input and the output in FIG. 1, is illustratively a bit code conversion which is accomplished by a combinatorial table look-up function using,input data signal states and locally generated clock signals jointly to address a read-only memory 10 that is operated as a waveform generator. The local clock signals are produced by counting down the output of an oscillator 11. The oscillator output is applied through a buffer 12 to a counting chain 13 which is comprised of three four-bit binary counters 16, 17, and 18. Output of oscillator 11 is advantageously at a frequency which is much higher than twice the bit rate of the NRZ input data and, advantageously, an integer power of two times the data frequency; and, in an illustrative embodiment, the oscillator output was at 10.24 MHz for a signal processing

circuit receiving NRZ input data at 10 kilobits per second.

The buffered oscillator output is applied in parallel to clocking inputs of the three four-bit, i.e., divide by 16, counter sections of the counting chain 13. Those are positive-edge-trigger inputs, as schematically indicated in the drawing. Both control inputs of the first stage 16 are permanently enabled by application of a positive bias from a positive potential source 19, the output of which is applied through a resistor 20. The overflow output RC of stage 16 is applied to both enabling inputs of the stage 17 so that the latter stage can be clocked only at the time of overflow of the first stage 16. Similarly, overflow outputs of the stages 16 and 17 are applied to the respective enabling inputs of the third counting section 18 so that the latter section is able to count only in response to overflow at the same time of both of the first two sections 16 and 17.

All three counting stages have their clear inputs permanently disabled by application of a positive bias from a supply 21 schematically represented by a circled plus sign. That schematic representation indicates the connection to the plus terminal of a voltage supply which has its terminal of opposite polarity connected to ground. Other voltage supplies are similarly indicated in the drawing in terms of a circled polarity sign. Similarly, the parallel loading enable inputs are also permanently disabled by application of a positive bias from a supply 22 - through inverting input connections to the respective counting sections 16-18. Outputs from all stages of the counting chain 13, except the two least significant stages of the first counting section 16 and the two most significant stages of the counting section 18, are connected to provide bit parallel, binary-coded signals identifying respective time phases. Those count phase signals will be applied during input signal bit times for the NRZ input data signal for use in a manner which will be described.

A two-bit shift register, including D-type flip- flop circuits 23 and 26, is provided to collect information about input NRZ data signal states. That register is clocked by a bit rate clock signal, e.g., at 10 kHz, from the second stage of the third counter section 18. The NRZ input signal is applied to the D input of the first flip- flop 23, and a Q output of that flip-flop is coupled directly to the D input of the second flip-flop 26. That same Q output is further coupled, along with the Q output of the flip-flop 26, as a two-bit portion of the address information applied to the read only memory 10. Those two address bits are the bits a7 and a8 in the total array of 11 address bits aO through alO.

In a bit code conversion from NRZ to Manchester, the shape of each Manchester bit waveform is largely determined in part by the current bit state of the input NRZ data bit, and in part by the previous bit state of the same NRZ input signal. There are, thus, four possible different bit state combinations of two bits each, which determine the essential configuration of the Manchester output. Thus, the bit parallel output of the two-bit shift register, including flip-flop 23 and 26 outputs in each bit time, provides both the current and the previous bit states of the input signal to address the ROM 10. More generally stated, if ri input bit states are to be used to define each output signal bit configuration, then 2 ⁿ bit state combinations are possible. Consequently, the ROM 10 stores 2 ⁿ different output bit waveforms representing those combinations. Each stored waveform is represented in storage by

128 different binary-coded time phase sample values in the illustrative embodiment under consideration. Those values are selectable by the seven most significant bits (up to and including the 10-kHz bit) of the counter chain outputs previously noted and applied to the seven least significant bit address inputs aθ through a6 of the ROM 10. Two additional address inputs a9 and alO on ROM 10 are the two

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most significant ones of the 11 address inputs. Those two schematically represent the capability for storing and accessing additional sets of waveforms (a total of four sets in the illustration) representing different signal processing functions such as, e.g., data signal translations in different amplitude ranges for testing or for working into transmission facilities having widely different characteristics. The additional inputs are advantageously selectable by signals from either a manual controller or an automatic controller (not shown) for a system including the illustrated processing circuits.

Each stored sample value in ROM 10 is an 8-bit binary-coded character, the value of which is determined in a manner which will be subsequently described. Those binary-coded sample value characters appear on output leads designated Q0 through Q7 from the ROM 10, and are coupled to corresponding input connections of a data latch register 27 which comprises an array of eight D-type flip- flop circuits. It will be appreciated from the foregoing that the effective sample rate of the waveforms output from ROM 10 is much higher than twice the NRZ input data bit rate; and, in the illustrative embodiment, that ROM output sample rate is at 1.280 MHz. This high sample rate assures spectrum control at and above the data rate, e.g., ideally to 640 kHz from the carrier but, when quantization noise is included, illustrativel , out to about 80 kHz from the carrier. The output of the third stage of the first counting chain section 16 is utilized to provide clock enabling for the input connections of latch register 27. That clocking of the latch is then at a frequency of 1.28 MHz in the illustrative embodiment.

Latch register 27 outputs are continuously enabled by virtue of the fact that the clearing input to the register is disabled by the positive bias supplied from a source 28 through a biasing resistor 29. Those latch outputs are applied to inputs of a digital-to-analog converter 30 by direct connection. Converter 30 is

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supplied with operating potential from a negative voltage supply 32 and a corresponding ground connection. In addition, the converter is supplied with reference current for the conversion function from a positive voltage supply 33 which is coupled through a resistor 35 to the converter and has a return path coupled to ground through a resistor 36. Since the output of ROM 11 changes once in each half-cycle of the maximum frequency of its clock address, the clocking of latch 27 at twice the maximum frequency of the ROM 10 address input loads the latch only after the ROM output has settled and thereby stabilizes inputs to converter 30.

Output from converter 30 appears as a current output on a lead 37 which is coupled to an inverting input connection of an operational amplifier 38. That amplifier is connected to perform a σurrent-to-voltage conversion as one of its functions. To this end, its noninverting input connection is coupled to ground; and its inverting input connection is coupled through a resis ^' tor 39 from the positive supply 33. In addition, a parallel resistor- capacitor combination, including a resistor 40 and a capacitor 41, is connected to provide feedback from the amplifier output to its inverting input connection for accomplishing a single-pole of low-pass filtering for smoothing out quantizing noise at the 1.28-MHz sampling rate. A cut-off frequency substantially above twice the data rate, e.g., about 80 kHz has been found satisfactory. This filtering produces no significant phase shift in the 10-kHz NRZ signaling band. Output from amplifier 38 is coupled by an adjustable potential divider 42 to a noninverting input connection of an operational amplifier 43. That amplifier is connected as a unity gain amplifier for providing a low impedance output through a coupling resistor 46 to an inverting input connection of a further operational amplifier 47.

Amplifier 47 is provided with a negative feedback connection through a resistor 48 to set the level of gain

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for the amplifier stage, and it is further provided with a negative feedback connection through an inverting output and a resistor 49 to the noninverting input connection of the amplifier. The latter input is further connected to ground through a resistor 50. This arrangement provides the amplifier with a balanced output type of operation so that it supplies to the overall output of the code converter a balanced output signal coupled through resistors 51 and 52. FIG. 2 depicts certain aspects of improvement realized in the circuit of FIG- 1 using a ROM translation as compared to a Bessel-filtered type of circuit previously mentioned herein. The figure is a plot of frequency spectra magnitudes versus frequency measured from a carrier frequency. In the figure, there are two references. One is a dotted curve, labeled "IF Response," which is a continuous spectrum in watts-per-Hz, representing the response of a typical intermediate frequency stage of a radio receiver (not shown) that may receive signals having the FIG. 1 Manchester output modulated thereon. The second reference is comprised of two solid lines at ninety degrees with respect to each other and labeled "Interf rence limit specification." The latter reference is a typical radio channel interference limit specification. Data points above and to the right of those perpendicular lines represent unacceptable interference, whereas data points to the left and below those lines represent interference which is tolerable.

In FIG. 2, the dashed line represents a Bessel- filtered signal continuous spectrum including substantial energy above about 35 kHz. The solid line curve ^" represents the ROM translation continuous spectrum of the FIG. 1 embodiment; and, although it still includes some energy to the right of the IF Response reference, it includes much less energy in that region, and somewhat more energy below the 10-kHz data rate to the left of that reference, as compared to the dashed curve. Consequently, the ROM

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translation version of the present invention produces an output which is significantly better matched in a frequency sense to the bandpass characteristics of circuits which will receive the data signal. That improved match tends to reduce the error rate.

In an interference sense, the data points represented by asterisks in FIG. 2 represent Bessel- filtered signal components, including the unmodulated carrier signal, near the top of the ordinate line, and the 10-kHz data signal component at the upper left-hand portion of the figure. All of the other asterisk data points represent harmonics of the 10-kHz signal; and it is seen that a substantial number of those harmonics, e.g., particularly those at the fifth and sixth harmonic frequencies, are close enough to the interference limit specification that component tolerances, small modulation nonlinearities , and similar effects can cause the limit to be exceeded. By contrast, however, the circled "X" marks, which represent the corresponding data points for the illustrative ROM translation of FIG. 1, are significantly below the interference limit specification.

FIGS. 3-6 illustrate four waveforms for the data stored in the ROM 10 to represent the 2 ⁿ 2-bit data sequences for the previous-bit/current-bit combinations 00, 01, 10, and 11, respectively. In each case, ordinates are in arbitrary amplitude units, which are proportional to current, of ROM 10 output. Time is represented on the abscissa and is indicated relative to the beginning of a bit cell. The beginning of such a bit cell is at the central, or zero, time location on that axis. Thus, in each figure, the waveform includes the waveform of the last half of the previous bit cell of the combination, followed by the waveform of the first half of the current bit cell. Accordingly, each waveform presents the data signal transition wave between bit cells in a Manchester-encoded signal, i.e., the transition between the significant information representative signal transitions for the

respective binary ONE or ZERO bit values indicated.

The illustrative signal waves of FIGS. 3-6 are advantageously derived to produce three effects. A first effect is the reproduction of the data information. For bit code conversion alone, output waves could be arbitrarily selected to reproduce the data information in the new bit code. However, in the course of that conversion, the invention advantageously lends itself to realizing one or more of at least two additional signal wave modifications. Thus, the second effect advantageously produced is an amplitude-limiting effect on the waveforms for the ZERO-to-ONE transition and the ONE-to-ZERO transition of FIGS. 4 and 5, respectively. Those two are amplitude-limited, illustratively at about H^llO amplitude units, because the transitions for ZERO-to-ZERO and ONE- to-ONE, which extend to about + _^ 125 units in FIGS. 3 and 6, respectively, normally experience greater attenuation in radio receiving station filters. Hence, by imposing amplitude-limiting on the first two types of transition in the encoding operation at the transmitting station, the opportunities for having substantially equal data bit amplitude results for any of the transitions at the receiving station is greatly enhanced and, thereby, greatly reduces the likelihood of having data amplitudes at the receiving station which are data-pattern sensitive.

The third effect advantageously implemented in the ROM translation of the circuit in FIG. l ^' is a band- limiting function, which accomplishes the aforementioned effect of confining a greater proportion of the data signal energy within the radio equipment passband than was heretofore the case. That translation also further reduces the magnitude of interference at harmonics of the data rate.

Although the present invention has been described in connection with a particular embodiment thereof, it is to be understood that additional applications, embodiments, and modifications, which will be apparent to those skilled

in the art, are included within the spirit and scope of the invention.

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