Title:
MULTI-LAYER HIGH BANDWIDTH MEMORY AND MANUFACTURING METHOD THEREFOR
Document Type and Number:
WIPO Patent Application WO/2024/051124
Kind Code:
A1
Abstract:
Provided in the present invention is a multi-layer high bandwidth memory. A high bandwidth memory and a logic chip are integrated on a wafer using a fan-out embedded component packaging method, thereby improving the storage capacity; and the packaging efficiency is increased by means of a wafer-level bumping process. The multi-layer high bandwidth memory comprises: at least one high bandwidth memory chip module, wherein each high bandwidth memory chip module comprises N vertically stacked high bandwidth memory wafers, and is provided on the surface thereof with a first metal connection layer electrically connected thereto; a logic chip, which is provided on the surface thereof with a second metal connection layer electrically connected thereto; a plastic packaging layer, which coats the high bandwidth memory chip module, the logic chip, the first metal connection layer and the second metal connection layer, is provided on a first surface thereof with a redistribution layer and a surface passivation layer that are electrically connected to the first metal connection layer and the second metal connection layer, and is provided on a second surface thereof with a bearing layer; and bumps, which are electrically connected to the redistribution layer.
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Inventors:
LV XIMING (CN)
SU MEIYING (CN)
SU MEIYING (CN)
Application Number:
PCT/CN2023/080074
Publication Date:
March 14, 2024
Filing Date:
March 07, 2023
Export Citation:
Assignee:
NAT CENTER FOR ADVANCED PACKAGING CO LTD (CN)
International Classes:
H01L25/18; H01L21/56
Foreign References:
| CN115394768A | 2022-11-25 | |||
| CN113451292A | 2021-09-28 | |||
| CN109388595A | 2019-02-26 | |||
| CN112820702A | 2021-05-18 | |||
| US20210118863A1 | 2021-04-22 | |||
| CN110854093A | 2020-02-28 |
Attorney, Agent or Firm:
SHANGHAI ZHISHENG INTELLECTUAL PROPERTY OFFICE (CN)
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