Title:
MULTI-TABLE INSTRUCTION PREFETCH UNIT FOR MICROPROCESSOR
Document Type and Number:
WIPO Patent Application WO/2023/124345
Kind Code:
A1
Abstract:
A method, programming product, and/or system for prefetching instructions include an instruction prefetch table that has a plurality of entries, each entry for storing a first portion of an indirect branch instruction address and a target address, wherein the indirect branch instruction has multiple target addresses and the instruction prefetch table is accessed by an index obtained by hashing a second portion of bits of the indirect branch instruction address with an information vector of the indirect branch instruction. The method, programming product, and/or system further include a first prefetch table for uni-target branch instructions and a second prefetch table for multi-target branch instructions. In operation it is determined whether a branch instruction hits in one of the multiple prefetch tables; a target address for the branch instruction is read from the respective prefetch table in which the branch instruction hit; and the branch instruction is prefetched to an instruction cache.
Inventors:
GORTI NAGA P (US)
KARVE MOHIT (US)
KARVE MOHIT (US)
Application Number:
PCT/CN2022/123746
Publication Date:
July 06, 2023
Filing Date:
October 08, 2022
Export Citation:
Assignee:
IBM (US)
IBM CHINA CO LTD (CN)
IBM CHINA CO LTD (CN)
International Classes:
G06F9/30
Foreign References:
| US5964869A | 1999-10-12 | |||
| US20130275726A1 | 2013-10-17 | |||
| CN113515311A | 2021-10-19 | |||
| CN105988774A | 2016-10-05 | |||
| CN111158754A | 2020-05-15 |
Attorney, Agent or Firm:
CCPIT PATENT AND TRADEMARK LAW OFFICE (CN)
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