Multiboard Multiprocessor Connector System

Background of the Invention

1. Field of the invention

This invention relates to a connector system for a multiple circuit board system. More specifically, this invention relates to a connector system in a multiboard multiprocessor system, in which the processors are coupled in a two-dimensional array, but the boards are coupled in a line without a backplane.

2. Description of Related Art In computer systems with multiple circuit boards, it is advantageous to provide a connector system which does not use too much of the circuit board space for making connections. Where the multiboard system comprises a plurality of processors, the topology may require a large number of connections and thus exacerbate the problem. For example, multiprocessor systems with the processors connected in a square array, in a hypercube, or in other rich topologies have been proposed.

One method of the prior art is to connect the multiple circuit boards with a backplane, i.e., a wire connector which is joined to all of the circuit boards at a common location on each board. While this method of the prior art does connect all of the circuit boards, it has the drawbacks that (1) the backplane may supply only a limited number of connections, (2) the backplane may require a great deal of routing circuitry on each board, and (3) the backplane may be unsuitable for mμltiprocessor systems with a rich topology.

Summary of the Invention The invention provides a connector system for coupling a plurality of substantially identical circuit

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boards in a line, but forming logical connections as in a two-dimensional array such as a square. Each circuit board may comprise one or more connector ports, each of which may couple to a corresponding port on an adjacent circuit board, by means of a coupling element. Nonadjacent circuit boards may be coupled by means of a logical helix of connection paths, in which data from a plurality of input ports is circularly shifted to a plurality of output ports in a plurality of circuit boards, so that the data is ultimately coupled from a connector port on one circuit board to a corresponding port on a nonadjacent circuit board.

In a preferred embodiment, a square array of components is coupled with east-west wiring, north-south wiring, row and column wiring, and global wiring. East- west wiring may be made directly between adjacent circuit boards, and may be made by means of a logical helix coupling between nonadjacent circuit boards (such as at the two ends of a row) . North-south wiring may be made by means of a logical helix coupling between circuit boards which are one row apart. Row wiring may be made by means of a plurality of logical helix couplings; column wiring may be made directly and by reference to the row wiring. In a preferred embodiment, each circuit board may comprise one or more processors (such as an integrated circuit comprising a square array of processors) , and the connector system may couple the circuit boards in a square array, so as to form a square array of interconnecting processors. With known technology, at least 4096 processors may be coupled in a 64 x 64 array in a diameter of no more than 13 cm and a volume of no more than 1000 αα- ³ .

Brief Description of the Drawings

Figure 1 is a diagram of a multiprocessor system comprising an embodiment of the invention.

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Figure 2A is a diagram of a set of global wiring and a set of E-W wiring. Figure 2B is a diagram of a set of E-W wiring in an alternative embodiment.

Figure 3A is a diagram of a set of N-S wiring. Figure 3B is a diagram of a set of N-S wiring in an alternative embodiment.

Figure 4A is a diagram of a set of row wiring and a set of column wiring. Figure 4B is a diagram of a set of row wiring and a set of column wiring in an alternative embodiment.

Figure 5 is a diagram of a set of self-identifi¬ cation circuits.

Description of the Preferred Embodiment

An embodiment of this invention may be used together with inventions which are disclosed in a copending application titled "CLOSE-PACKED IMPEDANCE-CONTROLLED CONNECTORS", United States application Serial No. 738,051, Lyon & Lyon Docket No. 192/192, filed the same day in the name of Robert P. Stimson and Richard Jay Lind an, both assignors to the same assignee, hereby incorporated by reference as if fully set forth herein.

Figure 1 is a diagram of a multiprocessor system comprising an embodiment of the invention.

A multiprocessor system 101 may comprise a cylindrical processor platform 102 having a plurality of cylindrical slices 103. Each cylindrical slice 103 may comprise a plurality of processors 104 (e.g., embodied in an integrated circuit 105) in a square subarray 106 within a square array 107 of those processors 104. In a preferred embodiment, the platform 102 may comprise sixteen slices 103 with logical addresses 0,0 0,1 0,2 0,3 1,0 1,1 1,2 1.3 2,0 2,1 2,2 2,3 3,0 3,1 3,2 3,3 and physically disposed as shown in this table:

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0,0 0,1 0,2 0,3

1,0 1,1 1,2 1,3

2,0 2,1 2,2 2,3

3,0 3,1 3,2 3,3 In a preferred embodiment, the slices 103 may comprise an aluminum alloy or similar sturdy heat- resistant material, and may be coupled together with rods or screws 108.

Each slice 103 may comprise a plurality of connector slots 109 on each side 110, each of which may be empty or may be filled with an electrical connector 111. In a preferred embodiment, a connector 111 may comprise a gold- plated berylliumcopper springy "button connector" (or a "fuzzbutton", as they are also known in the art), such as a part named "CINAPSE" made by Cinch Corporation of Elk Grove Village, Illinois. However, it would be clear to one of ordinary skill in the art, after perusal of the specification, drawings and claims herein, that numerous other types of connectors would also be workable, and are within the scope and spirit of the invention. For example, the connectors 111 may comprise small metal plugs, springs, or tubes. The slots 109 on opposite sides 110 of each slice 103 are not necessarily coupled.

The slots 109 of adjacent slices 103 may be aligned to conform to a set of slot positions 112, so that when a first slice 103 and a second slice 103 are in physical proximity, the slots 109 of the two slices 103 may be coupled if both slots 109 are filled with connectors 111 and may be decoupled if one or both slots 109 are empty. Each slice 103 may also comprise a set of coupling circuits 113 for electrically coupling selected slots 109 together, or for coupling selected slots 109 to a set of circuits 114 (e.g., processors 104) on the slice 103. Thus, circuits 114 on one slice 103 may be coupled to circuits 114 on an adjacent slice 103 by means of a pair of slots 109 which are filled with connectors ill. Moreover, circuits 114 on one slice 103 may be coupled to

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circuits 114 on a nonadjacent slice 103 by means of pairs of slots 109 between a plurality of pairs of adjacent slices 103 and by means of circuits 114 on those slices 103. In a preferred embodiment, the slices 103 may be disposed physically in line within the platform 102, but the processors 104 on the slices 103 may be disposed logically in a square array within the array 107 of processors 104. It is desirable for each slice 103 to be electrically coupled to each other slice 103 with which it is logically coupled, such as E-W neighbors, N-S neighbors, other slices 103 in the same row or column, and among substantially all slices 103 globally. As used herein, "wiring" means electrical coupling between a slice 103 and another slice 103, "global wiring" means wiring among substantially all slices 103, "E-W wiring" means wiring between slices 103 which are E-W neighbors, "N-S wiring" means wiring between slices 103 which are N-S neighbors, "row wiring" means wiring between slices 103 which are in a row, and "column wiring" means wiring between slices 103 which are in a column.

Figure 2A is a diagram of a set of global wiring and a set of E-W wiring.

In a set of global wiring, substantially all slices 103 may be coupled by means of a single slot position 112. The slot 109 for that slot position 112 on each side 110 of each slice 103 may be filled, and the circuits 114 on each slice 103 may couple the slot 109 on the left side 110 of each slice 103 to the slot 109 on the right side 110 of each slice 103, so as to couple all slots 109 for that slot position 112 in each slice 103 together into a global wire 201. In a preferred embodiment, sixteen such global wires 201 may carry sixteen bits of information to substantially all slices 103. In a set of E-W wiring, each slice 103 may be coupled to a left neighbor 202 and to a right neighbor 203 by means of a set of four helical E-W wires 204 in a set of

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four E-W slot positions 112. The left side 110 of each slice 103 may be designated "E" and the right side 110 of each slice 103 may be designated "W". Within each slice 103, circuits 114 may couple each helical E-W wire 204 from one slot position 112 on the E side 110 to the next modulo-four on the W side 110; thus E-W wire 204 0E is coupled to E-W wire 204 IW, E-W wire 204 IE is coupled to E-W wire 204 2W, E-W wire 204 2E is coupled to E-W wire 204 3W and E-W wire 204 3E is coupled to E-W wire 204 OW, so as to fully couple all four helical E-W wires 204 on each slice 103 with its left neighbor 202 and its right neighbor 203.

For three out of each four pairs of slices 103, E-W neighbors occupy adjacent slices 103 and may be coupled directly by means of one of the four slot positions 112. The fourth pair of slices 103 may be coupled by means of one of the four helical E-W wires 204 cycling through all four slot positions 112. Thus, slice 103 0,0 is coupled to slice 103 0,1 is coupled to slice 103 0,2 is coupled to slice 103 0,3. The next four slices 103 may use a different one of the four helical E-W wires 204 so that slice 103 0,3 is not coupled to slice 103 1,0. . In a preferred embodiment, sixteen sets of E-W wiring may carry sixteen bits of information between E-W neighbor slices 103.

Figure 2B is a diagram of a set of E-W wiring in an alternative embodiment.

In an alternative embodiment, the platform 102 may comprise only four slices 103, with logical addresses 0,0 0,1 1,0 L,l and physically disposed as shown in this table:

0,0 0,1

1,0 1,1

A set of E-W wiring for an alternative embodiment may be similarly constructed, with two changes. First, no couplings are made between slice 103 0,1 and slice 103

1,0. Second, circuits 114 on slice 103 0,0 couple E-W

wire 204 0E with E-W wire 204 2E and couple E-W wire 204 IE with E-W wire 204 3E, while circuits 114 on slice 103 1,1 couple E-W wire 204 OW with E-W wire 204 2W and couple E-W wire 204 IW with E-W wire 204 3W. Figure 3A is a diagram of a set of N-S wiring.

In a set of N-S wiring, each slice 103 may be coupled to its left neighbor 202 and to its right neighbor 203 by means of a set of four helical N-S wires 301 in a set of four N-S slot positions 112. The left side 110 of each slice 103 may be designated "S" and the right side 110 of each slice 103 may be designated "N". Within each slice 103, circuits 114 may couple each helical N-S wire 301 from one slot position 112 on the S side 110 to the next on the N side 110; thus N-S wire 301 OS is coupled to N-S wire 301 IN, N-S wire 30115 is coupled to N-S wire 3012N and N-S wire 301 2S is coupled to N-S wire 301 3N, so as to couple three out of four helical N-S wires 301 on each slice 103 with its left neighbor 202 and to couple three out of four helical N-S wires 301 on each slice 103 with its right neighbor 203.

N-S neighbors do not occupy adjacent slices 103 and thus may be coupled by means of the four helical N-S wires 301 cycling through all four slot positions 112. Thus, slice 103 0,0 is coupled to slice 103 0,1 is coupled to slice 103 0,2 is coupled to slice 103 0,3 is coupled to slice 103 1,0. This pattern is continued unchanged throughout the entire platform 102, so that slice 103 0,0 is coupled to slice 103 1,0 is coupled to slice 103 2,0 is coupled to slice 103 3,0. Three global wires 201 may couple slice 103 3,0 with slice 103 0,0 as if they were left neighbor 202 and right neighbor 203 respectively. In a preferred embodiment, sixteen sets of N-S wiring may carry sixteen bits of information between N-S neighbor slices 103. Figure 3B is a diagram of a set of N-S wiring in an alternative embodiment.

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A set of N-S wiring for an alternative embodiment may be similarly constructed, with one change. Instead of three global wires 201 which couple slice 103 3,0 with slice 103 0,0 as if they were left neighbor 202 and right neighbor 203 respectively, two global wires 201 couple N-S wire 301 OS on slice 103 0,0 with N-S wire 3013N on slice 103 1,1 and couple NS wire 301 IS on slice 103 0,0 with N- S wire 301 2N on slice 103 1,1.

Figure 4A is a diagram of a set of row wiring and a set of column wiring.

In a set of row wiring, each slice 103 may be coupled to its left neighbor 202 and to its right neighbor 203 by means of a set of four helical row wires 401 in a set of four row slot positions 112, in like manner as in a set of E-W wiring, except that all connector slots 109 in all slices 103 are filled, making a fully connected set of four helical row wires 401 which cycle through the four row slot positions 112. Each row comprises one fourth of all the processors 104 and one of the four helical row wires 401. In a preferred embodiment, sixteen sets of row wiring may carry sixteen bits of information to each of four rows.

In a preferred embodiment, the array 107 of processors 104 may be controlled by a control unit 402, which may couple sixteen bits to each of four rows in the array 107, for a total of 64 bits. In a preferred embodiment, the control unit 402 may couple the same 64 bits as sixteen bits to each of four columns in the array 107. A set of column wiring may be coupled to a set of row wiring and may comprise two additional slot positions 112 for each slice 103. A set of first column wires 403 may couple all four slices 103 in each column, in like manner as in a set of global wiring, except that every fourth connector slot 109 remains unfilled. Thus, slices 103 0,0 0,1 0,2 and 0,3 are coupled; slices 103 1,0 1,1 1,2 and

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1,3 are coupled; slices 103 2,0 2,1 2,2 and 2,3 are coupled; and slices 103 3,0 3,1 3,2 and 3,3 are coupled.

A set of second column wires 404 may couple a selected one of the four helical row wires 401 to the first column wires 403, so as to couple information supplied on the row wires 401 to the four columns. In each slice 103, circuits 114 couple the selected one row wire 401 with the second column wire 404 on the right, and couple the second column wire 404 on the left to the first column wire 403 on the right. In a preferred embodiment, only one connector slot 109 is filled for each diagonal position in the array 107; thus the connector slot following slices 103 0,01,12,2 and 2,3 are filled (slice 103 2,3 is used because there is no connector slot following slice 103 3,3). Thus column 0 is coupled with row 0, column 1 is coupled with row 1, column 2 is coupled with row 2, and column 3 is coupled with row 3.

Figure 4B is a diagram of a set of row wiring and a set of column wiring in an alternative embodiment. A set of row wiring for an alternative embodiment may be similarly constructed, with two changes. First, circuits in slice 103 1,1 couple slot position 112 0 with slot position 112 2 and couple slot position 112 1 with slot position 112 3. Second, in the set of second column wires 404, only the connector slots 109 following slice 103 0,0 and slice 103 0,1 are filled.

Figure 5 is a diagram of a set of self-identification circuits.

In a preferred embodiment, each slice 103 may comprise a self-ID circuit 501, each of which is coupled both to circuits 114 on the slice 103 and to the self-ID circuits 501 on the left neighbor 202 (if one exists) and the right neighbor 203 (if one exists) . In each slice 103, each self-ID circuit 501 may receive a hexadecimal digit which represents the ID of its slice 103 from a set of four self-ID slot positions 502 coupled to the right neighbor 203, and may subtract one from that ID to

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determine the ID of its left neighbor 202. Each self-ID circuit 501 may transmit the ID of its own slice 103 to circuits 114 on its own slice 103 and the ID of its left neighbor 202 to the four self-ID slot positions 502 coupled to the left neighbor 202.

The four self-ID slot positions 502 for slice 103 3,3 may be coupled to the constant hexadecimal digit "F"

(decimal value fifteen), so as to identify slice 103 3,3 with that ID. Successive slices 103 will therefore each be identified with successively smaller IDs, down to hexadecimal digit "0" (decimal value zero) for slice 103

0,0. Each slice 103 may identify its logical position in the array 107 by noting the two most significant bits of its four-bit ID as its row address and the two least significant bits of its four-bit ID as its column address.

Alternative Embodiments

While preferred embodiments are disclosed herein, many variations are possible which remain within the concept and scope of the invention, and these variations would become clear to one of ordinary skill in the art after perusal of the specification, drawings and claims herein.

For example, while the invention has been disclosed with connections between slices which are physically made or broken, it would be clear to one of ordinary skill in the art, after perusal of the specification, drawings and claims herein, that connections between slices could be made with active circuits such as transceiver gates, so as to make those connections dynamically reconfigurable in the face of dynamic conditions.

Moreover, while the invention has been disclosed with circuits on each slice which are physically made or broken, it would be clear to one of ordinary skill in the art, after perusal of the specification, drawings and claims herein, that circuits on each slice could be made with active circuitry such as transceiver gates, so as to

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make those circuits dynamically reconfigurable (and so as to make the connectivity of the platform dynamically reconfigurable) in the face of dynamic conditions.

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