Title:
MULTIINPUT LOGICAL GATE
Document Type and Number:
WIPO Patent Application WO/2003/055074
Kind Code:
A1
Abstract:
A multiinput logical gate has a first resistor, and a second resistor one end of which is connected to a power source each, a current source, m pieces of transistors (m is an integer of 2 or more) the sources of which are parallel-connected to the current source, and the drain of which to the other ends of the first resistors, and m pieces of transistors the sources and drains of which are series-connected between the current source and the other ends of the second resistors. M pairs of differential input signals are inputted to the gates of the parallel-connected transistors and the gates of the series-connected transistors, respectively, and are outputted from the other ends of the first and second resistors as differential signals, respectively.
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Inventors:
SHIMPO YUKIO (JP)
YAMAGISHI AKIHIRO (JP)
TSUKAHARA TSUNEO (JP)
YAMAGISHI AKIHIRO (JP)
TSUKAHARA TSUNEO (JP)
Application Number:
PCT/JP2002/013191
Publication Date:
July 03, 2003
Filing Date:
December 17, 2002
Export Citation:
Assignee:
NIPPON TELEGRAPH & TELEPHONE (JP)
NTT ELECTRONICS CORP (JP)
SHIMPO YUKIO (JP)
YAMAGISHI AKIHIRO (JP)
TSUKAHARA TSUNEO (JP)
NTT ELECTRONICS CORP (JP)
SHIMPO YUKIO (JP)
YAMAGISHI AKIHIRO (JP)
TSUKAHARA TSUNEO (JP)
International Classes:
H03K19/20; H03K19/094; H03K19/0944; (IPC1-7): H03K19/20; H03K19/0944
Foreign References:
| JPS58114630A | 1983-07-08 | |||
| JPS62261225A | 1987-11-13 | |||
| JP2001244808A | 2001-09-07 |
Attorney, Agent or Firm:
Miyoshi, Hidekazu (2-8 Toranomon 1-chome, Minato-k, Tokyo 01, JP)
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