Title:
MULTILAYER CAPACITOR, AND WIRING BOARD
Document Type and Number:
WIPO Patent Application WO/2017/098767
Kind Code:
A1
Abstract:
This multilayer capacitor (1), which is mounted between a power supply and a ground of an IC mounted to a wiring board, is provided with: a stacked body (10) in which first internal electrodes (16) and second internal electrodes (17) are alternately stacked with dielectric layers (15) therebetween; a first external electrode (11) connected to first lead-out portions (16b) of the first internal electrodes (16); a second external electrode (12) connected to second lead-out portions (16c) of the first internal electrodes (16); and a third external electrode (13) connected to lead-out portions (17b) of the second internal electrodes (17). The first and second external electrodes (11, 12) are connected to a power supply pattern of the wiring board. The third external electrode (13) is connected to a ground of the wiring board. A first path which passes between the first external electrode (11) and the third external electrode (13) has a high ESR and a low ESL. A second path which passes between the second external electrode (12) and the third external electrode (13) has a low ESR and a high ESL.
Inventors:
FUJII YASUO (JP)
Application Number:
PCT/JP2016/076936
Publication Date:
June 15, 2017
Filing Date:
September 13, 2016
Export Citation:
Assignee:
MURATA MANUFACTURING CO (JP)
International Classes:
H01G4/232; H01G2/06; H01G4/30; H05K3/46
Foreign References:
| JPH0459914U | 1992-05-22 | |||
| JP2014096541A | 2014-05-22 | |||
| JP2001185441A | 2001-07-06 | |||
| JPH10233485A | 1998-09-02 |
Attorney, Agent or Firm:
UEDA Kazuhiro (JP)
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