Title:
MULTILAYER CERAMIC CAPACITOR
Document Type and Number:
WIPO Patent Application WO/2024/070337
Kind Code:
A1
Abstract:
The present invention provides a multilayer ceramic capacitor (1) in which the occurrence of dielectric breakdown is further suppressed. The multilayer ceramic capacitor (1) comprises: a laminate (2) including a plurality of dielectric layers (4) and a plurality of internal electrode layers (10) stacked on one another; and external electrodes (20) provided on a first end surface (62a) and a second end surface (62b). The internal electrode layers (10) comprise first internal electrode layers (10a) and second internal electrode layers (10b), the first internal electrode layers (10a) being led to the first end surface (62a), and the second internal electrode layers (10b) being led to the second end surface (62b). The external electrodes (20) include a first external electrode (20a) connected to the first internal electrode layers (10a) and a second external electrode (20b) connected to the second internal electrode layers (10b). A region that is disposed on the first end surface (62a) side and in which the first internal electrode layers (10a) do not overlap each other in the stacking direction (T), and a region that is disposed on the second end surface (62b) side and in which the second internal electrode layers (10b) do not overlap each other in the stacking direction (T) are defined as L gap regions (51). The L gap regions (51) comprise Si segregation layers (14).
Inventors:
URATANI KOSUKE (JP)
Application Number:
PCT/JP2023/030103
Publication Date:
April 04, 2024
Filing Date:
August 22, 2023
Export Citation:
Assignee:
MURATA MANUFACTURING CO (JP)
International Classes:
H01G4/30
Foreign References:
| JP2004096010A | 2004-03-25 | |||
| JP2001237140A | 2001-08-31 | |||
| JP2001126951A | 2001-05-11 |
Attorney, Agent or Firm:
KATO Ryuta et al. (JP)
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