Title:
MULTILAYER STRUCTURE, METHOD FOR PRODUCING MULTILAYER STRUCTURE AND SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2024/048393
Kind Code:
A1
Abstract:
This multilayer structure comprises an amorphous substrate that has an insulating surface, an alignment layer that is arranged on the amorphous substrate, and a semiconductor pattern that contains gallium nitride and is arranged on the alignment layer; and the alignment layer has a first region that overlaps with the semiconductor pattern and a second region that does not overlap with the semiconductor pattern. The upper surface of the second region is positioned below the upper surface of the first region. The alignment layer has a groove part in the second region, the groove part extending from the vicinity of the lower end of the semiconductor pattern toward the first region; and when viewed in plan, the groove part overlaps with the semiconductor pattern. The alignment layer has a lateral surface in the first region, the lateral surface being connected to the upper surface of the second region.
Inventors:
AOKI HAYATA (JP)
NISHIMURA MASUMI (JP)
NISHIMURA MASUMI (JP)
Application Number:
PCT/JP2023/030331
Publication Date:
March 07, 2024
Filing Date:
August 23, 2023
Export Citation:
Assignee:
JAPAN DISPLAY INC (JP)
International Classes:
H01L21/20; C30B25/06; C30B29/38; H01L21/3065; H01L21/338; H01L29/778; H01L29/812; H01L33/32
Foreign References:
| JP2012119569A | 2012-06-21 | |||
| JP2017178766A | 2017-10-05 | |||
| JPH11243229A | 1999-09-07 | |||
| JPS5710280A | 1982-01-19 | |||
| JP2000124140A | 2000-04-28 | |||
| JPH08139361A | 1996-05-31 | |||
| JP2000269605A | 2000-09-29 | |||
| JP2018168029A | 2018-11-01 |
Attorney, Agent or Firm:
TAKAHASHI, HAYASHI AND PARTNER PATENT ATTORNEYS, INC. (JP)
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