CROSS REFERENCES TO RELATED APPLICATIONS

This patent application is related to commonly owned US Patent Application entitled: Method And System For Power Optimization For System Of Thermoelectric Cooling Devices (Attorney Docket 6919/13), filed on the same day as this patent application, the disclosure of this patent application is incorporated by reference in its entirety herein.

TECHNICAL FIELD

The present disclosure relates to thermoelectric coolers (TECs or TEMs), and specifically, to multilevel thermoelectric cooling stacks.

BACKGROUND

Many imaging applications use an electronic element, such as a complementary metal oxide semiconductor (CMOS) or a charge-coupled device (CCD), which is sensitive to thermal noise. As a result, these semiconductors and/or CCDs require cooling to near-cryogenic temperatures in order to achieve optimal performance. Active cooling to such temperatures may be achieved using a multilevel thermoelectric cooling (TEC) stack, formed of two or more devices.

Each device includes solid state p-n junctions, between plates. The p-n junctions are typically connected electrically in series and connected thermally in parallel. One plate is a hot side and the other plate is the cold side, as the p-n junctions, when subject to an electric current, pump, or otherwise transfer heat from the cold side to the hot side. For example, a stack is formed with one device on top of the another, with the top device within the surface area of the bottom device. The top device has an exposed cold side, for receiving an element, such as an integrated circuit, to be cooled, and the bottom device has its hot side exposed.

The above described TEC stack exhibits numerous drawbacks, such as: thermal energy leaks from the ambient environment (or the higher TEC levels), in a direction toward the element. When the element to be cooled is a high pin-count electronic device, the number of conductors and of corresponding ground planes in a printed circuit board (PCB), on which the device is mounted, gives rise to a multiplicity of thermal conduction paths, resulting in thermal leakage reaching the element. In addition, there is a contribution to thermal leakage caused by thermal (black-body) radiation. Regardless of the source, even small amounts of thermal leakage create a positive feedback mechanism, which further increases the power dissipation of the TEC levels. This makes the lowest levels of the stack considerably more vulnerable (than the higher levels) to any additional load created by thermal leaks.

Another drawback of the aforementioned TECs is that the TEC levels, which are distanced further from the element, not only dissipate more heat, but are also maintained at a higher temperature than those which are closer to the element. In general, thermal conduction increases linearly with the difference in temperature of two adjacent bodies, and thermal radiation as the difference in the fourth power of their temperatures. Therefore, the furthermost (in distance) layers, from the semiconductor and/or CCD are often the greatest contributors of thermal leakage by conduction and radiation.

SUMMARY OF THE DISCLOSURE

The present disclosure includes embodiments directed to multilevel thermoelectric cooling (TEC) stacks, each TEC stack including a plurality of successive of TEC levels, each level including a device with a guard ring extending from and running along the device periphery. The TEC stacks levels are layered one on top of the other, for channeling or “wicking” thermal power away from an element mounted on a substrate, such as a circuit board, and in communication with the uppermost TEC level, to be cooled. The element may generate an intrinsic heat load, which is transferred by the successive TEC levels to a heat sink, and from there, to the ambient or to a fluid, such as water, which may or may not be pre-chilled.

The disclosed multilevel thermoelectric cooling (TEC) stack channels thermal power away from an element to be cooled which is mounted on a substrate such as a circuit board and may generate an intrinsic heat load. The TEC stack has an inner TEC level which is in direct or indirect communication, including thermal communication including, for example, thermal contact, with the element and an outer TEC level. At least one of the TEC levels includes a shaped thermal guard ring which is in thermal contact with the substrate. The thermal guard ring(s) define isothermal boundaries on the substrate, and effectively channel, or “wick”, thermal power away from the element to be cooled. The thermal guard ring(s) may be fitted with thermal radiation shield(s). The guard ring temperature(s) are adjusted by an external TEC power supply and controller, in order to minimize the total electrical power consumed by the stack while keeping the element at or below a threshold temperature.

Unless otherwise defined herein, all technical and/or scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the disclosure pertains. Although methods and materials similar or equivalent to those described herein may be used in the practice or testing of embodiments of the disclosure, exemplary methods and/or materials are described below. In case of conflict, the patent specification, including definitions, will control. In addition, the materials, methods, and examples are illustrative only and are not intended to be necessarily limiting.

BRIEF DESCRIPTION OF THE DRAWINGS

Some embodiments of the present disclosure are herein described, by way of example only, with reference to the accompanying drawings. With specific reference to the drawings in detail, it is stressed that the particulars shown are by way of example and for purposes of illustrative discussion of embodiments of the disclosure. Dimensions of components and features shown in the figures are chosen for convenience and clarity of presentation and are not necessarily shown to scale. The description taken with the drawings makes apparent to those skilled in the art how embodiments of the disclosure may be practiced.

Attention is now directed to the drawings, where like reference numerals or characters indicate corresponding or like components. In the drawings:

FIGs. 1A and IB are cross-sectional diagrams of an exemplary multilevel TEC stack, according to an embodiment of the disclosure;

FIG. 2 is a side view of an exemplary TEC level, according to the principles of the disclosure; and,

FIGs. 3A and 3B are thermal diagrams corresponding to the embodiment of FIGs. 1 A and IB.

DETAILED DESCRIPTION OF THE DRAWING FIGURES

The disclosed subject matter provides a multilevel thermoelectric cooling (TEC) stack, which channels thermal power away from an element to be cooled which is mounted on a substrate such as a circuit board, and is responsive to the element generating an intrinsic heat load. The TEC stack has an inner TEC level which is in direct or indirect thermal contact with the element and an outer TEC level. At least one of the TEC levels includes a shaped thermal guard ring which is in thermal contact with the substrate. The thermal guard ring(s) define isothermal boundaries on the substrate, and effectively channel, or “wick”, thermal power away from the element to be cooled. The thermal guard ring(s) may be fitted with thermal radiation shield(s). The guard ring temperature(s) are adjusted by an external TEC power supply and controller, in order to minimize the total electrical power consumed by the stack while keeping the element at or below a threshold temperature.

FIGs. 1A and IB are cross-sectional diagrams of an apparatus, a multilevel thermoelectric cooling (TEC) stack 100, according to an embodiment of the disclosed subject matter. The TEC stack 100 includes at least two and, for this example, three, TEC levels 110, 120, 130. These example levels include an inner level 110, which includes a TEC device HOd, an intermediate level 120; which includes a TEC device 120d, and, an outer level 130; which includes a TEC device 130d. Each TEC device typically consists of a multiplicity of Peltier junctions sandwiched between plates, whose temperature difference is controlled by electrical currents supplied to the TEC devices by an external power supply.

Shaped thermal guard rings 1 lOd, 120d, and 130d are positioned proximate to, and extend at least partially along, the periphery of the corresponding TEC levels 110, 120, and 130. The guard rings are, for example, in thermal contact with a substrate 220, such as a circuit board (shown in broken lines), and form corresponding isothermal boundaries, or isotherms, 110b, 120b, and 130b on the circuit board 220. The isotherms are configured to set up a geometrical temperature distribution on the substrate 220, so as to direct the flow of heat away from the element 205 and towards a heat sink 230 (both shown in broken lines). The latter releases the heat, for example, to an ambient environment.

The geometric temperature distribution is defined by the ring temperatures (T1 for ring 110a, T2 for ring 120a, and T3 for ring 130a) and T5 for the ambient. The temperature differences (T2-T1, T3-T2, and T5-T3) are controllable by the electrical currents flowing in each of the TEC levels 110, 120, 130. The greater the current applied to a TEC level, the larger is temperature difference for that TEC level.

In FIG. 1A, the isotherms 110b, 120b, 130b, are shown, for example, as having a rectangular shape. Alternately, other shapes are suitable for these isotherms, such as polygonal, elliptical, circular, any closed or partially closed curve, or combinations thereof, provided that the thermal gradients established by the isotherms direct the flow of heat away from the element 205.

The guard rings 110a, 120a, 130a are, for example, of a thermally conductive material, such as a thermally conductive ceramic, a metal or metal alloy. For example, the material of the guard rings is of a thermal conductivity which is greater than or equal to 100 watts per meter per degree Celsius (W/m/°C) within the temperature range of, for example, approximately -20°C to approximately -100°C. Example materials meeting the aforementioned thermal conductivity, at the aforementioned predetermined temperature, include gold, silver, aluminum, copper, boron nitride, and aluminum nitride. Furthermore, the guard ringsl 10a, 120a, 130a, for example, may be structured as solid materials or as vapor chambers, such as heat pipes.

Turning now to FIG. IB the apparatus, the TEC stack 100, is shown with an element 205, such as an integrated circuit, mounted on a substrate, such as a circuit board 220. The element 205 is in thermal communication with the outer (or uppermost) TEC level 110. The circuit board 220 is, for example, parallel to the X-Y plane and perpendicular to the Z-axis. The element 205 may be surface-mounted to the circuit board 220, for example, by a ball-grid-array (BGA) which is bonded to multiple, typically on the order of hundreds, of contacts on the circuit board 220. The contacts, for example, act as electrical conductors and also as thermal conductors, enabling a flow of heat between the element 205 and one or more conducting planes inside the circuit board 220. The geometric temperature distribution across the surface of board 220 determines whether heat flows towards, or away from, the element 205.

Thermal radiation shields 210c, 220c, 230c extend from the circuit board 220. The radiation shields 210c, 220c, 230c, are in communication, for example, thermal contact, with the respective thermal guard rings 110a, 120a, 130a, so as to at least partially surround the element 205 (with the innermost guard ring 110a and its radiation shield 210c at least partially surrounding the element 205) . The radiation shields 210c, 220c, 230c, for example, on their sides facing away from the element 205, include a reflective layer, for example, gold, silver, brass, copper or aluminum. Alternately, the material of the reflective layer has a reflectivity which is, for example, in the range of 0.95 to 1.00 over a predetermined spectral range which depends upon the ambient temperature of objects within line of sight of element 205.

The threshold reflectivity and the spectral range are governed by the physics of thermal radiation, which is emitted by all bodies at a temperature above absolute zero (0 Kelvin), equal to approximately -273°C. The total thermal power, P, radiated by a perfect black body is equal to oA(T+273) ⁴ , where P is in watts, T is the temperature of the body in degrees C, A is the surface area of the body in square centimeters (cm ² ) and c> is the Stefan-Boltzmann constant, equal to 5.67xl0 ¹² watts/(cm ² -K ⁴ ). For example, for a black body of area A=10 cm ² and temperature T=20°C, the total thermal power is P = 0.42 watts. Of this total power, roughly 50%, or 0.21 watts, is emitted at wavelengths less than 14 |im. For this example, a radiation shield having a 95% reflectivity in the spectral range below 14 |im would block approximately 0.95 x 0.21 = 0.2 watts of thermal radiation from reaching the element 205.

FIG. 2 is a side view, taken along the X-axis, of an exemplary TEC level 310. A TEC device 310d is in thermal communication with a shaped thermal guard ring 310a. Temperature sensors 3 lOt provide temperature readings Ti and To at the inner 3 lOi and outer 310o surfaces of the TEC device 310d. The temperature readings are output to an external TEC controller, for example, by a wired connection, a fiber-optic cable, or a wireless connection. The connections between external devices, such as a TEC controller 350 (shown in dashed lines) and a TEC power supply 360, and the TEC level 310 are designed to prevent, or at least to minimize, the possibility of thermal leakage from the external devices towards the TEC level 310, the circuit board 220, or the heat sink 230. For example, fiber-optics and/or capacitive coupling between the TEC controller 350 and the TEC level 310 may be used, instead of electrical wires, in order to prevent a source of thermal leakage caused by thermal conduction through the wires.

The TEC controller 350 operates in conjunction with the TEC power supply 360 that is operably connected to the TEC devices at each TEC level, for the purpose of adjusting the temperature distribution between the TEC levels (thereby altering the effective Coefficient of Performance (COP) of each level), to reduce the electrical power required from the TEC power supply, while maintaining the element at the desired temperature. The process is computer- implemented, and functions to minimize the total electrical power consumed by the TEC levels 110, 120, 130 of the TEC stack 100, to maintain a desired temperature for the element 205, the computer-implemented process is detailed, for example, in commonly owned patent application entitled: Method And System For Power Optimization For System Of Thermoelectric Cooling Devices (Attorney Docket 6919/13).

In other embodiments, a layer of thermally conductive interface material 31 Op is applied on either side of the TEC device 310d, in order to reduce the thermal contact resistance at the interfaces with adjacent components. For example, when the TEC level 310 represents the intermediate TEC level 120, the inner surface 3 lOi is adjacent to TEC level 110 and the outer surface 310o is adjacent to TEC level 130.

TEC device 310 may be implemented, for example, using Peltier modules produced by CUI Devices, which are available in a variety of sizes and heat flux capacities. Temperature sensor 3 lOt may be, for example, a Cernox® thin film resistance cryogenic temperature sensor produced by Lakeshore Cryotronics, Inc, Westerville Ohio 43082, USA, which covers a temperature range of, for example, from -272°C to 147°C. The thermally conductive interface material 310p may be for example, Apiezon® N grease, available from Lakeshore Cryotronics, which has low vapor pressure and high thermal conductivity and solidifies below 30°C. In other embodiments, the guard ring 310a is in thermal contact with a shaped thermal radiation shield 310c. FIG. 2 shows an exemplary thermal radiation shield 310c which includes a shield substrate 311c coated with a reflective layer 312c. The reflective layer is applied at least on the surfaces of the shield substrate 311c that face away from the element. In an alternative embodiment, the shield substrate may be an integral part of the guard ring itself, and the reflective layer may be one or more highly polished surfaces of the shield substrate.

FIGs. 3A and 3B are thermal diagrams corresponding to the embodiment of FIGs. 1 A and IB, in which the isothermal boundaries 110b, 120b, and 130b are concentric circles, rather than rectangles. In FIG. 3A, an inner zone Z1 and intermediate zones Z2 and Z3 are areas on the circuit board 220 which are bounded by the isothermal boundaries 110b, 120b, and 130b at temperatures Tl, T2, and T3 respectively. Outer zone Z4 is the area on the circuit board 220 that is external to the outermost isothermal boundary 130b and is assumed to be at an ambient temperature T5. In FIG. 3B, QI, Q2, and Q3 denote the heat fluxes, in units of watts, which are pumped away from the element 205 by TEC devices HOd, 120d, and 130d, respectively. The values of QI, Q2, and Q3 are generally positive in the direction indicated by the dashed arrows. The element 205 is kept at temperature Tl, and the heat sink 230, which delivers the total heat flux produced by the element and the entire TEC stack to the ambient environment, is at temperature T4. Typically, T1<T2<T3<T5 <T4.

In other embodiments, a fan may be used to facilitate the removal of heat by convection between the heat sink and the ambient air (environment). Alternatively, the heat sink may be designed to have chilled water flowing through it in conductive pipes. In the latter case, the temperature of the heat sink T4 is significantly lower than that of the ambient temperature T5.

Operational Example

A TEC stack with three levels was produced in accordance with FIGs. 3 A and 3B. The element 205 is mounted at the center of the inner zone Zl, whose radius is Rl=1.5 centimeters (cm). The intermediate zone Z2 is an annulus with inner radius R1 and an outer radius R2=2.75 cm. The intermediate zone Z3 is an annulus with the inner radius R2 and an outer radius R3=4.0 cm. Outer zone Z4 has inner radius R3, and extends radially outwards from zone Z3.

The stack includes three TEC levels with one TEC device per level. The inner TEC level is in thermal communication with zone Zl and zone Z2. The intermediate TEC level is in thermal communication with zone Z2 and zone Z3, and the outer TEC level is in thermal communication with zone Z3 and zone Z4.

In order to maintain element 205 at a low operating temperature, the external TEC controller measures temperatures Tl, T2, T3, and T4, shown in Table 1 below as having the values -60, -30, 0, and +30°C, respectively. The TEC controller then issues commands to the TEC power supply so as to maintain the temperature difference

T2-T1, T3-T2, and T4-T3, at a desired value of 30°C. The circuit board 220 is assumed to have a single copper plane with a thickness of 35 microns and an effective radial thermal resistance equal to 11.12°C/W between isothermal boundaries 110b and 130b. Furthermore, each of the three TEC devices is assumed to operate with a coefficient of performance (COP) approximately equal to 0.6.

The heat fluxes are calculated using analytical methods which are facilitated by the circular symmetry and may also be checked numerically by using a finite-element thermal simulation. Table 1 shows the thermal performance of a prior-art TEC stack, which does not use the shaped thermal guard rings disclosed in the present disclosure, in the case when element 205 generates an intrinsic heat load of 1.0 watt. Table 1

Total Electrical Power : 130.2

The leakage heat flux in the inner TEC level 110 is caused by heat flow from the ambient environment, mainly through the circuit board, and this greatly increases the effective heat load that must be pumped by the inner TEC level. The electrical power consumed by each TEC level appearing in the penultimate column of Table 1 is equal to the effective input heat flux divided by the COP of the TEC device, which is approximately 0.6. The output heat flux incorporates the effective input heat flux and the electrical power and becomes the input heat flux for the subsequent level. The total electrical power required by the prior-art TEC stack is found to be 130.2 watts.

Table 2 shows the thermal performance of a TEC stack which is fitted with shaped thermal guard rings, as per the disclosed subject matter. By comparison with Table 1, the leakage heat flux in the inner TEC level 110 is substantially reduced, because the guard rings prevent heat generated by the other TEC levels as well as heat from the ambient environment from reaching the inner TEC level. It is believed that the reason for this may be that the maximum temperature difference seen by each of the three TEC levels is only 30°C, because the guard rings effectively isolate the TEC devices from each other - not by thermal insulation, as in the prior art TEC stacks, but rather, by the thermal “wicking” provided by the highly conducting thermal guard rings. The electrical power appearing in the penultimate column of Table 2 is calculated in the same way as in Table 1 , by dividing the effective heat load by the COP of approximately 0.6. The total electrical power required by the TEC stack is found to be just 118.6 watts, which is 10% less than that required by the prior-art TEC stack. Table 2

Total Electrical Power : 118.6

EXAMPLES

EXAMPLE 1

A multilevel thermoelectric cooling (TEC) apparatus comprises: a first thermoelectric cooling (TEC) level comprising a TEC device and a guard ring extending from the TEC device at a periphery of the TEC device, the TEC device configured for receiving an element to be cooled within the periphery; a second TEC level in thermal communication the first TEC level, the second TEC level comprising a TEC device whose periphery extends beyond the periphery of the device of the first TEC level and a guard ring extending from the TEC device of the second TEC level in the direction in which the guard ring of the first TEC level extends; each said thermal guard ring forming an isothermal for the respective TEC device; and, a power supply in electrical communication with the device of at least one of the first TEC level or second TEC level, to provide power to each said device and cause heat to flow in the direction from the first TEC level to the second TEC level.

EXAMPLE 2

The multilevel thermoelectric cooling (TEC) apparatus of Example 1 , wherein each TEC device includes oppositely disposed hot and cool sides, and the device of the first TEC level at the hot side is in thermal communication with the cool side of the device of the second TEC level.

EXAMPLE 3

The multilevel thermoelectric cooling (TEC) apparatus of Example 1 or Example 2, wherein the first TEC level is configured to at least partially surround the element to be cooled. EXAMPLE 4

The multilevel thermoelectric cooling (TEC) apparatus of any of Example 1 to Example 3, additionally comprising at least one intermediate TEC level between the first TEC level and the second TEC level, the intermediate TEC level comprising a TEC device whose periphery extends between the periphery of the device of the first TEC level and the periphery of the device of the second TEC level and a guard ring extending from the TEC device of the intermediate TEC level in the direction in which the guard ring of the first TEC level and the guard ring of the second TEC level extend.

EXAMPLE 5

The multilevel thermoelectric cooling (TEC) apparatus of any of Example 1 to Example 4, additionally comprising: a substrate in communication with each said guard ring.

EXAMPLE 6

The multilevel thermoelectric cooling (TEC) apparatus of any of Example 1 to Example 5, wherein the substrate comprises a material selected from a group consisting of ceramic, glass, metal, wood, paper, plastic, foam, and crystalline substances.

EXAMPLE 7

The multilevel thermoelectric cooling (TEC) apparatus of any of Example 1 to Example 6, wherein the substrate comprises a circuit board.

EXAMPLE 8

The multilevel thermoelectric cooling (TEC) apparatus of any of Example 1 to Example 7, wherein at least one of the guard rings comprises a material having a thermal conductivity which is greater than 100 watts per meter per degree Celsius at a predetermined threshold temperature, for example, a range of approximately -20°C to approximately -100°C. EXAMPLE 9

The multilevel thermoelectric cooling (TEC) apparatus of any of Example 1 to Example 8, wherein, at least one of the guard rings is structured as a solid material, a vapor chamber, or a heat pipe.

EXAMPLE 10

The multilevel thermoelectric cooling (TEC) apparatus of any of Example 1 to Example 9, wherein at least one of the guard rings comprises a metal or metal alloy which includes a material selected from a group consisting of gold, silver, aluminum, copper, boron nitride, and aluminum nitride.

EXAMPLE 11

The multilevel thermoelectric cooling (TEC) apparatus of any of Example 1 to Example

10, additionally comprising at least one thermal radiation shield in communication with at least one of said guard rings.

EXAMPLE 12

The multilevel thermoelectric cooling (TEC) apparatus of any of Example 1 to Example

11 , wherein the at least one shaped thermal radiation shield is in thermal comprises at least one reflective surface.

EXAMPLE 13

The multilevel thermoelectric cooling (TEC) apparatus of any of Example 1 to Example

12, wherein the at least one thermal radiation shield comprises a material selected from a group consisting of gold, silver, copper, brass, molybdenum, nickel, platinum, tungsten, bismuth, zinc, lead, tin, mercury, and aluminum.

EXAMPLE 14

The multilevel thermoelectric cooling (TEC) apparatus of any of Example 1 to Example

13, wherein the at least one reflective surface comprises a material having a thermal emissivity less than or equal to 0.05 over a predetermined range of thermal wavelengths. EXAMPLE 15

The multilevel thermoelectric cooling (TEC) apparatus of any of Example 1 to Example

14, additionally comprising a temperature sensor in communication with each said TEC level.

EXAMPLE 16

The multilevel thermoelectric cooling (TEC) apparatus of any of Example 1 to Example

15, additionally comprising a heat sink in communication with the second TEC level, the heat sink configured for causing a total heat flux produced by the element and the stack of TEC devices to flow to the ambient environment or to a pre-chilled heat transfer fluid.

EXAMPLE 17

The multilevel thermoelectric cooling (TEC) apparatus of any of Example 1 to Example

16, wherein the element to be cooled is in communication with external devices using fiber-optics and/or capacitive coupling.

EXAMPLE 18

The multilevel thermoelectric cooling (TEC) apparatus of any of Example 1 to Example

17, additionally comprising: an external TEC controller in communication with each said temperature sensor, the TEC controller configured to select a temperature differential for each of two or more TEC levels, such that a temperature of one or more of the guard rings is adjusted to minimize a total electrical power required from the power supply, while keeping the element at or below a predetermined threshold temperature of, for example, between approximately 10°C and approximately - 150°C.

Although the disclosure has been described in conjunction with specific embodiments, many alternatives, modifications, and variations will be apparent to those skilled in the art. Accordingly, the disclosure is intended to embrace all such alternatives, modifications, and variations that fall within the spirit and broad scope of this disclosure.