2. Description of the Relevant Art The continuing proliferation of computer development and applications has lead to computer systems that incorporate"multimedia"capability. That is, present computer technology allows for the processing of audio and video information as such information is generated by devices external to the central processing unit (CPU) or computer. For example, multimedia computers may present video images and/or audio tracks from a medium such as a CD-ROM.

Fig. I shows a typical prior art computer system depicting the elements relevant to the present discussion. A central processing unit (CPU) core 10 is coupled to an LI cache system 15 and a bus Input/Output (I/O) device 16 over a CPU local bus 8. The L I cache system 15 typically includes a cache controller and a cache SRAM (not shown). The CPU core 10, LI cache system 15. and bus I/O 16 may be implemented as separate discrete components but preferably are integrated onto a single chip processor as indicated by dashed box 9.

The bus I/O device 16 couples the CPU local bus 8 to a memory bus 11. A memory control unit or memory controller 12 also couples to the memory bus 11. A second level cache, referred to as an L2 cache 7. couples to the memory bus 11 and also couples to the memory control unit 12. The memory control unit 12 couples to a memory device 13. The memory device 13 typically is dynamic random access memory (DRAM).

A bus bridge 17 couples the memory bus 11 to a peripheral bus 18. Peripheral devices 19 are coupled to the peripheral bus. A multimedia device 190 represents one type of peripheral device which is coupled to the peripheral bus 18. Examples of multimedia devices are CD-ROM drives, graphics cards. video recorders. sound cards. modems. and the like.

The CPU core 10 and peripheral devices 19 and 190 communicate through the bus bridge 17 in different ways. A simple communication scheme allows data from the CPU core 10 to be placed on the CPU local bus 11 and transferred through the bus I/O device 16. memory bus 11. bus bridge 17, peripheral bus 18, and to a peripheral device/multimedia device. Data communication from the peripheral devices 19 and 190 to the CPU core 10 follows the same path, albeit in the reverse order.

The CPU core 10 typically engages in multiple activities such as access cycles to the memory device 13 through memory control unit 12. accesses to the LI cache SRAM 15. as well as receiving and transmitting data to a variety of peripheral devices 19/190. The CPU core 10 often performs digital signal processing (DSP) operations on video and audio data to and from the multimedia device 190. Digital signal processing is a time-consuming, iterative process often involving vast amounts of data and requiring a large portion of the CPU's computing resources.

Multimedia data often comprises real-time. isochronous data (i. e.. video and audio data metered out in regular time periods). For real-time data. such as video and audio. to be effectively observed by the human user. it must be performed (e. g., video data displayed on a monitor or sound data provided to speakers) at the same rate at which the

data was acquired originally. Any delays in processing will render music or motion pictures. for example. unintelligible and useless. As such. multimedia data often requires processing by the CPU"on the fly"or in real time." These demands on the CPU's processing power often renders direct communication between a multimedia device 190 and the CPU core 10 impractical because the CPU generally can receive, transmit and process data much faster than the multimedia device 190. Direct data transmission between CPU and multimedia device, consequently, may not be the most efficient transmission scheme in light of other processing demands on the CPU. Consequently, data from the multimedia device may be stored or buffered in the memory 13. Once in the memory, the CPU core 10 can retrieve the multimedia data more efficiently as larger blocks of data can be retrieved with less access overhead than with datum by datum transfers directly between multimedia device and CPU.

However, latency effects renders memory structures incapable of allowing real-time blocks of data to be stored, retrieved. and processed without detrimentally effecting the data's real-time nature. Further. latency in accessing DRAM often is unpredictable. For example. video data that is stored in the memory device 13 and periodically processed by the CPU core 10 with the latency inherent to the system may result in dropped frames or missed audio data. thereby resulting in jerky video and poor audio quality.

Buffering the multimedia data directly in the L1 cache system instead of main memory might be beneficial as cache memory accesses are faster and more efficient than accesses to system memory. However. directly buffering the multimedia data in the LI cache system 15 and bypassing main memory storage is impractical because cache memories cannot be used directly by peripheral devices to store data.

Therefore. it would be desirable to have a multimedia data controller capable of allowing real-time CPU processing of multimedia data while accomplishing other CPU-related tasks. Such a controller would be able to effectively process and display video images and broadcast audio signals without losing the quality or usefulness inherent to the information.

SUMMARY OF THE INVENTION The problems outlined above are in large part solved by the teachings of the present invention. The present invention incorporates a system and method for communication of data between a central processing unit (CPU) and one or more peripheral devices attached to a peripheral bus. The system comprises a CPU coupled to a system or memory bus. The system bus in turn couples to a peripheral bus through a bus bridge. One or more peripheral devices are coupled to the peripheral bus. The present invention comprises one or more memory buffers coupled to the CPU which stores peripheral and/or multimedia data transferred to or from the one or more peripheral devices.

Data to and from the peripheral device is stored temporarily in a first-in-first-out (FIFO) buffer. Both the CPU and peripheral device receive interrupt signals when retrieval of the data from the FIFO buffer is preferred. The retrieving device then obtains the stored data from the FIFO buffer.

In one embodiment, the memory buffer includes separate transmit and receive buffers. Data from the CPU is first stored in the transmit FIFO buffer, and once the transmit FIFO buffer becomes sufficiently full. the peripheral device requests control over the peripheral bus to retrieve data from the FIFO buffer. The peripheral bus writes data to the receive FIFO buffer via the peripheral bus and bus bridge for subsequent retrieval by the CPU.

In another embodiment-data stored in the respective transmit and receive buffers is transferred directly to/from the peripheral devices. There data stored in the transmit FIFO buffer is read by the peripheral or multimedia devices without passing through the bus bridge and peripheral bus. Data written into the receive FIFO buffer also is

communicated directly between the peripheral device and FIFO buffer without passing through the peripheral bus and bus bridge.

The FIFO buffer produces interrupt signals which reflect the amount of the FIFO buffer currently in use for storing data. These interrupt signals are used by the CPU and the peripheral device as an indication of when to retrieve data from the FIFO buffers. Instead of using interrupts to indicate when the FIFO buffer contains data to be retrieved for processing, the CPU may monitor the level of data in the FIFO. In response, the CPU may adjust the effective processing rate so as to ensure the FIFO maintains an optimal level of data. Finally, the CPU may adjust the clock rate of the FIFO buffer to maintain an optimal data level.

BRIEF DESCRIPTION OF THE DRAWINGS Other objects and advantages of the invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings in which: Fig. 1 is a block diagram representation of a typical prior art computer system.

Fig. 2 is an exemplary block diagram of the parallel implementation of the preferred embodiment.

Fig. 3A is a block diagram of the receive FIFO contained in the parallel implementation.

Fig. 3B is a block diagram of the transmit FIFO contained in the parallel implementation.

Fig. 4 is an exemplary block diagram of the serial data implementation of the preferred embodiment.

Fig. SA is a block diagram of the receive FIFO contained in the serial implementation.

Fig. 5B is a block diagram of the transmit FIFO contained in the serial implementation.

Figs. GAX, D are exemplary block diagrams including registers for correcting mismatched data rates.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood. however. that the drawing and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary. the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present invention as defined by the appended claims.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to Fig. 2. a multimedia data controller is shown consistent with the preferred embodiment. A central processing unit (CPU) core 100 is coupled to an LI cache system 150 and bus I/O device 160 over a CPU local bus 80. Also attached to the CPU local bus is a transmit first-in-first-out buffer (TX FIFO) 300 and receive FIFO buffer (RX FIFO) 200 according to the present invention. A parallel bus structure 175 couples the RX and TX FIFOs

to the bus 1/O 160. Preferably. these components are integrated into a single processor chip. as indicated by the dashed box 20.

The bus I/O 160 connects the CPU local bus 80 to a system bus or memory bus 110. A memory control unit 120 also couples to the system bus 110. The memory control unit 120 couples to a memory device 130 which preferably includes dynamic random access memory (DRAM). L2 cache 70 couples to the memory control unit 120 and to the system bus 110.

A bus bridge 170 provides connectivity between the system bus 110 and a peripheral bus 180. External devices 19 and multimedia devices 190 couple to the peripheral bus 180. The peripheral bus 180 preferably comprises a PCI (Peripheral Component Interconnect) bus, but may comprise other bus types such those complying with the ISA and EISA standards. Thus. the peripheral bus 180 is not limited to any particular bus architecture.

Multimedia device 190 represents such media devices as graphics/video cars or systems, audio cards or systems.

MPEG decoders/encoders. CD ROM systems. video cassette recorders, video cameras, and the like. Data to and from the peripheral devices 19 and multimedia device 190 may flow along the path including the CPU core 100. CPU local bus 80, bus I/O 160. system bus 110, bus bridge 170. peripheral bus 180. and peripheral device 19 or multimedia device 190. Data may flow in either direction-from the CPU core to the peripheral device and vice versa. Data may also be stored in and retrieved from the memory subsystem comprising the memory controller 120 and memory device 130. Thus. data from the multimedia device 190 may be provided to the memory 130, and the CPU 100 reads from the memory to obtain the data.

According to the present invention. data from the multimedia device 190 may flow over the peripheral bus 180. through the bus bridge 170 to the system bus 110, through the bus I/O 160. and over the bus structure 175 to the RX FIFO 200. Once in the RX FIFO 200, the CPU retrieves the data over CPU local bus 80. Data to be transmitted to the multimedia device from the CPU core flows over the CPU local bus 80 to the TX FIFO 300. Subsequently. the multimedia device retrieves the data from the TX FIFO 300 via the bus structure 175, bus I/O 160, system bus 110. bus bridge 170. and peripheral bus 180.

The RX and TX FIFOs appear to the CPU 100 as if they are L I cache units. For example, the FIFO's have me same access rights as cache memory and generally are as fast as or faster than cache memory. Accesses to the FIFO's thus is faster than DRAM memory accesses with little of the latency problems inherent to DRAM memory accesses. In other words. FIFO accesses by the CPU 100 are similar to cache hits. and thus have reduced latency compared to main memory accesses.

Multimedia devices typically have real time processing requirements and data rates. This is generally not true for other tasks handled by the CPU. Processing rate also varies among different multimedia devices. Differences in these real time dependencies make data communication problematic. For example, data in the FIFO buffers may be ovenvritten if the CPU stores data in the buffer faster than the multimedia device can retrieve it. Thus in one embodiment the processor is programmed with the isochronous rate of the multimedia device. Synchronizing processing rates between the CPU and the multimedia device efficiently enables data to be written into a FIFO buffer at the same rate the data is retrieved. Thus, valid data in the buffers will not be ovenvritten. This approach. however. places generally unacceptable limitations on the operating system and is further limited because the data rate may change for a multimedia device during different modes of operation and certainly different multimedia devices have different data rates. Accordingly, the preferred embodiment includes several ways to overcome this problem including the use of interrupt signals, adjusting in real-time the effective data rate of the CPU. and adjusting the clock rate of the FIFO buffers.

The embodiment including interrupt signals will now be described. Referring now to Figs. 2. 3A. and 3B. the RX FIFO 200 and TX FIFO 300 preferably contain logic circuitry to generate interrupt signals. In Fig. 3A. an

embodiment of the RX FIFO 200 is shown. As shown, the RX FIFO 200 includes a FIFO buffer 202 and a logic circuit 204. The FIFO buffer 202 is coupled to the CPU local bus 80 and the bus structure 175. Logic circuit 204 generates a plurality of signals shown collectively as signal 205. These signals preferably represent interrupt signals which are either received by the system interrupt controller or provided to a pin. such as the NMI pin, of the CPU core 100 as described below. The logic circuit 204 generates one or more of the interrupt signals in response to the excess capacity signal 203. Excess capacity signal 203 monitors the excess storage capacity of the FIFO buffer 202 to indicate the amount of the FIFO buffer available for storage of new data. Specifically, excess capacity signal 203 indicates whether only one memory position in FIFO buffer 202 contains valid data. whether the FIFO buffer is half- full of data. whether the FIFO buffer is completely full of data. or whether some other number of memory locations contains valid data. This predetermined number of locations may be programmable or fixed (i. e., hardWired).

Based on the status of excess capacity signal 203, logic circuit 204 generates an appropriate interrupt.

Interrupt signal 210 is generated when the excess capacity signal 203 indicates only one position in the FIFO buffer 202 contains valid data. Interrupt signal 220 is generated when the signal 203 indicates that one-half of the FIFO's memory locations are full. Interrupt signal 230 is generated when the excess capacity signal indicates all of the FIFO is full of data. Finally. interrupt signal 240 is generated upon a predetermined number of locations in FIFO buffer 202 becoming full.

Similarly. in Fig. 3B. logic circuit 304 generates a plurality of signals shown collectively as signal 305.

These signals preferably represent interrupt signals which are either received by the system interrupt controller or provided to a pin. such as the NMI pin. of the CPU core 100. The CPU core first fills the FIFO buffer 302. The multimedia device then begins retrieving the data from the buffer. Buffer level signal 303 indicates the amount of data stored in the buffer that has yet to be retrieved by the multimedia device. Based on the status of buffer level signal 303, logic circuit 304 generates one or more of the interrupt signals 310,320.330, and 340. Interrupt signal 310 is generated when the buffer level signal 303 indicates only one position in the FIFO buffer 302 contains valid data ; that is, all but one memory positions of the buffer have been retrieved by the multimedia device. Interrupt signal 320 is generated when the buffer level signal 303 indicates that one-half of the FIFO's memory have yet to be read by the multimedia device. Finally, interrupt signal 330 is generated when the multimedia device has retrieved enough data from the buffer so that only a predetermined number of memory locations in the buffer have yet to be retrieved.

Moreover. once the multimedia device has retrieved enough data from the FIFO buffer so as to create one of these buffer level conditions. the corresponding interrupt is generated and used by the CPU 100 as an indication of when to store more data in the buffer.

One or more of the interrupt signals may be used in a given implementation. For example, the system designer may desire to implement interrupt signal 220 to trigger the CPU core 100 to retrieve data from the receive FIFO buffer 202 once the buffer becomes half-full of data from the multimedia device. The data can be retrieved and processed while the buffer is filling up with new data. On the transmit side. interrupt signal 310 may be implemented exclusievely to indicate to the CPU core when the multimedia device has retrieved all but one memory positions. thereby signaling the CPU to store new data in the TX FIFO. Factors such as the data rate. type of data and processing power of the CPU relative to the multimedia device influence the designer's choice of interrupt protocol.

The operation of the present invention will now be described with reference to the preferred embodiment shown in Figs. 2, 3A. and 3B. Multimedia data communication generally is bi-directional-from the multimedia device 190 to the CPU core 100. and vice versa. When the multimedia device contains data to be processed by the CPU, the multimedia device requests control of the peripheral bus 180 from the bus bridge 170. According to predetermined and commonly known bus control schemes, the bus bridge 170 grants control of the peripheral bus to the multimedia device 190. The multimedia device then places its data (including address. data, and control bits) on

the peripheral bus and the bus bridge then transmits that data to the RX FIFO 200 via the system bus 110. bus I/O 160. and bus structure 175. The multimedia data preferably comprises addresses which are mapped to the RX FIFO 200 In Fig. 3A. the multimedia data received on bus structure 175 from the system bus 110 is stored in FIFO buffer 202. When the FIFO buffer reaches some preferred level of capacity (i. e. * only 1 position filled. half filled, completely filled, or X number of positions filled as described above), excess capacity signal 203 signals the logic circuit 204 of this capacity condition. In response, the logic circuit generates the corresponding interrupt signal 305 which is received by the CPU core 100. This interrupt signal triggers the CPU to retrieve multimedia data from the RX FIFO 200 over the CPU local 80.

Figs. 2 and 3B illustrate the preferred embodiment for communicating data from the CPU core 100 to the multimedia device 190 and follows a similar scheme to that for multimedia device-to-CPU communication described above. The CPU core 100 begins filling the TX FIFO buffer 302 with data targeted for the multimedia device. The multimedia device retrieves some or all of the data from the buffer through the bus 1/O 160. system bus 110. bus bridge 170 and peripheral bus 180. When the level of data in the buffer drops to a predetermined level. buffer level signal 303 directs the logic circuit 304 to generate an interrupt signal reflective of the buffer's data level (i. e., only 1 position filled, half filled. or X number of positions filled). This interrupt signal is received preferably by the CPU core 100 indicating a need for the CPU core to write more data to the transmit FIFO buffer 304.

In an alternative embodiment as shown in Figs. 4, SA, and SB. multimedia data may be communicated between multimedia device 190 and CPU core 100 through an RX FIFO 400 and TX FIFO 500 without passing through the bus I/O, system bus, and bus bridge 170. This architecture is beneficial when the data to an from the multimedia device constitutes a serial stream of data, and not parallel as in the embodiment described above.

Serial data from the multimedia device can be written directly into the RX FIFO 400 over signal line 192 and ultimately retrieved by CPU core 100 via the CPU local bus 80. Data from the CPU core 100 can be written into the TX FIFO 500 and retrieved by the multimedia device 190 over serial signal line 194.

The parallel nature of the CPU local bus 80 necessitates the conversion of serial multimedia data received over signal line 192 to parallel form. Further. parallel data from the CPU core to be transmitted to the multimedia device 190 must be converted to serial form for transmission over serial signal line 194. The RX FIFO 400 and TX FIFO 500 preferably incorporate logic to convert data between serial and parallel forms. Parallel-to-serial and serial- to-parallel conversion blocks are shown in Fig. SA and 5B.

In Fig. 5A serial-to-parallel converter 401 converts serial data received from multimedia device 190 over signal line 192. The data is then placed on a bus 406. From this point on. the RX FIFO 400 performs identically to RX FIFO 200 with data being read from the FIFO buffer 402 over the CPU local bus 80. Excess capacity signal 403 is similar to excess capacity signal 203 in Fig. 3A. Specifically, signal 403 reflects the excess capacity level of the FIFO buffer 402. Logic circuit 404 uses excess capacity signal 403 to generate one or more of the interrupts 410. 420, 430. and 440 shown collectively as signal 405. The interrupt signals are used by the CPU core 100 to indicate when to retrieve data from the FIFO buffer. Interrupt signal 410 represents the condition in which only one FIFO buffer position contains data. Signal 420 represents the condition in which the buffer is half-full. Signals 420 represents the condition in which the buffer completely full. Finally, signal 440 represents the condition when X positions contain data.

In Fig. 5B TX FIFO 500 performs identically to TX FIFO 300 except that the parallel data read from a FIFO buffer 502 is placed on a parallel bus 507 and converted to a serial stream of data by parallel-to-serial converter 506.

Parallel-to-serial converter 506. in turn. outputs the serial data stream on line 194 for transmission to the multimedia

device 190. The functions of buffer level signal 503 and interrupt signal 505 comprising signals 510. 520, and 530 correspond to buffer signal 303 and interrupt signals 305 in Fig. 3B.

Figs. 6A-6D show an alternative to the embodiment of Figs. 3A. 3B. 5A. and 5B in which registers are used instead of interrupt signals to overcome the problems of mismatched data rates, thereby ensuring the efficient flow of data between the CPU core 100 and multimedia device 190. When using a register instead of interrupt signals. the CPU writes to and reads from the FIFO buffers at a predetermined nominal rate approximating the multimedia data rate.

In Fig. 6A, the RX FIFO's logic circuit 204 periodically updates a register 250 to indicate how full the FIFO buffer 202 is with data from the multimedia device. For example. the logic circuit 204 may store in the register a number indicating the percentage of the total buffer space free for the multimedia device to store more data.

Alternatively, the number stored in the register might reflect the percentage of the buffer space presently containing data to be read by the CPU. In either case. the register provides a way for the CPU to infer how full the buffer has become so that the CPU can adjust its effective data rate if necessary. For instance, if it is desired for the CPU to retrieve data from the RX FIFO so that the buffer never becomes more than 50% full and if the register 250. in fact. indicates the buffer is 70% full. the CPU will increase temporarily its effective data retrieval rate. A faster effective rate can be achieved either by retrieving the same quantity of data more often than the nominal rate or retrieving less data at the same rate. Alternatively, if the buffer is only 5% full. it may be desired for the CPU to slow down its effective retrieval rate to let the multimedia device 190 temporarily fill the buffer faster than the CPU 100 retrieves the data. Slower effective retrieval rates are achieved either by reading the same quantity of data less often than the nominal rate or reading more data at the same nominal ratu.

Fig. 6B exemplifies the TX FIFO using a register 350 instead of interrupts. The CPU 100 writes data to the TX FIFO buffer 302 at a nominal rate approximating the isochronous rate of the multimedia device. To prevent the CPU 100 from overwriting data in the FIFO buffer when the multimedia does not retrieve data as fast as the CPU stores data in the buffer. the CPU periodically checks the status of register 350. Register 350 is updated by logic circuit 304 to reflect the level of data in the FIFO buffer. From the status of register 350, the CPU core 100 can determine how much of the data has been retrieved by the multimedia device 190 and thus. whether the multimedia device is able to retrieve data from the FIFO buffer at the same rate at which the CPU stores data. If. for example. register 350 indicates the FIFO buffer is almost filled, the CPU can use that information to slow down its effective rate of storing data in the buffer. Slowing the effective rate is accomplished similar to that described above for slowing the retrieval rate with respect to the RX FIFO. That is, the CPU core 100 can store the same quantity of data less often than the nominal rate or storing more data at the nominal rate. The function of registers 450 in Fig. 6C and 550 in Fig. 6D parallels that of registers 250 and 350. respectively, for the serial embodiment of the present invention.

An alternative embodiment to the use of interrupt signals or changing the effective data rate of the CPU is to dynamically change the TX or RX FIFO clock rate as needed to output more or less data depending on the amount of data stored in the FIFO.

Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.