Title:
MULTIPROCESSOR SYSTEM
Document Type and Number:
WIPO Patent Application WO/2008/062511
Kind Code:
A1
Abstract:
A processor element (PE0) transmits a command to a processor element (PE1) via an
inter-PE communication path. If a status response received from the processor element
(PE1) shows an abnormal state, the processor element (PE0) transmits a state
check command to a processor element (PE2) via an inter-PE communication path.
When the communication between the processor element (PE0) and the processor element
(PE2) is successful, it is determined that the receiving circuit of the processor
element (PE1) is out of order. When the communication between the processor element
(PE0) and the processor element (PE2) is failed, it is determined that the transmitting
circuit of the processor element (PE0) is out of order.
Inventors:
TAKAHASHI HIROMASA (JP)
CHIBA TAKASHI (JP)
KAMIJO SHUNSUKE (JP)
CHIBA TAKASHI (JP)
KAMIJO SHUNSUKE (JP)
Application Number:
PCT/JP2006/323168
Publication Date:
May 29, 2008
Filing Date:
November 21, 2006
Export Citation:
Assignee:
FUJITSU LTD (JP)
TAKAHASHI HIROMASA (JP)
CHIBA TAKASHI (JP)
KAMIJO SHUNSUKE (JP)
TAKAHASHI HIROMASA (JP)
CHIBA TAKASHI (JP)
KAMIJO SHUNSUKE (JP)
International Classes:
G06F11/22; G06F13/00
Foreign References:
| JPH10133963A | 1998-05-22 | |||
| JP2002118564A | 2002-04-19 | |||
| JP2001195377A | 2001-07-19 |
Attorney, Agent or Firm:
OSUGA, Yoshiyuki (Nibancho Bldg.8-20, Nibancho, Chiyoda-ku, Tokyo 84, JP)
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