NEURAL NETWORK COMPUTATION CIRCUIT USING SEMICONDUCTOR STORAGE ELEMENT, AND OPERATION METHOD

WIPO Patent Application WO/2019/049686

A1

A combining weight coefficient used in neural network computation is stored in a memory array (20), a word line (22) corresponding to the input data of a neural network is driven by a word line drive circuit (24), and a bit line to which is connected a combining weight coefficient to be computed by a column selection circuit (25) is connected to a computation circuit (26), with a sum total of cell currents flowing in the bit line (23) determined by the computation circuit (26). The determination result of the computation circuit (26) is preserved in an output-holding circuit (27), and is set to the word line drive circuit (24) as input to a neural network of the next layer. A control circuit (29) indicates, on the basis of information held in a network configuration information-holding circuit (28), to the word line drive circuit (24) and the column selection circuit (25) that the word line (22) and the bit line (23) used in neural network computation be selected.

HAYATA YURIKO
KOUNO KAZUYUKI
NAKAYAMA MASAYOSHI
MOCHIDA REIJI
ONO TAKASHI
SUWA HITOSHI

PCT/JP2018/031298

March 14, 2019

August 24, 2018

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PANASONIC CORP (JP)

G06N3/063; G06G7/60; G11C11/54

JPH0628331A	1994-02-04
US5371834A	1994-12-06
JPH0454685A	1992-02-21
JPH05282269A	1993-10-29
JP2015534172W

M. PREZIOSO ET AL.: "Training and operation of an integrated neuromorphic network based on metal-oxide memristors", NATURE, vol. 521, 2015, pages 61 - 64, XP055568356, DOI: 10.1038/nature14441
See also references of EP 3680824A4

NII, Hiromori et al. (JP)

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