BACKGROUND OF THE INVENTION

Field of the Invention

This invention relates to low noise solid-y≤ta preamplifier circuits and, more particularly, to a twa-**-sta integrated circuit amplifier having a three-phase doub auto-zeroing switching sequence which enables cancellation offsets , charge injection, kT/C noise and low frequen flicker noise . The circuit, which is particularly useful computerized tomography applications , also moderates therm noise by employing a filtering method that is merged with t overall frequency compensation of the preamplifier .

Description of the Prior Art

In computerized tomography (CT) , X-ray signals ar detected using an array of photodiodes mounted directl behind scintillators . The resolvable dynamic range of th signal to be detected is on the order of one million to one i . e . , 120 dB, due to the range of X-ray attenuat io encountered in the human body . Economic and syste architectural advantages arise from the ability to completel integrate the preamplifier and subsequent analog-to-digita converter (ADC) together for several CT channels on a singl complementary metal oxide semiconductor (CMOS) monolithi integrated circuit ( IC) . However, the noise properties an power supply levels of CMOS have heretofore limited th dynamic range of any signal conditioning function to roughl 95 dB . Therefore, it would be desirable to achieve 120 d dynamic range and corresponding linearity in a CMO photodetector preamplifier circuit .

Prior implementations of CT preamplifiers have utiliz discrete components, including low-noise junction fie effect transistor (JFET) input bipolar operation amplifiers, to achieve the desirable wide dynamic ran While a low-noise fully integrated CMOS preamplifier for has not before been implemented, some CMOS instrumentat amplifiers display certain similarities thereto; howeve their basic functions are different. Examples of these C instrumentation amplifiers are presented, for example, R.D. Yen and P.R. Gray in "A MOS Switched-Capacit Instrumentation Amplifier", TEEE J. Sot id-state circ it Vol. SC-17, Dec. 1982, pp. 1008-1013; D.J. Allstot in Precision Variable-Supply CMOS Comparator", IEEE j. Sol state Circuits, Vol. SC-17, Dec. 1982, pp. 1080-10 B.S. Song and P.R. Gray in "A Precision Curvature-Compensa CMOS Bandgap Reference", IEEE J. Solid-State Cirαύf.f., V SC-18, Dec. 1983, pp. 634-643; and B.S. Song, M.F. Tomps and K.R. Lakshmikumar in "A 12-Bit 1-Msample/s Capaci Error-Averaging Pipelined A/D Convertor"" , IEEE _T. Sol State Circuits, Vol. 23, Dec. 1988, pp. 1324-1333. circuits disclosed in these journal articles addr amplification of voltage-mode signals, whereas photodetector preamplifier must amplify current -mode signal

SUMMARY OF THE INVENTION

It is therefore an object of the present invention provide apparatus to interface low level current-m signals, such as provided by a photodetector, corresponding voltage-mode signals providing a dynamic ra on the order 120 dB.

Another object of the invention is to provide preamplifier circuit which can be implemented in C technology to allow for complete integration of the

interface function, including analog-to-digital conversi of several channels on a single integrated circuit.

Briefly, in accordance with a preferred embodiment the invention, a low-noise CMOS circuit is provided to acc a current signal input and produce an output voltage aft integration of the signal. A key property of the circuit its ability to cancel the low frequency noise that typically encountered when using MOS transistors. T specific MOS transistor nonidealities that arise inclu transistor flicker and thermal noise, charge injectio voltage offset, device mismatch, and nonlinearity. T preamplifier circuit according to the invention functions cancel low-frequency noise through use of correlated-doub sampling (CDS) , and to limit high frequency noise through u of low-pass filtering.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other objects, aspects and advantag will be better understood from the following detail description of a preferred embodiment of the invention wi reference to the drawings, in which:

Figure 1 is a schematic diagram of the basic low-noi preamplifier circuit according to the invention; Figure 2 is a timing diagram showing the related clo waveforms for the circuit shown in Figure 1;

Figures 3A, 3B and 3C are simplified schematic diagra of the basic preampl- "ier circuit shown in Figure 1 showin respectively, the operations of auto-zeroing the fir amplifier stage, auto-zeroing the second amplifier stage a integrating the input current signal;

Figure 4 is a schematic diagram showirg the low-noi preamplifier accorα n« to the invention, witn noise limiti internal frequency compensation; and

Figure 5 is a schematic diagram showing a single-en version of the low-noise preamplifier circuit according the invention.

DETAILED DESCRIPTION OF PREFERRED

EMBODIMENTS OF THE INVENTION

Figure 1 illustrates the basic circuit of the low-no preamplifier of the invention, which comprises a balanc two-state, capacitively coupled integrator that canc offset and charge injection almost completely through use a specific auto-zeroing switching sequence. The first st comprises an operational amplifier 11 having inverting non-inverting inputs connected, respectively, to in terminals 12 and 13. The operational amplifier, which ha gain of Ai, provides complementary voltage output signals therefore is hereinafter referred to a having a double-en (or balanced) output. The output of a photodiode 9 coupled to the inverting input of amplifier 11 via in terminal 12, and a reference current source (not shown) be coupled to the non-inverting input of amplifier 11 input terminal 13. The reference current source may be u to provide dark current correction or, alternatively, ^" it be omitted. As another alternative, the opposite polar output terminal of photodiode 9 may be coupled to the inverting input of operational amplifier 11 via in terminal 13 (as indicated in Figure 4) to act as a dou ended input for amplifier 11.

The double-ended outputs of operational amplifier 11 cross-coupled via interstage coupling capacitors 14 and having capacitance values Cz _r to the inverting and inverting inputs of a second operational amplifier 16, w is substantially identical to the first operati amplifier 11 but having a gain of A2 • The double-e outputs of second amplifier 16 are coupled via a low-

noise limiting filter 17 to the preamplifier outp terminals 18 and 19 to provide an output voltage.

A first feedback path is provided by a capacitor 21 fr the positive side of low-pass filter 17 to the inverti input of operational amplifier 11. A second feedback path provided by a capacitor 22 from the negative side of low-pa filter 17 to the non-inverting input of operation amplifier 11. The feedback capacitors have capacitan values of Ci . These feedback paths provide the integrati function of the preamplifier.

The circuit includes a number of CMOS switch pairs whi are controlled by various clock phases shown in Figure The first of these CMOS switches are field effect transisto (FETs) 23 and 24 which are respectively coupled between t positive output and inverting input, and the negative outp and the non-inverting input, of operational amplifier 1 This pair of FETs is turned on by clock phase φi during ti interval Δi, as shown in Figure 2. The next pair of CM switch pairs is made up of FETs 25 and 26 which a respectively coupled between the positive output a inverting input and the negative output and non-inverti input of operational amplifier 16. This pair of FETs turned on by clock phase Φ ₁₂ during time intervals Δi and Δ as shown in Figure 2. Another pair of FETs 27 and 28 a respectively coupled between the positive output of low-pa filter 17 and feedback capacitor 21, and the negative outp of low-pass filter 17 and feedback capacitor 22. FETs and 28 are turned on by clock phase Φ3 during interval Δ

The final switch pair is made up of FETs 29 and 31 which a respectively coupled between the junction of FET 27 a feedback capacitor 21 and circuit ground, and between t junction of FET 28 and feedback capacitor 22 and circu ground. FETs 29 and 31 are turned on by clock phase Φ during time interval Δi and Δ2, as shown in Figure 2. Ti

interval Δ2 represents the time period after clock phase but before the end of clock phase Φ ₁₂ .

The switching pattern defined by the clock phases sho in ^" Figure 2 comprises two auto-zeroing phases f amplifiers 11 and 16, respectively, followed by integration phase for processing the input current signa The operation of these phases is illustrated in Figures 3 3B and 3C, respectively. During interval Δi, F switches 23, 24 and 25, 26 are closed so that bo amplifiers 11 and 16 are auto-zeroed, making their inpu referred offset and noise voltages appear at their respecti outputs. FET switches 29 and 31 are also closed at th time, while FET switches 27 and 28 are open. This conditi is illustrated in Figure 3A. At the end of interval Δi, F switches 23 and 24 open, as indicated in Figure 3B, and t noise and offset of amplifier 11 are sampled by capacitors and 22 and are amplified during interval Δ2 by the gain amplifier 11. This amplified error voltage signal is appli to the left-hand sides of capacitors 14 and 15 while the right-hand sides continue to be held at the offset and noi level of amplifier 16. At the end of interval Δ switches 25 and 26 open and the amplified error volta signal is sampled by amplifier 16 across capacitors and 15. Then at the start of time interval Δ ₃ , the righ hand sides of capacitors 21 and 22 are switched from grou (0 volts) to the outputs of amplifier 16 as shown Figure 3C, but the output signal of the preamplifier remai at 0 volts irrespective of all the noise, offset and swit charge injection. The only residual offset at this time the charge injection and noise from the opening switches 25 and 26 sampled onto interstage coupli capacitors 14 and 15. This error, however, is reduced by factor Ai, corresponding to the gain of amplifier 11, w input-referred, so that it can be made negligibly small using sufficient gain in the first stage of the preamplifie

Interval Δ3 is the time interval in which the curre signal is actually integrated. During this integrati interval, input-referred noise of amplifier 11 displaces t output signal with a noise gain of 1/β where &-C _\ / <Cι+C _s where C ₃ is the shunt capacitance of the photodiode, and th amplified noise can be sampled by a subsequent stag Therefore, to reduce the output noise level, low-pa filter 17 is included in the loop as shown in Figure 1 limit the bandwidth of any broad-band thermal noise. It c be shown that the output RMS noise voltage under th circumstance is

Where ε is the input-referred thermal noise power spectr density in vol ts per iHz and ωx is the unity gain bandwid of amplifier 11 cascaded with amplifier 16 and the low-pa filter 17, in radians per second. An effective way implement this _. filtering and also provide frequen compensation of the cascade of amplifiers is shown Figure 4 wherein capacitors 32 and 33 of capacitance value are added to compensate the preamplifier during phase Φ3 usi a pole-splitting technique. The compensation capacitor value is increased by the Miller effect by an amount A2+ where A2 is the gain of amplifier 16, thus forming a domina low-frequency pole at the output of amplifier 11. (T Miller effect is based on Miller's network theorem described, for example, in A.S. Sedra and K.S. Smith, "Micr Electronic Circuits", Holt. Rinehart and Winston. 1982, N York, N.Y., pp 41-43.) The added capacitors 32 and 33 al move the pole formed by capacitive loading at the output amplifier 16 to a high frequency to ensure stability. this connection, the closed loop unity gain bandwidth radians per second is

ω _τ ^" - βύ - βSϋi- , ₍ 2 )

2C _C

where g is the transconductance of amplifier 11. ml For this circuit, the output noise can be determined the case of the thermal noise of the input different

MOSFET pair 23, 24 of amplifier 11. The thermal noise po spectral density (PSD) of a MOS transistor is

ι ² - .kτ V ² /Hz

L3gs,J (3! where k is Boltzmann's constant and T is temperature in In the present case, amplifier 11 has a transconductance m _l and the output noise variance is computed as

<Jno - 2 ^χ -%kτ

I3 « β ² 4 3βCc _{( 4 )}

and the RMS thermal noise is

σ _no - 2VL

V 3βCc (5 )

Interestingly, this noise does not directly depend amplifiers 11 and 16; rather, it is dependent on compensation capacitor size and the feedback factor β. As example to illustrate typical noise levels, if C _c = 200 ci » 75 pF and C _s - 300 pF, then using Equation (5) the out RMS noise voltage is σ _no -» 8.3 μv. Depending upon availability of complement photodetector output signals, a single-ended circuit may desirable. For this case, the preamplifier shown in Figur can be used. In this circuit, amplifiers 11' and 16' similar to amplifiers 11 and 16 except that they provid single-ended output rather than a double-ended output . output signal of amplifier 11' is inverted by invert amplifier 34 (having a gain of 1) before being applied interstage coupling capacitor 14. Since this circuit empl

a single-ended input and provides a single-ended output, on one switch is required as a replacement, respectively, f each pair of switches shown in Figure 1; otherwise, operati of'the circuit is essentially unchanged. In summary, the preamplifier circuit according to t invention provides for virtually complete cancellation offsets and charge injection, rejects flicker noise as p conventional correlated double sampling, and controls therm noise via band-limiting incorporated into the frequen compensation.

While only certain preferred features of the inventi have been illustrated and described herein, ma modifications and changes will occur to those skilled in t art. It is, therefore, to be understood that the append claims are intended to cover all such modifications a changes as fall within the true spirit of the invention.