NON-INTEGER DIVISION OF FREQUENCY Background of Invention [0001] As the operating frequencies of modern computers continue to increase, power consumption by such computers increases accordingly. The relationship between power consumption and frequency is given in Equation 1.

P = CV2t (1) In Equation 1, P represents power, C represents capacitance, V represents voltage, and f represents frequency. It is evident from Equation 1 that as f increases, P increases proportionally.

[0002] However, sometimes, increased power consumption may not be desirable or feasible at all parts of a computer system due to one or more system constraints, testing purposes, or performance concerns. For example, when power consumption is increased, temperature accordingly increases, and this may lead to diminished reliability. Further, due to increased power consumption at certain parts of the computer system, the supply of power at other parts of the computer system may be adversely affected. Thus, in order to avoid such problems caused by increased power consumption, frequency at particular parts of the computer system is decreased, i. e.,"divided down. " Figures la and lb show a typical prior art approach to dividing down a frequency of a signal.

[0003] Specifically, Figure la shows a frequency divider (10) that is formed by a positive edge-triggered D-Q flip-flop (also referred to as"D-Q flip-flop") (12) and a delay stage (14), which is formed by an inverter (16). An input signal, CLKIN, serves as an input to a clock input of the D-Q flip-flop (12).

A Q output of the D-Q flip-flop (12), via FLIP FLOP OUT, serves as an input to the delay stage (14), which, in turn, outputs to both a D input of the D- Q flip-flop (12) and an output, CLKOUT, of the frequency divider (10).

[0004] Figure lb shows a timing diagram (20) of the frequency divider (10) shown in Figure la. If the D input to the D-Q flip-flop (12) is initially logic high, i. e.,'1,'when a first positive edge, i. e. , a first"rising"edge, on CLK IN (22) triggers the D-Q flip-flop (12), the D-Q flip-flop outputs logic high on FLIP FLOP OUT (24). The logic high on FLIP FLOP OUT (24) is inputted by the delay stage (14), which, in turn, inverts the logic high on FLIP FLOP OUT (24) and outputs logic low, i. e.,'0,'on CLK OUT (26).

The logic low outputted by the delay stage (14) also propagates to the D input of the D-Q flip-flop (12) to ready the D-Q flip-flop (12) for the next time it is triggered.

[0005] A next rising edge on CLK_IN (28) triggers the D-Q flip-flop (12) causing the D-Q flip-flop (12) to output logic low on FLIP FLOP OUT (30) due to the logic low at the D input of the D-Q flip-flop (12). The logic low on FLIP FLOP OUT (30) is inputted by the delay stage (14), which, in turn, inverts the logic low on FLIP FLOP OUT (30) and outputs logic high on CLKOUT (32). The logic high outputted by the delay stage (14) also propagates to the D input of the D-Q flip-flop (12) to ready the D-Q flip-flop (12) for the next time it is triggered.

[0006] The description of the timing diagram (20) of Figure lb shows that the frequency of CLKOUT is one-half that of CLKIN. In other words, the frequency of CLKOUT is equal to the frequency of CLK IN divided by two.

Essentially, the frequency divider (10) of Figure la and other prior art frequency dividers generate an output signal by counting the number of cycle of an input signal. For example, the frequency divider (10) of Figure la generates one cycle on an output signal for every two cycles on an input signal.

Furthermore, the capability of most frequency dividers can be extended to allow the generation of multiple output signal frequencies, where the multiple output signal frequencies are generated by dividing down an input signal's frequency by particular integer values.

[0007] Figure 2a shows a typical prior art frequency divider (40) that is capable of generating multiple output signal frequencies. Specifically, Figure 2a shows a frequency divider (40) that is formed by four negative edge-triggered J-K flip-flops (also individually referred to as"J-K flip-flop") (42,44, 46, 48). The J and K inputs to the four J-K flip-flops (42,44, 46, 48) are tied to logic high, and thus, every time a negative edge, i. e. , a"falling"edge, arrives at a clock input of one of the four J-K flip-flops (42,44, 46, 48), the value stored inside that J-K flip-flop is inverted. The Q outputs of the first, second, and third J-K flip-flops (42,44, 46) are connected to the clock inputs of the second, third, and fourth J-K flip-flops (44,46, 48), respectively. Further, the signals from the Q outputs of the first, second, and third J-K flip-flops (42,44, 46) are represented by Co, Cl, and C2, respectively. The clock input of the first J-K flip-flop (42) is connected to an input signal, CLK, and the signal from the Q output of the fourth J-K flip-flop (48) is represented by C3.

[0008] Figure 2b shows a timing diagram (50) of the frequency divider (40) shown in Figure 2a. Initially, the four J-K flip-flops (42,44, 46,48) store a logic low. At a first falling edge of CLK (52), the clock input of the first J-K flip-flop (42) is pulsed and the value stored in the first J-K flip-flop (42) goes from logic low to logic high, which results in logic high to go from the Q output of the first J-K flip-flop (42) to the clock input of the second J-K flip- flop (44). Moreover, this logic high at the Q output of the first J-K flip-flop (42) causes Co to go high (54). Thus, the first falling edge (52) at the clock input of the first J-K flip-flop (42) causes Co to go high (54). However, the logic high on Co (54) does not affect the value stored in the second J-K flip- flop (44) because the second J-K flip-flop (44) can only be triggered by a falling edge at its clock input.

[0009] At a second falling edge of CLK (56), the clock input of the first J-K flip-flop (42) is pulsed and the value stored in the first J-K flip-flop (42) goes from logic high to logic low, which results in logic low to go from the Q output of the first J-K flip-flop (42) to the clock input of the second J-K flip-flop (44).

Moreover, this logic low at the Q output of the first J-K flip-flop (42) causes Co to go low (58) and triggers the second J-K flip-flop (44). Thus, because Co goes high (54) at a first falling edge of CLK (52) and Co goes low (58) at a second falling edge of CLK (56), Co's frequency is one-half of CLK's frequency. In other words, the frequency divider (40) can generate a signal that has a frequency equal to that of a clock signal's frequency divided by two.

[0010] Because the second J-K flip-flop (44) is triggered by the falling edge on Co (58), the value stored in the second J-K flip-flop (44) goes from logic low to logic high, which results in logic high to go from the Q output of the second J- K flip-flop (44) to the clock input of the third J-K flip-flop (46). Moreover, this logic high at the Q output of the second J-K flip-flop (44) causes C1 to go high (60). Thus, the second falling edge (56) at the clock input of the first J-K flip-flop (42) causes Co to go low (58), which, in turn, triggers the second J-K flip-flop (44) and causes C1 to go high (60). However, the rising edge on Ci (60) does not affect the value stored in the third J-K flip-flop (46) because the third J-K flip-flop (46) can only be triggered by a falling edge at its clock input.

[0011] At a fourth falling edge of CLK (62), the clock input of the first J-K flip-flop (42) is pulsed and the value stored in the first J-K flip-flop (42) goes from logic high to logic low, which results in logic low to go from the Q output of the first J-K flip-flop (42) to the clock input of the second J-K flip-flop (44).

Moreover, this logic low at the Q output of the first J-K flip-flop (42) causes Co to go low (64) and triggers the second J-K flip-flop (44).

[0012] Because the second J-K flip-flop (44) is triggered by the falling edge on Co (64), the value stored in the second J-K flip-flop (44) goes from logic high to logic low, which results in logic low to go from the Q output of the second J- K flip-flop (44) to the clock input of the third J-K flip-flop (46). Moreover, this logic low at the Q output of the second J-K flip-flop (44) causes C1 to go low (66). Thus, the fourth falling edge (62) at the clock input of the first J-K flip-flop (42) causes Co to go low (64), which, in turn, triggers the second J-K flip-flop (44) and causes C1 to go low (66). Furthermore, because C1 goes high (60) at a second falling edge of CLK (56) and Ci goes low (66) at a fourth falling edge of CLK (62), Ci's frequency is one-fourth of CLK's frequency.

In other words, the frequency divider (40) can generate a signal that has a frequency equal to that of a clock signal's frequency divided by four.

[0013] Because Ci goes low (66), the third J-K flip-flop (46) is triggered and the value stored in the third J-K flip-flop (46) goes from logic low to logic high, which results in logic high to go from the Q output of the third J-K flip- flop (46) to the clock input of the fourth J-K flip-flop (48). Moreover, this logic high at the Q output of the third J-K flip-flop (46) causes 2 to go high (68). Thus, the fourth falling edge (62) at the clock input of the first J-K flip- flop (42) causes Co to go low (64), which, in turn, causes Ci to go low (66), which, in turn, causes 2 to go high (68). However, the rising edge onc2 (68) does not affect the value stored in the third J-K flip-flop (46) because the third J-K flip-flop (46) can only be triggered by a falling edge at its clock input.

[0014] Those skilled in the art will understand that because the first J-K flip- flop (42) is pulsed at every falling edge of CLK and the second J-K flip-flop (44) is pulsed at every second falling edge of CLK, it follows that the third J-K flip-flop (46) is pulsed at every fourth falling edge of CLK and the fourth J-K flip-flop (48) is pulsed at every eighth falling edge of CLK. For instance, an eighth falling edge of CLK (70) causes Co to go low (72), which, in turn, causes Ci to go low (74), which, in turn, causes C2 to go low (76), which, in turn, causes C3 to go high (78). Therefore, as shown in Figure 2b, if CLK's frequency is represented by f, then the frequency of Co isf/2, the frequency of Ci isf/4, the frequency of C2 isf/8, and the frequency of C3 is f/16.

[0015] Based on Equation 1 given above, frequency and power consumption are directly related, and thus, the dividing down off by a particular integer value automatically results in the dividing down of P by that particular integer value. Similar to the frequency divider (10) shown in Figure la, the frequency divider (40) shown in Figure 2a essentially generates divided down signals by counting the number of cycles of an original signal.

[0016] However, although various situations require that power consumption be decreased, dividing down an original frequency by an integer value may result in performance degradation in cases where peak performance occurs at a frequency value that is not equal to the original frequency divided by any integer value.

Summary of Invention [0017] In one aspect, a frequency divider that is capable of dividing down a frequency of a signal by a non-integer value comprises a phase counter stage that counts phases of the signal, where the phase counter stage generates a signal edge when a certain number of phases have been counted, and where an output signal of the frequency divider is generated dependent on the signal edge generated by the phase counter stage.

[0018] In another aspect, a method for dividing down a frequency of a signal by a non-integer value comprises counting phases of the signal, where a phase counter stage generates a signal edge when a certain number of phases have been counted, and generating an output signal dependent on the signal edge generated by the phase counter stage.

[0019] Other aspects and advantages of the invention will be apparent from the following description and the appended claims.

Brief Description of Drawings [0020] Figure 1 a shows a typical prior art frequency divider.

[0021] Figure lb shows a timing diagram for the frequency divider shown in Figure la.

[0022] Figure 2a shows a typical prior art frequency divider.

[0023] Figure 2b shows a timing diagram for the frequency divider shown in Figure 2a.

[0024] Figure 3a shows a frequency divider in accordance with an embodiment of the present invention.

[0025] Figure 3b shows a timing diagram in accordance with the embodiment shown in Figure 3a.

Detailed Description [0026] The present invention relates to a method and apparatus for a frequency divider that is capable of non-integer frequency division. More particularly, the present invention relates to a method and apparatus for a frequency divider that performs non-integer frequency division by counting phases of an input signal.

[0027] Figure 3a shows a frequency divider (80) in accordance with an exemplary embodiment of the present invention. The frequency divider (80) includes a phase counter stage (82), a flip-flop stage (84), a delay stage (86), and a duty cycle corrector stage (88). An input signal, CLKIN, serves as an input to the phase counter stage (82). The phase counter stage (82) outputs to a clock input of the flip-flop stage (84). The flip-flop stage (84), which has a data input connected to logic high, i. e.,'1,'outputs to both the delay stage (86) and the duty cycle corrector stage (88). The delay stage (86) outputs to a reset input of the flip-flop stage (84), and the duty cycle corrector stage (88) outputs an output signal, CLK OUT, of the frequency divider (80).

[0028] For purposes of the description below with reference to Figure 3b, the signal generated by the phase counter stage (82) is represented as PHASE COUNT OUT, the signal generated by the flip-flop stage (84) is represented as FLIP FLOP OUT, and the signal generated by the delay stage (86) is represented as DELAY OUT [0029] Those skilled in the art will appreciate that the flip-flop stage (84) may be formed using a D-Q flip-flop, a J-K flip-flop, or another type of edge- triggered flip-flop. Further, those skilled in the art will appreciate that in other embodiments, the data input of the flip-flop stage (84) may be connected to logic low, i. e.,'0.' [0030] Figure 3b shows an exemplary timing diagram (90) in accordance with the embodiment shown in Figure 3a. Particularly, Figure 3b shows timing waveforms for CLKIN, PHASECOUNTOUT, FLIPFLOPOUT, DELAY OUT, and CLKOUT when the frequency divider (80) generates a signal on CLKOUT that has a frequency equal to that of the frequency of CLKIN divided by 1.5.

[0031] CLK IN is shown in Figure 3b as a pulsing clock signal having a frequency off. In order to divide down CLK IN by 1.5, the phase counter stage (82) counts the phases of CLKIN and outputs a rising edge on PHASE COUNT OUT (92) at a third phase of CLKIN (94). The rising edge on PHASE COUNT OUT (92) triggers the flip-flop stage (84), which, in turn, outputs logic high on FLIP FLOP OUT (96) due to its data input being tied to logic high.

[0032] The logic high on FLIP FLOP OUT (96) is fed into the delay stage (86), which, after some delay (shown in Figure 3b), outputs logic high on DELAY OUT (98), where the logic high on DELAY OUT (98) resets the flip-flop stage (84) causing the flip-flop stage (84) to output logic low on FLIP FLOP OUT (100).

[0033] At a next third phase of CLKIN (102), the phase counter stage (82) outputs another rising edge on PHASE COUNT OUT (104), where the rising edge on PHASE COUNT OUT (104) causes the flip-flop stage (84) to output high on FLIP FLOP OUT (106), where after the process described above (96, 98, 100) is repeated. During the process described above with reference to Figure 3b, the duty cycle corrector stage (88) continuously corrects the duty cycle of FLIP FLOP OUT according to system requirements and outputs CLK OUT. Moreover, those skilled in the art will understand that CLK OUT can be directly or indirectly dependent on the generation of a signal edge by the phase counter stage (82).

[0034] Those skilled in the art will appreciate that the process described above repeats itself for every third phase of CLK IN. This leads to the frequency of CLKOUT being equal tof/1. 5, wherefis the frequency of CLK IN.

[0035] Moreover, those skilled in the art will appreciate that in other embodiments the frequency divider (80) may be used to divide down CLK IN by other non-integer values, such as 2.5, in which case, the phase counter stage (82) would output a rising edge on PHASE COUNT OUT for every fifth phase of CLK IN. Further, those skilled in the art will appreciate that the delay stage (86) may contain control logic or be programmable so that the delay amount can be automated based on the amount that CLKIN is divided down by. In other embodiments, those skilled in the art will appreciate that the phase counter stage (82) may be programmable such that the amount that CLKIN is divided down can be automatically selected without user intervention.

[0036] Further, those skilled in the art will appreciate that the duty cycle corrector stage (88) may not be necessary in certain embodiments depending on system requirements. Additionally, those skilled in the art will appreciate that in other embodiments, the present invention is capable of dividing down a signal by integer values as well as non-integer values.

[0037] Advantages of the present invention may include one or more of the following. In some embodiments, because a frequency divider counts phases of an input signal instead of cycles of the input signal, the frequency divider may generate an output signal that has a frequency equal to that of the input signal divided by a non-integer value.

[0038] In some embodiments, because a frequency divider can divide down an original signal's frequency by a non-integer value, performance may be improved in cases where higher performance occurs at frequency values that are non-integer factors of the original signal's frequency.

[0039] In some embodiments, because a frequency divider can divide down an original signal's frequency by a non-integer value, performance may be improved in cases where higher performance occurs at power consumption values that are related to frequency values that are non-integer dividends of the original signal's frequency.

[0040] In some embodiments, because a phase counter stage of a frequency divider is programmable, the frequency divider may be capable of dividing down a signal's frequency by various non-integer values.

[0041] In some embodiments, because a phase counter stage of a frequency divider is programmable, the frequency divider may be capable of dividing down a signal's frequency by integer values as well as by non-integer values.

[0042] In some embodiments, because a phase counter stage of a frequency divider is programmable, the amount that the frequency divider divides down an original signal's frequency may be automatically selected without user intervention.

[0043] In some embodiments, because a delay stage of a frequency divider is programmable, the amount of delay generated by the delay stage may be dependent on the amount that the frequency divider divides down an original signal.

[0044] While the invention has been described with respect to a limited number of embodiments, those skilled in the art, having benefit of this disclosure, will appreciate that other embodiments can be devised which do not depart from the scope of the invention as disclosed herein. Accordingly, the scope of the invention should be limited only by the attached claims.