The present invention concerns a non- volatile memory device comprising a carrier substrate and a plurality of memory cells, wherein each memory cell contains a memory material in the form of an electrically polarizable material, in particular an electret or ferroelectric material exhibiting hysteresis, wherein said memory cell is a capacitor-like structure with a pair of electrodes contacting directly or indirectly a volume of said memory material, said pair of electrodes when electrically connected to electronic control circuits being capable of subjecting said memory material to an electric field as well as detecting a polarization response thereto in said memory material, in order to effect write- and/or read- and/or erase operations in said cell.

Electret- or ferroelectric-based solid-state memories have several advantages compared to many other current memory technologies. One important advantage is that the information is non- volatile, i.e. that the ferroelectric polarization and thus the stored data are not lost when the power is turned off. Other advantages include a wide choice of architectures and geometries, some of which provide very high data densities.

Relevant architectures can be classified as either active or passive. In the former case, each memory cell storing a bit contains one or more active elements (transistors) for cell selection during writing, reading and erasing operations. In the latter case, memory cells are capacitor- like structures that are electrically accessed without requiring an active element associated exclusively with each cell. This may be achieved by cells arranged in a passive crosspoint matrix, with cell selection being performed by applying potentials to the matrix lines in a coordinated fashion.

Ferroelectric memories of the active type, termed FeRAMs, are commercially available and are sold in chip sizes up to at least 256 kbit. Test modules exist up to at least 64 Mbit. The conventional layout of such prior art active ferroelectric memory cells is shown in some detail in fig. Ia where the switching transistor and capacitor are juxtaposed, and in fig. Ib, where the capacitor is stacked atop the transistor to save real estate. Fig 2 shows an example of a physical arrangement for the embodiment of fig. Ib, wherein a

tungsten plug forms a via connection between the transistor and capacitor, and where SBT is used for memory material (cf. below).

Two of the most serious drawbacks of conventional FeRAM are the high cost and the comparatively low packing density. Stacked solutions for higher density are being developed but add further to the complexity. The memory materials in these devices are inorganic ferroelectrics, e.g. PZT (Pb(Zr ₅ Ti)O ₃ ), SBT (layered perovskite, SrBi ₂ Ta ₂ O ₉ ). A wide range of problems exist relating to the materials aspects of manufacturing and operation of FeRAMs, which contribute to complexity and cost. Much effort has gone into solving these problems, cf., e.g. Ramesh, "Materials Science and Engineering", Vol. 32, pp. 191-236 (2001); Schwartz, "Chemical Solution Deposition of Perovskite Thin Films", Chem. Mater., Vol. 9, pp. 2325-2340 (1997); Celinska et al, Appl. Phys. Lett. Vol. 82, pp.3937-3939 (2003); Angus I. Kingon et. Sudarsan Srinivasan, "Lead zirconate titanate thin films directly on copper electrodes for ferroelectric, dielectric and piezoelectric applications", Nature Materials Vol. 4, pp. 233-237 (2005); and European patent application EP 1 492 124 A2, titled "Three dimensional ferroelectric memory device" (Stipe Barry Suching, assigned to Hitachi).

Summing up, the semiconductor industry has a set path towards higher FeRAM capacity. The general concept is stacked lT/lC-cells, with oxygen barriers to protect the plugs and the CMOS circuits, and hydrogen barriers to protect the FE material. In addition, 3D-structures are foreseen as necessary when cell dimensions shrink, in order to get enough polarization. These structures are built with either pillar-shaped or hole-shaped bottom electrodes, whose sides and top/bottom are covered first with the FE material, and then with the top electrode. Conformal deposition of FE material is mandatory to achieve uniform thickness, and MOCVD is the dominating deposition technique. As is apparent from the literature, conventional FeRAM state of the art is still beset by numerous issues relating to complex and space-consuming architectures, as well as materials that require critical processing procedures and ancillary materials for satisfactory manufacturing and operation.

Turning now to state of the art passive electret- or ferroelectric-based memories, the traditional basic cell structure is very simple as shown in fig. 3, with the memory material 2 being sandwiched between a pair of planar

electrodes Ia, Ib in a capacitor-like configuration. Addressing is typically achieved by a matrix structure of crossed sets of parallel electrodes in a so- called passive matrix addressing configuration. These types of architectures provide high data density and can be realized by simple manufacturing processes, since few manufacturing steps are involved. Furthermore, the memory material 2 can be applied globally on top of the bottom electrode 1 a (BE), e.g. by spin coating, before the top electrode Ib (TE) is applied on top of the memory film. As has been shown by the present applicant in e.g. International published application WO02/05287, the well-known problems adhering to passive matrix addressing such as sneak currents and disturb of non-addressed cells can be adequately overcome for most applications by judicious attention to device design and electrical drive protocols. It has been demonstrated that such devices can be made with polymers as memory materials, providing opportunities for manufacturing memory devices in low- temperature processes compatible with all-organic electronics.

Unfortunately, there are certain drawbacks adhering to passive electret- or ferroelectric-based memories also. When a subset of electrodes in the addressing matrix is activated electrically in connection with write-, read-, or erase operations, so-called "sneak currents" may flow in non-addressed electrodes in the matrix, obscuring the results. Also, non-addressed cells may experience disturbing electrical signals which in certain cases can lead to change in polarization and thus corruption of the logic content of the memory cells. In addition to the sneak current and disturb issues which impose limits on design and performance, there are materials-related problems intimately linked to the basic capacitor architecture referred above, where a top and a bottom electrode form a sandwich with the memory material between them. When the top electrode is applied on top of the memory material, the electrode/memory material interface may suffer damage or may become undesirably modified. This is particularly critical in the usual case where the memory material thickness shall be as small as possible, particularly where polymer ferroelectric materials with high coercive fields are involved.

Thus, a primary object of the present invention is to provide a new generation of electret- or ferroelectric- based data storage devices and methods for manufacturing and operating same, whereby the advantages of the prior art such as simplicity, speed and data density of traditional passive ferroelectric memory cells are retained, but where fundamental problems mentioned

above, namely of process-related damage to the memory material or interfaces can be reduced or eliminated.

This primary object of the present invention is realized with a non- volatile memory device which is characterized in that pairs of electrodes are arranged in an array of one or more dimensions, and that the plurality of memory cells are formed with pairwise combinations of adjacent array electrodes such that the memory cells likewise become arranged in a corresponding array with each memory cell defined in memory material provided in or adjacent to a spacing between the electrodes of pairs provided on the carrier substrate, whereby an electric field generated by applying a potential between the electrodes of a pair extends substantially parallel to said carrier substrate, such that the memory material of the memory cell when subjected to said electric field becomes polarized in a direction along an axis of the electric field, or responds to said electric field as applied with a change in the direction or value of an already therein set polarization.

In a preferred embodiment of the present invention the electrodes are arranged in rows and columns of a two-dimensional array, and in an equally preferred embodiment thereof each array electrode is provided as a pillar-like structure extending above the carrier substrate or integrated therein. Similarly, also then the pillar-like array electrodes are arranged in rows and columns of a two-dimensional array, with the memory material advantageously provided between opposite surfaces of adjacent pillar-like array electrodes

Further features and advantages shall be apparent from the remaining dependent claims.

Now the present invention shall be discussed in more detail by way of exemplary embodiment and the appended drawing figures, of which figs. Ia and Ib show electrical schematics of prior art FeRAM cells with the IT/ 1C (one transistor, one capacitor per cell) architecture, as mentioned above, fig. 2 shows geometric structure of prior art FeRAM cells with the IT/ 1C (one transistor, one capacitor per cell) architecture, as mentioned above,

fig. 3 the prior art "vertical" capacitor-like structure for a single memory cell, as mentioned above, figs. 4a and 4b show two variants of a cell structure according to the present invention, fig. 5 shows another variant of a cell structure according to the present invention, figs. 6a and 6b show a side view and a top view, respectively, of a two- dimensional array of lateral memory cells formed between arrayed electrodes on a surface, fig. 7 shows a portion of a quadratic array of memory cells being read by a full row/column read voltage protocol, fig. 8 a portion of a quadratic array of memory cells being written by a full row/column read voltage protocol, whereby half of the cells are over- written in the process, fig. 9 shows a portion of a quadratic array of memory cells being read by a full row/column read voltage protocol where only a portion of the electrodes in the matrix array are at a non-zero voltage, fig. 10 a write/read operation on a single cell in a quadratic array, where electrode voltages are controlled in a coordinated fashion, exposing non- addressed cells in both x- and y-directions to electrical fields of E/3 or less, fig. 11 a variant of the write/read operation shown in fig. 10 with a different set of electrode potentials, fig. 12 a portion of a quadratic array of memory cells where each electrode is shaped so as to avoid spurious diagonal switching fields in excess of E/3, fig. 13a and 13 b show a top and a side view, respectively, of an array of memory cells that can be addressed by a passive matrix scheme, fig. 14 shows a portion of a passive matrix built according to the architecture shown in figs. 13a, 13b, subjected to a voltage protocol that limits electrical fields in non-selected cells to disturbing fields of E/3 or less, and

fig. 15 a portion of a passive matrix built according to the architecture shown in figs. 13a, 13b, subjected to a voltage protocol that provides parallel readout of data from a full row of memory cells in the matrix.

The basic premise of the present invention is that the electrodes that define the capacitor-like memory cell are formed on or in a carrier surface or substrate in such a way that the electric field between them which polarizes and interrogates the memory material is directed predominantly in a direction parallel to the supporting surface. This is illustrated schematically with the aid of figs. 4a, 4b and 5. For reference, fig. 3 shows the prior art conventional "vertical" capacitor-like structure, where the memory material 2 is sandwiched between a bottom electrode Ia on the supporting surface and a top electrode Ib that has been deposited on top of the memory material. When a potential difference is applied between the two electrodes, an electrical field is set up in the memory material, pointing in a direction essentially perpendicular to the surface.

Figures 4a, 4b and 5 show variants of cell structures according to the present invention, termed "lateral" cells below and the background of this concept which is not entirely unknown in the prior art, shall now briefly be discussed in order to elucidate structural and operational aspects of the memory device according to the present invention.

In the first place JP publication 2002/299572A discloses the structure of a straight-forward lateral memory cell. Herein memory material in the form of ferroelectric film is sandwiched between a first and second electrode provided perpendicularly to the surface of a Si substrate. Since the faces of the electrodes sandwiching the ferroelectric memory material are perpendicular to the substrate and the direction of the polarization is parallel with the plane of the substrate, the element area is not increased even if the sandwiching face is increased. As well-known to persons skilled in the art the capacitance of a capacitor shall be dependent on the area of the dielectric between the capacitor plates, i.e. the electrodes. On the other hand it is also inversely proportional to the distance between the electrodes, so to some extent the advantages gained with this lateral memory cell structure would depend on the design rule, i.e. how small the separation between the vertical electrodes can be made.

Further a mix of lateral and vertical memory cell geometries has been exploited in published International patent application No. WO03/046995 (assigned to the present applicant) and wherein bit line electrodes are provided in parallel recesses formed in the crossing word lines and covered with memory material before electrode material for bit lines are deposited in the recesses. This allows for a ferroelectric memory cell with allows for ferroelectric e.g. ferroelectric memory cells with both vertical and lateral switching direction and a substantially increased memory cell area and hence charges storage capacity. Finally, published International patent application No. WO03/052762

(assigned to the present applicant) discloses a data storage apparatus which exploits the piezoelectric properties of a soft ferroelectric of electret memory material. Also this apparatus employs a first set of parallel electrodes wherein recesses extending crosswise have been formed, but then provided with an electrode pair or twin electrodes and surrounded by memory material provided in the recesses and between the twin electrodes and the vertical recess surfaces of the orthogonally crossing first set of electrodes, such that memory cells are formed in the memory material and with a lateral polarization direction, i.e. either parallel to the substrate or bottom of the recesses or with the extension of the first set of electrodes.

As will be seen from the above, use and exploitation of lateral polarizing fields or switching directions, referring e.g. to the substrate as been exploited for variety of purposes, but no attempt has ever been made to employ the principle in two-dimensional arrays wherein vertical electrodes are used and a memory cell with the lateral polarization directions are formed by providing the memory material substantially between the electrode structures such that memory cells are formed between adjacent pairs of electrodes in any direction.

In fig. 4a, two near-planar low aspect ratio or "flat" electrodes are located side by side on a surface, with a film of memory material filling the gap between them and being subjected to an electrical field with predominant components parallel to the surface. In fig. 4b, two near-planar electrodes and an inert dielectric filling the gap between the electrodes present a smooth surface supporting a layer of memory material. A further variant, closely similar to that shown in fig. 4b but not shown here, consists of two electrodes

embedded into the substrate with the top of the electrodes flush with the substrate surface. Depending on the actual geometries in question, the memory material may in all these cases be subjected to field components in a direction perpendicular to the surface also, but always in the same field pattern within the memory material volume. In fig. 5, two higher aspect ratio, or "pillar" electrodes extend above the carrier substrate, with the volume between them being partly or completely filled with memory material. In this case, the electrical field set up in the memory material can be almost exclusively in a direction parallel to the supporting surface, and it is possible to make a memory cell with a small gap between electrodes without making the volume of memory material too small (a small gap is required if low operating voltages are desired).

The conventional vertical configuration differs from the lateral ones in several respects. A very significant advantage of the lateral cell structures compared to the vertical ones is that deposition of a top electrode onto the memory material is avoided. This removes a major source of problems that can arise due to damage or undesired modification of the memory film during the top electrode deposition step. Furthermore, short circuits through pinholes in the memory film are a moot point with lateral cell structures, whereas they can pose major problems in vertical cell structures employing ultrathin memory films. More generally, lateral structures lend themselves to manufacturing procedures whereby incorporation of the memory material into the device structures takes place in processing steps that follow after and are well separated from those where the electronic circuitry, including electrodes defining the memory cells, are formed. This allows traditional processing technologies to be employed in traditional silicon fabs, combined with back-processing that includes application of memory material and packaging, e.g. at separate fabrication facilities in case there exist any cross- contamination issues. In addition to the advantages of allowing such back- processing, the task of developing viable materials and processes is simplified significantly when it is no longer necessary to apply top electrodes on memory materials.

In cases where it is desirable to achieve high areal data storage density, lateral cell structures can be arranged in dense two-dimensional arrays as illustrated in figs. 6a and 6b. In this example is shown a quadratic two- dimensional array of lateral memory cells formed between individually

addressable pillar electrodes that extend upwards from the CMOS substrate (see illustration below). Using e.g. sol-gel deposition, it is possible to fill the volume between the electrodes with an inorganic ferroelectric material such as PZT. By applying an appropriate voltage across two neighbour electrodes, the FE-material between them can be laterally switched, thus creating a lateral memory cell. Independent memory cells can be created both in the "x" and "y" direction, depending on which electrodes are used.

Of course, in some applications and for architectural reasons, the memory cells can also be arranged in a one-dimensional or linear array such that the entire memory device would be a row of memory cells.

In order to perform write/read/erase operations in an arrayed geometry like the one illustrated in fig. 6b, the electrodes on each side of each addressed cell must be given electrical potential differences that set up the appropriate electrical field in the memory material between the electrodes. As is readily apparent, even with individually controllable potentials on each electrode in the array, disturbing voltages may appear across non-addressed cells in the vicinity of a given addressed cell unless electrode potentials on several adjacent electrodes are controlled in a coordinated fashion. All this would be fairly familiar to persons skilled in the art of ferroelectric memory technology.

In most cases involving memory materials of relevance in the present context, disturbing of neighbour cells during a read or write operation is avoided if no more than 1/3 of the electric field required for switching the polarization is applied over any of the cells that are not to be read/written. In the case of reading operations, it is in principle possible to avoid any disturbing fields whatsoever across non-addressed cells by means of a so- called "full row (or column) read" protocol as illustrated in fig. 7. In this case, all the electrodes to the left of the (vertical) line to be read are pulsed with the same potential V (Volts), whereas the electrodes to the right are held at zero potential. As a result, only the column to be read sees an electric field.

Analogously, full row write is possible with the constraint that the information in one direction (e.g. y) is destroyed when full rows are written in the other direction (e.g. x), as seen in the example shown in fig. 8. The

difference compared to full row read is that each cell, which is written, may have a different polarity compared to the neighbour cell, as indicated by the "-E" in the vertical column of indicated E-field strengths in the figure. To maintain zero field in all "x" cells not to be written, the "y" cells have to be sacrificed, as visualized in the figure by the horizontal rows of indicated E- field values "E" and "-E" in "y" cells.

An alternate way of doing full row read is shown in fig. 9. The basic concept is the same, but the potential of the electrodes to the right and left (only right shown) of the cells to be written is gradually decreased from V/2 to V/4 to 0, creating small E/4 disturb fields in the closest cells. The advantage is that most electrodes in a large array now can be kept at zero potential.

As shall now be illustrated with reference to an example shown in fig. 10, it is possible to perform single cell read or write, as well as operation of cells in both x- and y-directions, without disturbing neighbouring cells with fields higher than E/3 (where E is the field required to switch the cell). This is achieved by applying voltages to 12 electrodes simultaneously in a particular pattern as indicated in the figure. In this case, a total of 31 cells are subjected to non-switching electric fields by the switching of one cell. In addition, four regions (indicated by a question mark) not associated with any specific memory cell are subjected to electric fields that may be somewhat higher than E/3, but which depend explicitly on the local geometry. The possible detrimental effect of these regions must be assessed in each separate case. Electrodes not designated with any voltage are assumed to be at zero potential. The same pattern of electric potentials can be applied to several groups of electrodes simultaneously in a large matrix array for obtaining parallel read/write operations. Potentials would then be applied in multiple isolated clusters rather than in single rows or columns.

Since it is the potential differences between the electrodes in the matrix that define the fields in the cells, a large (in principle infinite) number of different electrode patterns can be selected that would be functionally equivalent to that shown in fig. 10. One example is shown in fig. 11. In this case, one electrode is given a negative polarity, i.e. a potential level below the zero potential applied to electrodes contacting non-addressed cells outside the cluster surrounding the addressed cell shown.

As mentioned above, the field patterns between the electrodes shall depend on the local geometry, and may to a large extent be controlled by the shape of the electrodes. This may be used to minimize detrimental effects of stray or fringe fields or to enhance field strengths in selected regions. In fig. 12 is shown an example where the electrodes shown in figs. 7-11 are modified so as to diminish the possible disturb fields associated with the regions marked by question marks in figures 10 and 11.

In order to facilitate addressability and the control of disturb fields, the two-dimensional arrangement of electrodes, as well as the shapes of the electrodes themselves, may be selected in a number of different ways. An example is given below in conjunction with so-called passive matrix addressing, where a rectangular rather than a quadratic electrode arrangement is chosen in order to bring disturb fields in non-addressed cells below a prescribed limit. Other arrangements are possible, e.g. where the electrodes are centered on a hexagonal or a trigonal lattice.

A particularly advantageous variant of an addressing scheme in arrayed memories according to the present invention shall now be described. As is well known in the case of traditional vertical type memory cell structures, passive matrix addressing arrays combine a very high cell density with a simple electronic driving and detection architectures and manufacturing methods. Also, the passive matrix scheme can be adapted for electronic circuitry and memory cells embedded in the same chip, or for devices where the memory cell part is separated from the electronic driver and detection circuitry. As shall be shown below, it is possible to achieve these advantages in a lateral cell matrix also, provided an appropriate device architecture and voltage protocol is used.

An example of an architecture for lateral cell structures addressed by a passive matrix arrangement is shown in figures 13a and 13b. The memory cells are formed in the spaces between a set of pillar electrodes arranged in a matrix. Every second electrode in each given column of electrodes is connected to a common conducting rail (a "column rail") embedded in the substrate underneath that column. In each column of electrodes, the remaining electrodes are connected to a set of parallel conducting rails ("row rails") embedded in a higher stratum of the substrate and oriented perpendicular to the column rails as shown. A layer of insulator ensures that

short-circuits between the column and row rails is avoided and also provides distance between the memory cells and the embedded rails. By applying different potentials between column and row rails, it becomes possible to apply electrical fields to the memory material in selected volume elements between the pillar electrodes, for performing write, read and erase operations. Electrical connections to the column and row rails can conveniently be achieved through connections at the edges of the matrix structure.

In analogy with the conventional passive matrix addressing schemes, it is possible to apply coordinated electrical drive pulses to the column and row rails in such a way that only a single or a set of selected memory cells are subjected to switching fields, whereas the non-selected cells at most experience disturb fields of E/3, where E is the field used for switching the polarization in selected cells. For most memory materials of relevance, it is considered sufficient to keep disturb fields below this level in order to operate large memory arrays. A possible pattern of electrode potentials to induce switching in a single selected memory cell in the matrix array is illustrated in fig. 14. The switching field, of magnitude E, is achieved by applying a potential difference of V across a cell gap extending between two nearest neighbour electrodes in a column of pillar electrodes as shown. As can be seen from fig. 14, two volume elements constituting a single memory cell at the crossing point between one column rail held at potential V and one row rail held at potential zero, are subjected to electric fields of magnitude E, whereas all other volume elements in the matrix are exposed to fields E/3 or less. All other column rails are at the same time maintained at potential V/3, and all other row rails are maintained at potential 2V/3 during this addressing operation. In order to keep disturb fields below E/3 in all volume elements both in the row and column directions, the physical distance between row rails are in this case chosen to be twice the distance between column rails. Given the same manufacturing design rule defining minimum electrode widths and spacings, this implies an areal data storage density one third of that achievable with a traditional passive matrix arrangement with vertical capacitor-like cells. On the other hand, the comparative doubling of cell volume can be used in several ways to enhance overall device performance. In further analogy with the conventional passive matrix addressing schemes, it is possible to employ what is commonly referred to as "full row read"

operation in the known art. As is illustrated in fig. 15, all row rails except one are maintained at potential zero, with the one remaining rail which represents the set of selected cells in the matrix, being kept at potential V. At the same time, each column rail is connected to a sense amplifier clamping the each column rail to zero potential. Thus, each cell contiguous to the electrodes that connect to the selected row rail at potential V is subjected to the full switching field E, and the switching charge generated in those cells that experience polarization reversal is sensed by the sense amplifier connected to each column rail. In this way, all cells selected by a single row rail are read out in parallel, and only the selected cells in the matrix array experience an electric field at all. The advantages of zero disturbing fields in non-addressed cells are several, and are well recognized by persons skilled in the art of passive matrix operations.

It is to be understood that the figures show primarily the principles of architectures rather than teaching the true physical embodiments of realistic devices. Thus, it should be pointed out that each memory device needs to be carefully designed with regards to physical dimensions, geometric shapes of electrodes, etc in order to obtain the proper electric field distributions for operating the devices. In many cases, the electric field strength required for switching the memory substance is very high, exceeding typical dielectric strength of many substances, including air. Thus, sharp edges, points or asperities should be avoided, and the top of the electrodes should be embedded in a material of adequate dielectric strength (e.g. the memory substance itself) to avoid spurious arcing between the top of the electrodes selected for addressing a given memory cell.

As noted above, an important attribute of the present invention is the separation of the processes that produce the substrate with conducting lines, electrodes and electronics on the one hand, and the processes for applying the memory substance in the form of an electret or ferroelectric on the other hand. Beneficial aspects that can accrue from this separation include optimization of manufacturing flow (e.g. multiple production sites), and freedom from cross-contamination of production environments. Furthermore, the choice of memory substance becomes much less restricted, permitting the use of both inorganic-based and organic-based memory substances in conjunction with aggressive processes such as implantation, high temperature anneal etc that might be involved in the manufacturing of

the substrate with conductors, electrodes, electronics, etc. Memory substances of relevance encompass an ever-widening range of materials, including several families of ceramic ferroelectrics as mentioned in the introduction, and polymeric ferroelectrics such as PVDF, P(VDF-TrFE), odd nylons, etc. Several of these memory substances, in particular the ferroelectric polymers, decompose or lose their functionality at temperatures well below those required for normal processing of silicon-based electronics, or are damaged during standard electrode-deposition processes required in manufacturing of top electrodes according to prior art ferroelectric memory devices, but this disadvantage can largely be obviated by relying on memory cells with lateral geometries, as disclosed hereinabove.