PRIORITY APPLICATIONS

[0001] The present application claims priority to U.S. Patent Application Serial No. 15/817,441 entitled "NON- VOLATILE (NV) MEMORY (NVM) MATRIX CIRCUITS EMPLOYING NVM MATRIX CIRCUITS FOR PERFORMING MATRIX COMPUTATIONS" and filed on November 20, 2017, which claims priority to U.S. Provisional Patent Application Serial No. 62/531,921 entitled "MATRIX CIRCUITS EMPLOYING NON- VOLATILE (NV) MEMORY CIRCUITS FOR PERFORMING MATRIX COMPUTATIONS" and filed on July 13, 2017, the contents of which are incorporated herein by reference in their entireties.

RELATED APPLICATIONS

[0002] The present application is related to U.S. Provisional Patent Application Serial No. 62/531,924 entitled "MULTI-LEVEL CELL (MLC) MATRIX CIRCUITS EMPLOYING NON-VOLATILE (NV) MLC MEMORY CIRCUITS FOR PERFORMING MATRIX COMPUTATIONS" and filed on July 13, 2017, which is incorporated herein by reference in its entirety.

[0003] The present application is also related to U.S. Patent Application Serial No. 15/817,474 entitled "MULTIPLE (MULTI-) LEVEL CELL (MLC) NON- VOLATILE (NV) MEMORY (NVM) MATRIX CIRCUITS FOR PERFORMING MATRIX COMPUTATIONS WITH MULTI-BIT INPUT VECTORS" and filed on November 20, 2017, which is incorporated herein by reference in its entirety.

BACKGROUND

I. Field of the Disclosure

[0004] The technology of the disclosure relates generally to computerization of biological networks, and more particularly to circuit network implementations of synapse networks to provide matrix multiplication with artificial intelligence (AI) learning. II. Background

[0005] Biological networks are networks that apply to biological systems. For example, the biological circulatory system in a human involves the function of pumping and channeling of blood through blood vessels to the body, the lungs, and the heart. Network representation of intracellular biological networks typically considers molecular components within a cell as nodes and their direct or indirect interactions as links. The recognition of biological networks has motivated the development of various neuromorphic computing systems whose architectures reflect the general organizational principles of nervous systems in an effort to partially reproduce the immense efficiency advantage that biological computation exhibits in some problems. These neuromorphic systems are organized as populations of excitatory and inhibitory spiking neurons (i.e., nerve cells that are specialized cells transmitting nerve impulses) with configurable synaptic connections. Synaptic plasticity plays a crucial role in allowing neural networks to learn and adapt to various input environments. Thus, neuromorphic systems implemented in computer networks need to implement plastic synapses in circuits to obtain basic "cognitive" capabilities such as learning.

[0006] Synapses outnumber neurons by several orders of magnitude in biological neural networks. Reproducing these biological features in neuromorphic electronic circuits presents a scaling problem, as integrating thousands of dedicated synapse circuits per neuron can quickly become infeasible for circuit systems that require a large number of neurons. This scaling problem in computer networks has traditionally been solved by either treating synapses as simple linear elements and time-multiplexing spikes from many pre-synaptic sources onto the same linear circuit, or by treating them as basic binary elements that can be set either on or off externally, without learning abilities. Real synapses, however, exhibit non-linear phenomena like spike timing dependent plasticity (STDP) that modulate the weight of an individual synapse based on the activity of the pre- and post-synaptic neurons. The modulation of synaptic weights through plasticity has been shown to greatly increase the range of computations that neural networks can perform.

[0007] Capturing the plasticity properties of real synapses in analog neuromorphic hardware requires the use of distinct physical circuits/elements for each synapse. In conventional complementary metal oxide semiconductor (CMOS) circuit technology, this can lead to restrictions on scalability. Some potential solutions to the scalability issues in pure CMOS technology involve the use of very large integrated structures or the adoption of deep submicron technologies. For example, microchip CMOS circuit implementations of STDP rules may result in about thirty (30) transistors per plastic synapse, and thus may lead to high costs for their hardware realization. There is, overall, general thinking that STDP is very expensive to implement in conventional CMOS microchips. Scalability restrictions however can be greatly relaxed if one resorts to compact nano-scale circuit elements that can reproduce the plasticity properties of real synapses. One potential candidate for these elements is a memristor. A memristor is an element which behaves somewhat like a non-linear resistor with memory. In the neuromorphic community, memristors are seen as ideal devices for synapse implementations, as they combine three (3) key functions in one device. Memristors are non-linear, passive, two-terminal electrical devices that relate to electrical charge and magnetic flux linkage. A memristor's electrical resistance is not constant, but depends on the history of current that had previously flowed through the device. That is, its present resistance depends on how much electric charge has flowed in what direction through it in the past. Thus, a memristor device remembers its history, which is called its non-volatility property. When the electric power supply is turned off to the memristor, the memristor remembers its most recent resistance until it is turned on again. Memristors can implement biologically realistic synaptic weight updates (i.e., learning), can carry out long-term multi-valued weight storage, and can also communicate weighted pre-synaptic activity to the postsynaptic side, significantly relaxing scalability restrictions.

[0008] STDP can be implemented with just one (1) memristor per synapse if appropriate peripheral signal conditioning neurons are used in hybrid CMOS/memristor realizations. Typically, plasticity in these memristor synapses is evoked by applying specific waveforms to the two (2) terminals of the memristor, with the waveforms aligned to pre-respectively postsynaptic pulses. The correlation of the waveforms across the memristor in turn implements STDP-like plasticity with the form of the STDP curve defined by the applied wave shape. Both hardware and software models of plasticity based on the basic STDP mechanism are typically chosen, primarily for their simplicity. [0009] In this regard, Figure 1A illustrates a matrix network circuit 100 as a crossbar network that includes a way of interconnecting memristors and CMOS circuit neurons for STDP learning. The matrix network circuit 100 includes a first resistive random access memory (RRAM) cross-bar network 102A and a second RRAM crossbar network 102B. Each of the first and second RRAM cross-bar networks 102A, 102B include respective memristors 104A, 104B at respective synaptic junctions 106A, 106B each representing individual synapses. CMOS buffer gates 108A, 108B, 108C represent three (3) layers of neurons, referred to as CMOS circuit neurons 108A, 108B, 108C. Figure IB illustrates a synaptic connection for a post-synaptic CMOS circuit neuron 108 formed by controlling the first and second RRAM cross-bar networks 102A, 102B. The flat side of the CMOS circuit neuron 108 is its input node 110 (i.e., dendrites) and the sharp side of the CMOS circuit neuron 108 is its output node 112 (i.e., axon). The CMOS circuit neuron 108 controls a voltage V _post at its input node 110 and a voltage Vpr _e at its output node 112. When the CMOS circuit neuron 108 is not spiking, it forces a constant voltage at both input and output nodes 110, 112, while collecting through its input node 110 the sum of input synaptic spike currents Ii, I2 coming from the memristors 104A, 104B, which contribute to changing the neuron internal state. When the CMOS circuit neuron 108 spikes, it sets a one-spike waveform at both input and output nodes 110, 112. In this manner, the CMOS circuit neuron 108 sends its output spikes forward as pre-synaptic spikes for the destination synaptic memristors, but also backward to preceding synaptic memristors as post-synaptic spikes.

[0010] Neural networks that employ memristor networks for providing synapses can also be used for other applications that require weighted matrix multiplication computations, such as convolution for example. For example, Figure 2A illustrates a memristor cross-bar synapse matrix 200 with a pre-neuron layer 202 of pre-neuron circuits 204(l)-204(m) and a post-neuron layer 206 of post-neuron circuits 208(1)- 208(n). Synapses can be provided between the pre-neuron circuits 204(l)-204(m) and the post-neuron circuits 208(l)-208(m). It may be desired to sum up the multiplication of the state of each pre-neuron circuit 204(l)-204(m) with the state of each post-neuron circuit 208(l)-208(n) to provide an accelerated weighted sum and weight update. For example, Figure 2B illustrates a memristor cross-bar matrix circuit 212 of the memristor cross-bar synapse matrix 200 in Figure 2A. The memristor cross-bar matrix circuit 212 includes an RRAM cross-bar array circuit 214 with rows Ri-R _m and columns Ci-C _n of memristors 216(l)(l)-216(m)(n) that can form respective synapses 210(1)(1)- 210(m)(n). The memristors 216(l)(l)-216(m)(n) are configured to store a memory state of an m x n matrix. Input voltages V _m may be for a 1 x m input vector. It may be desired to multiply an input vector by the m x n matrix provided by the memristors 216(l)(l)-216(m)(n). The memristors 216(l)(l)-216(m)(n) in each column Ci-C _n of are coupled to each other in parallel. Thus, the conductance of the RRAM cross-bar array circuit 214 represents the weight of the memristor cross-bar matrix circuit 212. The individual sums of the currents Ii-I _n represent the weight (i.e., the conductance) of the selected column Ci-C _n of memristors 216()(l)-216()(n) multiplied by the state of the pre-neuron circuits 204(l)-204(m) represented by the input voltages Vi_V _m . For example, current Ii is the sum of each input voltage Vi_V _m from a pre-neuron circuit 204(l)-204(m) in a selected row Ri-R _m multiplied by the conductance of a respective memristor 216(l)(l)-216(m)(l) when column Ci is selected, according to the formula:

^I J =∑ ^G u - ^v i

i

where:

i = rows Ri-R _m ; and

j = columns Ci-C _n .

[0011] Thus, current Ii is the sum of the conductance of memristor 216(1)(1) times input voltage Vi _, plus the conductance of memristor 216(1)(2) times input voltage V _2i . . . , plus the conductance of memristor 216(l)(m) times input voltage V _m . The weight of the memristor cross-bar matrix circuit 212 (i.e., the conductances of each memristor 216(l)(l)-216(m)(n)) is updated to provide training based on output voltages of each of the post-neuron circuits 208(l)-208(n) applied backward to preceding input voltages Vi- V _m of the pre-neuron circuits 204(l)-204(m).

[0012] The memristor cross-bar matrix circuit 212 in Figure 2B has a sneak path current issue. Sneak path current is current that flows from an addressed row Ri-R _m to and adjacent row Ri-R _m - For example, assume that column Ci in the cross-bar synapse weight matrix circuit 214 is selected. A current flows in column Ci not only through selected memristors 216(l)(l)-216(m)(l) in column Ci to post-neuron circuit 208(1), but a sneak current also flows back into pre-neuron circuit 204(1). It may not be possible to distinguish the sneak-eurrent leading to an incorrect updating of the weight of the memristor cross-bar matrix circuit 212. Further, RRAM technologies, such as memristors, may not have highly repeatable resistances leading to retention issues that can cause incorrect calculations. Endurance of RRAM technologies may also be limited.

SUMMARY OF THE DISCLOSURE

[0013] Aspects disclosed in the detailed description include non-volatile (NV) memory (NVM) matrix circuits employing NVM matrix circuits for performing matrix computations. In exemplary aspects disclosed herein, an NVM matrix circuit is provided that has a plurality of NVM storage string circuits each comprising a plurality of NVM bit cell circuits organized in respective memory rows and each configured to store a memory state. For example, the NVM matrix circuit may form an m x n NVM matrix circuit, where 'm' represents the number of memory rows of NVM storage string circuits provided, and 'n' represents the number of NVM bit cell circuits within each NVM storage string circuit provided in respective memory columns. A plurality of bit lines are provided and each configured to be coupled to a respective NVM storage string circuit. A plurality of source lines are provided and each configured to be coupled to a respective NVM storage string circuit. Each NVM bit cell circuit has a stored memory state represented by a resistance, and includes a transistor whose gate node is coupled to a word line among a plurality of word lines configured to receive an input vector of 1 x m size for example. Activation of the gate of a given NVM bit cell circuit controls whether its resistance is contributed to a respective source line. For example, the input vector could be a pre-synapse weight vector for example. Each source line is coupled to a respective output node wherein the source lines for all the NVM storage string circuits can collectively provide an output vector. The output vector may be a post-synapse vector for example. To multiply an input vector of 1 x m size times the m x n memory matrix circuit formed by the plurality of NVM storage string circuits, a line voltage is applied to the bit lines of the NVM storage string circuits while input voltages representing an input vector are applied to gate nodes of the NVM bit cell circuits of the NVM storage string circuits. This causes a summation current to be generated on each source line based on the weighted summed contribution of each NVM bit cell circuit' s resistance to its respective source line. Each output line forms an output vector, which is the result of the 1 x m input vector times one (1) column n of the m x n NVM matrix circuit. By the NVM bit cell circuits of the NVM storage string circuits including a transistor coupled to a word line that controls the resistance presented on its respective source line, a cross-bar connection between the word lines and the bit lines does not have to be provided which avoids creating sneak path currents in the NVM matrix circuit. The word lines and the bit lines are isolated from each other through the NVM bit cell circuits.

[0014] In this regard, in one aspect, an NVM matrix circuit is provided. The NVM matrix circuit comprises a plurality of word lines configured to receive an input vector represented by an input voltage on each word line among the plurality of word lines. The NVM matrix circuit also comprises a plurality of bit lines and a plurality of source lines. Each bit line among the plurality of bit lines is configured to receive a corresponding line voltage. The NVM matrix circuit further comprises a plurality of NVM storage string circuits, each configured to be electrically coupled between a corresponding bit line among the plurality of bit lines and a corresponding source line among the plurality of source lines each comprising a plurality of NVM bit cell circuits. Each NVM bit cell circuit among the plurality of NVM bit cell circuits has a resistance representing a stored memory state in the NVM bit cell circuit to form a data vector for the corresponding NVM storage string circuit. Each NVM bit cell circuit among the plurality of NVM bit cell circuits in the NVM storage string circuit comprises a gate node coupled to a corresponding word line among the plurality of word lines. Each NVM bit cell circuit is configured to couple its resistance to the source line in response to the input voltage applied to the corresponding word line coupled to the gate node. The NVM matrix circuit further comprises a plurality of access transistors. Each access transistor is coupled to a corresponding bit line among the plurality of bit lines and a corresponding NVM storage string circuit among the plurality of NVM storage string circuits coupled to the source line corresponding to the bit line. Each access transistor comprises an access gate node coupled to an access line, and is configured to electrically couple the corresponding bit line to the corresponding NVM storage string circuit in the response to an access voltage applied to the access gate node.

[0015] In another aspect, an NVM matrix circuit is provided. The NVM matrix circuit comprises a plurality of means for applying a plurality of input voltages representing an input vector, a plurality of means for applying a plurality of line voltages, and a plurality of means for providing a plurality of output currents representing an output vector. The NVM matrix circuit further comprises a plurality of NVM storage string means each electrically coupled to a corresponding means for applying an input voltage among the plurality of means for applying the plurality of input voltages and a corresponding means for providing an output current among the plurality of means for providing the plurality of output currents. Each of the plurality of NVM storage string means comprises a plurality of NV means for storing a memory state, each having a resistance representing the stored memory state to form a data vector for a corresponding NVM storage string means among the plurality of NVM storage string means. Each plurality of NV means for storing the memory state comprises a means for electrically coupled the resistance of the plurality of NV means for storing the memory state to the means for providing the output current among the plurality of means for providing the plurality of output currents. Each NV means also comprises a means for controlling coupling of the resistance of the plurality of NV means for storing the memory state to the means for providing the output current among the plurality of means for providing the plurality of output currents. The NVM matrix circuit further comprises a plurality of access means for controlling the means for electrically coupling the corresponding means for applying the input voltage among the plurality of means for applying the plurality of input voltages to a corresponding NVM storage string means in the coupling of the resistance of the plurality of NV means for storing the memory state to the means for providing the output current among the plurality of means for providing the plurality of output currents.

[0016] In a further aspect, a method of performing matrix multiplication in an NVM matrix circuit is provided. The method comprises applying a line voltage on at least one bit line among a plurality of bit lines coupled to a corresponding NVM storage string circuit among a plurality of NVM storage string circuits, to electrically couple the line voltage to the corresponding NVM storage string circuit coupled to a corresponding bit line among the plurality of bit lines. Each NVM storage string circuit comprises a plurality of NVM bit cell circuits each having a resistance representing a stored memory state in the NVM bit cell circuit to form a data vector for the corresponding NVM storage string circuit. The method further comprises applying a second line voltage on at least one source line among a plurality of source lines coupled to a corresponding NVM storage string circuit among the plurality of NVM storage string circuits, to electrically coupled the second line voltage to the corresponding NVM storage string circuit coupled to a corresponding source line among the plurality of source lines. The method further comprises applying a plurality of input voltages representing an input vector on a plurality of word lines, wherein each word line is coupled to a corresponding gate node of an NVM bit cell circuit in each of the plurality of NVM storage string circuits, to electrically couple the NVM bit cell circuit to the source line to couple the resistance of the NVM bit cell circuit to the source line. The method further comprises applying an access voltage to a plurality of access transistors, wherein each access transistor is coupled to a corresponding bit line among the plurality of bit lines and a corresponding NVM storage string circuit among the plurality of NVM storage string circuits coupled to the source line corresponding to the bit line, to electrically couple the corresponding bit line to the corresponding NVM storage string circuit.

[0017] In another aspect, an NVM matrix system is provided that comprises a first NVM matrix circuit and a second NVM matrix circuit. The first NVM matrix circuit comprises a plurality of first word lines configured to receive a first input vector represented by a first input voltage on each first word line among the plurality of first word lines. The first NVM matrix circuit further comprises a plurality of first bit lines, and a plurality of first source lines. Each first bit line among the plurality of first bit lines is configured to receive a corresponding first line voltage. Each first source line is coupled to a first output node among a plurality of first output nodes. The first NVM matrix circuit also comprises a plurality of first NVM storage string circuits, each configured to be electrically coupled between a corresponding first bit line among the plurality of first bit lines and a corresponding first source line among the plurality of first source lines. Each first NVM storage string circuit comprises a plurality of first NVM bit cell circuits. Each first NVM bit cell circuit among the plurality of first NVM bit cell circuits has a resistance representing a stored memory state in the first NVM bit cell circuit to form a first data vector for the corresponding first NVM storage string circuit. Each first NVM bit cell circuit comprises a first gate node coupled to a corresponding first word line among the plurality of first word lines, and is configured to couple its resistance to the first source line in response to the first input voltage applied to the corresponding first word line coupled to the first gate node. The second NVM matrix circuit comprises a plurality of second word lines each coupled to an output node among the plurality of first output nodes. The second NVM matrix circuit further comprises a plurality of second bit lines, and a plurality of second source lines. Each second bit line among the plurality of second bit lines is configured to receive a corresponding second line voltage. Each second source line is coupled to a second output node among a plurality of second output nodes. The second NVM matrix circuit also comprises a plurality of second NVM storage string circuits, each configured to be electrically coupled between a corresponding second bit line among the plurality of second bit lines and a corresponding second source line among the plurality of second source lines. Each second NVM storage string circuit comprises a plurality of second NVM bit cell circuits. Each second NVM bit cell circuit among the plurality of second NVM bit cell circuits has a resistance representing a stored memory state in the second NVM bit cell circuit to form a second data vector for the corresponding second NVM storage string circuit. Each second NVM bit cell circuit comprises a second gate node coupled to a corresponding second word line among the plurality of second word lines, and is configured to couple its resistance to the second source line in response to a second input voltage applied to the corresponding second word line coupled to the second gate node.

BRIEF DESCRIPTION OF THE FIGURES

[0018] Figure 1A is an exemplary matrix network circuit employing memristor networks to provide synapses for complementary metal oxide semiconductor (CMOS) circuit neurons;

[0019] Figure IB illustrates an exemplary synaptic connection for a post-synaptic

CMOS circuit neuron in the matrix network circuit of Figure 1 A;

[0020] Figure 2A illustrates an exemplary memristor cross-bar matrix circuit; [0021] Figure 2B illustrates an exemplary memristor cross-bar matrix circuit employing an RRAM cross-bar array circuit;

[0022] Figure 3A is a schematic diagram of an exemplary non- volatile (NV) memory (NVM) matrix circuit without need for cross-bar connections employing NVM storage string circuits in the form of NAND NVM flash circuits and each comprised of a plurality of NVM flash bit cell circuits for performing matrix computations;

[0023] Figure 3B is a schematic diagram of an exemplary two-dimensional (2D) NAND NVM flash circuit that can be an NVM bit cell circuit in the NVM matrix circuit in Figure 3 A;

[0024] Figure 4A illustrates an exemplary logic '0' write operation in the NVM matrix circuit in Figure 3A;

[0025] Figure 4B illustrates an exemplary logic T write operation in the NVM matrix circuit in Figure 3A;

[0026] Figure 5 illustrates an exemplary read operation in the NVM matrix circuit in Figure 3A;

[0027] Figure 6A illustrates another exemplary logic '0' write operation in the NVM matrix circuit in Figure 3A;

[0028] Figure 6B illustrates another exemplary logic ' 1 ' write operation in the NVM matrix circuit in Figure 3A;

[0029] Figure 7 A illustrates another exemplary logic '0' write operation in the NVM matrix circuit in Figure 3A;

[0030] Figure 7B illustrates another exemplary logic ' 1 ' write operation in the NVM matrix circuit in Figure 3A;

[0031] Figure 8A is a flowchart illustrating an exemplary process of performing a write operation in the NVM matrix circuit in Figure 3 A;

[0032] Figure 8B is a flowchart illustrating an exemplary process of performing a read operation in the NVM matrix circuit in Figure 3A;

[0033] Figure 9 is an example of the NVM matrix system that includes the NVM matrix circuit in Figure 3 A and another NVM matrix circuit like the NVM matrix circuit in Figure 3A being configured and/or reconfigured and coupled to the first NVM matrix circuit to provide neuron layers for a synapse NVM matrix circuit; [0034] Figure 10 is a schematic diagram of an exemplary NVM matrix circuit without need for cross-bar connections employing NVM storage string circuits in the form of NAND NVM ferroelectric (Fe) Field-Effect Transistor (FET) (FeFET) circuits each comprising a plurality of NVM FeFET bit cell circuits for performing matrix computations;

[0035] Figure 11 is a schematic diagram of an exemplary NVM matrix circuit without need for cross-bar connections employing NVM storage string circuits in the form of AND NVM flash circuits each comprised of a plurality of NVM flash bit cell circuits for performing matrix computations;

[0036] Figure 12 is a schematic diagram of an exemplary NVM matrix circuit without need for cross-bar connections employing NVM storage string circuits in the form of AND NVM FeFET circuits each comprised of a plurality of NVM FeFET bit cell circuits for performing matrix computations;

[0037] Figure 13 is a schematic diagram of an exemplary NVM matrix circuit without need for cross-bar connections employing NVM storage string circuits in the form of AND NVM magneto-resistive random access memory (MRAM) circuits each comprised of a plurality of NVM MRAM bit cell circuits for performing matrix computations;

[0038] Figure 14 is a schematic diagram of an exemplary NVM matrix circuit without need for cross-bar connections employing NVM storage string circuits in the form of AND NVM resistive random access memory (RRAM) circuits each comprised of a plurality of NVM RRAM bit cell circuits for performing matrix computations;

[0039] Figure 15 is a schematic diagram of an exemplary NVM matrix circuit without need for cross-bar connections employing NVM storage string circuits in the form of NOR NVM flash circuits each comprised of a plurality of NVM flash bit cell circuits for performing matrix computations;

[0040] Figure 16 is a schematic diagram of an exemplary NVM matrix circuit without need for cross-bar connections employing NVM storage string circuits in the form of NOR NVM FeFET circuits each comprised of a plurality of NVM FeFET bit cell circuits for performing matrix computations;

[0041] Figure 17 is a schematic diagram of an exemplary NVM matrix circuit without need for cross-bar connections employing NVM storage string circuits in the form of NOR NVM MRAM circuits each comprised of a plurality of NVM MRAM bit cell circuits for performing matrix computations;

[0042] Figure 18 is a schematic diagram of an exemplary NVM matrix circuit without need for cross-bar connections employing NVM storage string circuits in the form of NOR NVM RRAM circuits each comprised of a plurality of NVM RRAM bit cell circuits for performing matrix computations;

[0043] Figure 19 is a block diagram of an exemplary chip package that includes a system-on-a-chip (SoC), a dedicated memory chip, and a dedicated NVM matrix circuit chip that can include NVM matrix circuits disclosed herein, including without limitation the NVM matrix circuits in Figures 3A-18; and

[0044] Figure 20 is a block diagram of an exemplary processor-based system that includes memory systems that can include NVM matrix circuits disclosed herein, including without limitation the NVM matrix circuits in Figures 3A-18.

DETAILED DESCRIPTION

[0045] With reference now to the drawing figures, several exemplary aspects of the present disclosure are described. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0046] Aspects disclosed in the detailed description include non-volatile (NV) memory (NVM) matrix circuits employing NVM matrix circuits for performing matrix computations. In exemplary aspects disclosed herein, an NVM matrix circuit is provided that has a plurality of NVM storage string circuits each comprising a plurality of NVM bit cell circuits organized in respective memory rows and each configured to store a memory state. For example, the NVM matrix circuit may form an m x n NVM matrix circuit, where 'm' represents the number of memory rows of NVM storage string circuits provided, and 'n' represents the number of NVM bit cell circuits within each NVM storage string circuit provided in respective memory columns. A plurality of bit lines are provided and each configured to be coupled to a respective NVM storage string circuit. A plurality of source lines are provided and each configured to be coupled to a respective NVM storage string circuit. Each NVM bit cell circuit has a stored memory state represented by a resistance, and includes a transistor whose gate node is coupled to a word line among a plurality of word lines configured to receive an input vector of 1 x m size for example. Activation of the gate of a given NVM bit cell circuit controls whether its resistance is contributed to a respective source line. For example, the input vector could be a pre-synapse weight vector for example. Each source line is coupled to a respective output node wherein the source lines for all the NVM storage string circuits can collectively provide an output vector. The output vector may be a post-synapse vector for example. To multiply an input vector of 1 x m size times the m x n memory matrix circuit formed by the plurality of NVM storage string circuits, a line voltage is applied to the bit lines of the NVM storage string circuits while input voltages representing an input vector are applied to gate nodes of the NVM bit cell circuits of the NVM storage string circuits. This causes a summation current to be generated on each source line based on the weighted summed contribution of each NVM bit cell's resistance to its respective source line. Each output line forms an output vector, which is the result of the 1 x m input vector times one (1) column n of the m x n NVM matrix circuit. By the NVM bit cell circuits of the NVM storage string circuits including a transistor coupled to a word line that controls the resistance presented on its respective source line, a cross-bar connection between the word lines and the bit lines does not have to be provided which avoids creating sneak path currents in the NVM matrix circuit. The word lines and the bit lines are isolated from each other through the NVM bit cell circuits.

[0047] In this regard, Figure 3A is a schematic diagram of an exemplary NVM matrix circuit 300 that can perform matrix multiplication without the use of cross-bar connections. The NVM matrix circuit 300 employs NVM storage string circuits 302(0)- 302(m) in 'm+ memory rows Ro-R _m that each include a plurality of NVM bit cell circuits Roo-R _mn in Figure 3A. In this example, the NVM storage string circuits 302(0)- 302(m) are NAND NVM flash circuits wherein the NVM bit cell circuits Roo-Rmn are NVM flash circuits. However, the NVM storage string circuits 302(0)-302(m) can be provided as other types of NVM matrix circuits as discussed in more detail below in other aspects. The NVM bit cell circuits Roo-Rmn in each respective NVM storage string circuit 302(0)-302(m) are arranged in memory rows Ro-R _m and memory columns Co-C _n . The NVM matrix circuit 300 includes a respective bit line BLo-BL _m for each memory row Ro-Rm. Bit line driver circuits 306(0)-306(m) are provided that are each configured to drive a respective line voltage Vo-V _m on the respective bit lines BLo-BL _m . Source lines SL ₀ -SL _m are also provided that are each coupled to a respective output node 308(0)-308(m). The NVM storage string circuits 302(0)-302(m) are coupled between a corresponding bit line BLo-BL _m and a corresponding source line SLo-SL _m in each respective memory row Ro-R _m - The source lines SLo-SL _m are configured to carry a respective current Io-I _m to the respective output nodes 308(0)-308(m) as an output vector So-S _m when their respective NVM bit cell circuits Roo-Rmn are activated. For example, the output vector So-S _m may be a binary post-synapse vector.

[0048] With continuing reference to Figure 3A, the NVM matrix circuit 300 also includes a respective word line WLo-WL _n for each memory column Co-C _n. Word line driver circuits 310(0)-310(n) are provided that are each configured to drive a respective input vector Xo-X _n comprising a plurality of input voltages on the respective word lines WLo-WL _n . As will be discussed in more detail below, the word lines WLo-WL _n are coupled to respective gate nodes Goo-G _mn of the NVM bit cell circuits Roo-Rmn in a given memory column Co-C _n to control the resistances of the NVM bit cell circuits Roo- Rmn being applied to the respective source lines SL ₀ -SL _m . For example, the input vector Xo-X _n may be a binary pre-synapse data vector. The NVM matrix circuit 300 also includes first access transistors 312(0)-312(m) coupled between a respective bit line BLo-BL _m and an NVM storage string circuit 302(0)-302(m). The first access transistors 312(0)-312(m) each comprise a first access gate node G coupled to a respective first access line 314 configured to be driven with a first access voltage by a first access line driver circuit 316. The first access transistors 312(0)-312(m) are each configured to control whether a corresponding line voltage Vo-V _m applied on a respective bit line BLo-BL _m is applied to a respective NVM storage string circuit 302(0)-302(m) in a corresponding memory row Ro-R _m - The first access transistors 312(0)-312(m) are configured to pass a line voltage Vo-V _m on respective bit lines BLo-BL _m in response to a first access signal (voltage) driven by the first access line driver circuit 316 onto a second access line 320 to the first access gate node G of the first access transistors 312(0)-312(m) sufficient to turn on the first access transistors 312(0)-312(m). The NVM matrix circuit 300 also includes second access transistors 318(0)-318(m) coupled between a respective NVM storage string circuit 302(0)-302(m) and a source line SLQ- SL _m coupled to the output nodes 308(0)-308(m). The second access transistors 318(0)- 318(m) are each configured to couple a respective NVM storage string circuit 302(0)- 302(m) to a respective source line SL ₀ -SL _m and a respective output node 308(0)-308(m) in response to a second access signal (voltage) driven by the second access line driver circuit 322 onto the second access line 320 to a second access gate node G of the second access transistors 318(0)-318(m) sufficient to turn on the second access transistors 318(0)-318(m). As shown in Figure 3 A, there is no cross-bar coupling between the word lines WLo-WL _n and the bit lines BLo-BL _m . The access transistors 312(0)-312(m), 318(0)-318(m) of the NVM storage string circuits 302(0)-302(m) can provide further isolation between the word lines WLo-WL _n and the bit lines BLo-BL _m .

[0049] With continuing reference to Figure 3A, each NVM bit cell circuit Roo-R _mn in the NVM matrix circuit 300 is an NVM flash circuit that does not need power to retain data in this example. Figure 3B is a schematic diagram of an exemplary two- dimensional (2D) NAND flash memory circuit that can be provided as the NVM storage string circuits 302(0)-302(m) in the NVM matrix circuit 300 in Figure 3A. Figure 3B illustrates an exemplary NVM storage string circuit 302(0) that can be provided in memory row R ₀ in the NVM matrix circuit 300 in Figure 3 A as an example in both a circuit and layout diagram. As shown in Figure 3B, the NVM bit cell circuits R ₀ o-R _mn are each coupled to each other in a series-coupled, string fashion, which source nodes Soo-Son-i of the NVM bit cell circuits Roo-R _n -i are coupled to drain nodes Doi-Do _n of an adjacent NVM bit cell circuit Roi-Ro _n - The end NVM bit cell circuits Roo, R _n in the NVM storage string circuit 302(0) are coupled to respective access transistors 312(0), 318(0). Each NVM bit cell circuit Roo-Ro _n has a resistance representing a stored memory state. Each NVM bit cell circuit Roo-R _mn has a transistor comprising a gate Goo-Go _n that is coupled to a respective word line WLo-WL _n based on in which memory column Co-C _n the NVM bit cell circuit Roo-R _mn is located. Each NVM bit cell circuit Roo-R _mn is configured to be activated to activate a semiconductor channel to couple its resistance on a respective source line SLo-SL _m in its memory row Ro-R _m - The collective memory states in the NVM bit cell circuits Roo-Ro _n form a data vector stored in the NVM storage string circuit 302(0). As shown in Figure 3B, there is no cross-bar coupling between the word line WLo and the bit line BLo, which is also true between all word lines WLo-WL _n and the respective bit lines BLo-BL _m . [0050] With continuing reference to Figure 3B, as will be discussed in more detail below, when a line voltage in applied to bit line BLo and access voltages are applied to the access gate nodes G of the access transistors 312(0)-312(m) sufficient to activate the semiconductor channels C of the access transistors 312(0)-312(m), the NVM storage string circuit 302(0) is coupled to the bit line BLo and the source line SLo. The input voltages as an input vector Xo-X _n applied to the word lines WLo-WL _n and gate nodes Goo-Go _n of the respective NVM bit cell circuits Roo-Ro _n as an input vector Xo-X _n control activation of the respective NVM bit cell circuits Roo-Ro _n - When activated, the NVM bit cell circuits Roo-Ro _n couple their resistances to the source line SLo. The resistances of the NVM bit cell circuits Roo-Ro _n are a function of their stored memory states. Thus, the resistances of the NVM bit cell circuits Roo-Ro _n can represent a weight vector. The current Io flowing on a respective source line SLo to the output node 308(0) is a function of the sum of the dot product multiplications of the respective input vector Xo-X _n multiplied by the corresponding memory states in the NVM bit cell circuits Roo-Ro _n of the NVM storage string circuit 302(0). Thus, with reference to Figure 3A, all the NVM bit cell circuits R ₀ o-Ro _n for the NVM storage string circuits 302(0)-302(m) in the NVM matrix circuit 300 in Figure 3A can represent a weight matrix. The current I ₀ -I _m flowing from the respective source lines SL ₀ -SL _M of the respective NVM storage string circuits 302(0)-302(m) to output nodes 308(0)-308(m) is a function of the respective line voltages Vo-V _m driven by the bit line driver circuits 306(0)-306(m) on the respective source lines SLo-SL _m divided by the summed channel resistances of the NVM bit cell circuits Roo-R _mn of the NVM storage string circuits 302(0)-302(m). The currents Io-I _m may be analog representations of a summation of the dot product multiplications which can be converted to binary values. In other words, the NVM matrix circuit 300 in Figure 3A is configured to produce currents Io-I _m on an input layer according to the following formula: = /∑R _y - j

where:

i = memory row 0 to m;

j = memory column 0 to n; VBL = voltage V;; and

Ri _j = resistance of an NVM bit cell circuit.

[0051] Thus, with continuing reference to Figure 3A, the NVM matrix circuit 300 is configured to perform matrix multiplication of each of the 1 x n weight vectors stored as respective memory states in each of the NVM storage string circuits 302(0)-302(m) by the n x 1 input vector Xo-X _n simultaneously. The dot products of these vector multiplications are provided as a function of the respective amplitudes of the currents Io- I _m generated at the output nodes 308(0)-308(m) according to the current formula provided above.

[0052] Further, if the word lines WLo-WL _m are coupled to a pre-neuron layer and the output nodes 308(0)-308(m) are coupled to a post-neuron layer, the NVM matrix circuit 300 is also configured to train the channel resistance of the NVM bit cell circuits Roo- Rmn by supporting backwards propagation of a weight update according to the following formula: ^{= '} $ postj ^' S ' post+\,j where:

Ri _j = resistance of an NVM bit cell circuit; and

S = value at source lines of NVM bit cell circuits.

[0053] The weight matrix of the NVM matrix circuit 300 provided as stored memory states in the NVM bit cell circuits Roo-R _mn can be set to the desired memory states in a write operation to provide the desired weight matrix. For example, Figure 4 A illustrates writing a logic '0' in a write operation to the NVM bit cell circuit R25 in the NVM matrix circuit 300 in Figure 3A. As shown therein, to write a logic '0' to NVM bit cell circuit R25 in this example, a 0 V or 5 V line voltage is applied by the bit line driver circuit 306(2) on the bit line BL2 for memory row R2 depending on whether the NVM bit cell circuit R25 stores a memory state with or without a charge trap, respectively. A line voltage of 5V is applied on source line SL2 coupled to the output node 308(2). An input voltage of 10V is applied to the word line WL2 to be applied to the gate node G25 of the NVM bit cell circuit R25 to program the memory state of the NVM bit cell circuit R25 to a logic '0' memory state. Similarly, Figure 4B illustrates writing a logic T in a write operation to the NVM bit cell circuit R25 in the NVM matrix circuit 300 in Figure 3 A. As shown therein, to write a logic Ί ' to NVM bit cell circuit R ₂ 5 in this example, a 0 V or 5 V line voltage is applied by the bit line driver circuit 306(2) on the bit line BL ₂ for memory row R ₂ depending on whether the NVM bit cell circuit R25 stores a memory state without or with a charge trap, respectively. A line voltage of 0V is applied on the source line SL ₂ coupled to the output node 308(2). A voltage of - 10 V is applied to the word line WL ₂ to be applied to the gate node G ₂ 5 of the NVM bit cell circuit R _2¾ to program the memory state of NVM bit cell circuit R _2¾ to a logic ' 1 ' memory state.

[0054] Figure 5 illustrates an exemplary read operation in the NVM matrix circuit 300 in Figure 3A. A read operation is performed to cause the NVM matrix circuit 300 to perform a matrix computation. To multiply the input vector Xo-X _n times the memory states of each of the NVM storage string circuits 302(0)-302(m) to generate respective currents Io-I _m on the source lines SLo-SL _m coupled to the output nodes 308(0)-308(m), all the NVM bit cell circuits Roo-R _mn are activated in this example. In this regard, in this example, an input voltage of 4.5 V is applied as the input vector Xo-X _n to each of the respective word lines WL ₀ -WL _n to cause the channel resistances of each of the NVM bit cell circuits R ₀ o-R _m n added in series to contribute to the overall series resistance of the respective source lines SLo-SL _m . Their channel resistances contribute to the overall series resistance of respective source lines SLo-SL _m and are a function of the memory states stored in the NVM bit cell circuits Roo-R _mn - The currents Io-I _m at the output nodes 308(0)-308(m) are a function of the sum of the dot product multiplications of input vectors Xo-X _n multiplied by the respective memory states of the NVM bit cell circuits Roo-Rmn each in the respective NVM storage string circuits 302(0)-302(m) as weight vectors.

[0055] More than one NVM bit cell circuit Roo-Rmn in a given memory row Ro-R _m in the NVM matrix circuit 300 in Figure 3A can be written to at a time as part of a write operation. In this regard, Figure 6A illustrates writing a logic '0' in a write operation to the NVM bit cell circuits R ₂₂ and R ₂₅ in the NVM matrix circuit 300 in Figure 3A. As shown in Figure 6A, to write a logic '0' to NVM bit cell circuits R ₂₂ and R _¾ in this example, a 0 V or 5 V line voltage is applied by the bit line driver circuit 306(2) on the bit line BL ₂ for memory row R ₂ depending on whether the NVM bit cell circuits R ₂₂ and R25 store a memory state with or without a charge trap, respectively. A line voltage of 5 V is applied on the source line SL2. An input (i.e., program) voltage of 10V is applied to the word lines WL ₂ and WL ₅ to be applied to both gate nodes G22 and G25 of the NVM bit cell circuits R ₂ 2 and R ₂ 5 to program the NVM bit cell circuits R ₂ 2 and R ₂ 5 to a logic '0' memory state. A different input voltage not sufficient to program the NVM bit cell circuits R ₀ o-R _m o, Roi-Rmi, Ro3-R _m 3 , Ro4-R _m 4, Roe-Rmn in memory columns C ₀ , Ci, C ₃ , C ₄ , and C6-C _n can be applied to write lines WLo _, WLi _, WL ₃ , WL ₄ , and WL ₆ -WL _n for the write operation. Similarly, Figure 6B illustrates writing a logic Ί ' in a write operation to the NVM bit cell circuits R22 and R25 in the NVM matrix circuit 300 in Figure 3A. As shown in Figure 6B, to write a logic T to NVM bit cell circuits R22 and R25 in this example, a 0 V or 5 V line voltage is applied by the bit line driver circuit 306(2) on the bit line BL2 for memory row R2 depending on whether the NVM bit cell circuits R22 and R25 store a memory state without or with a charge trap, respectively. A voltage of 0 V is applied on the source line SL2. An input (i.e., program) voltage of -10V is applied to the word lines WL2 and WL5 to be applied to both gate nodes G22 and G25 of the NVM bit cell circuits R22 and R25 to program the NVM bit cell circuits R22 and R25 to a logic ' 1 ' memory state.

[0056] More than one NVM bit cell circuits R ₀ o-R _m n in a given memory column Co- C _n in the NVM matrix circuit 300 in Figure 3A can be written to at a time as part of a write operation. In this regard, Figure 7A illustrates writing a logic '0' in a write operation to both NVM bit cell circuits R25 and R _m- i5 in memory column C5 in the NVM matrix circuit 300 in Figure 3A. As shown in Figure 7A, to write a logic '0' to NVM bit cell circuits R25 and R _m- i5 in this example, a 0 V or 5 V line voltage is applied by the bit line driver circuits 306(2), 306(m-l) on the bit lines BL2 and BL _m _i for memory rows R2 and R _m _i depending on whether the NVM bit cell circuits R25 and R _m- i5 store a memory state with or without a charge trap, respectively. A line voltage of 5 V is applied on the source lines SL2 and SL _m _i . An input (i.e., program) voltage of 10V is applied to the word line WL2 to be applied to gate nodes G25 and G _m- i5 of the NVM bit cell circuits R25 and R _m- i5 to program the NVM bit cell circuits R25 and R _m- i5 to a logic '0' memory state. Similarly, Figure 7B illustrates writing a logic T in a write operation to both NVM bit cell circuits R25 and R _m- i5 in memory column C5 in the NVM matrix circuit 300 in Figure 3 A. As shown in Figure 7B, to write a logic T to NVM bit cell circuits R25 and R _m- i5 in this example, a 0 V or 5 V line voltage is applied by the bit line driver circuits 306(2), 306(m-l) on the bit lines BL ₂ and BL _m _i for memory row R2 depending on whether the NVM bit cell circuits R ₂ 5 and R _m _i5 store a memory state without or with a charge trap, respectively. A line voltage of 0 V is applied on the source lines SL ₂ and SL _m _i . An input (i.e., program) voltage of -10V is applied to the word line WL ₂ to be applied to gates G25 and G _m- i5 of the NVM bit cell circuits R25 and Rm-i5 to program the NVM bit cell circuits R25 and R _m- i5 to a logic T memory state.

[0057] Figure 8A is a flowchart illustrating an exemplary process 800 of performing a read operation in the NVM matrix circuit 300 in Figure 3A. Examples of read operations to the NVM matrix circuit 300 in Figure 3A were discussed above with regard to Figures 6A-7B. In this regard, with reference to Figures 3A and 8A, the process 800 includes applying a line voltage on at least one bit line BLo-BL _m among a plurality of bit lines BLo-BL _m coupled to a corresponding NVM storage string circuit 302(0)-302(m) among the plurality of NVM storage string circuits 302(0)-302(m), to electrically couple the line voltage to the corresponding NVM storage string circuit 302(0)-302(m) coupled to a corresponding bit line BLo-BL _m among the plurality of bit lines BL ₀ -BL _m (block 802 in Figure 8A). Each of the plurality of NVM storage string circuits 302(0)-302(m) comprise a plurality of NVM bit cell circuits R _x0 -R _xn among a plurality of bit lines BLo-BL _m each having a channel resistance representing a stored memory state in the NVM bit cell circuit R _x o-R _xn to form a data vector for the corresponding NVM storage string circuit 302(0)-302(m). The process 800 also involves applying a second line voltage on at least one source line SLo-SL _m among a plurality of source lines SLo-SL _m coupled to a corresponding NVM storage string circuit 302(0)-302(m) among the plurality of NVM storage string circuits 302(0)-302(m), to electrically couple a second line voltage to the corresponding NVM storage string circuit 302(0)-302(m) coupled to a corresponding source line SLo-SL _m among a plurality of source lines SLo-SL _m (block 804 in Figure 8A). The process 800 also involves applying a plurality of input voltages representing an input vector Xo-X _n on a plurality of word lines WLo-WL _n , each word line WLo-WL _n among the plurality of word lines WLo-WL _n coupled to a corresponding gate node Goo-G _mn of an NVM bit cell circuit Roo-Rmn in each of the plurality of NVM storage string circuits 302(0)-302(m), to electrically couple the NVM bit cell circuit Roo-Rmn to the source line SLo-SL _m to couple the channel resistance of the NVM bit cell circuit Roo-R _mn to the source line SLo- SL _m (block 806 in Figure 8A). The process 800 also involves applying an access voltage to a plurality of access transistors 312(0)-312(m), each access transistor 312(0)- 312(m) among the plurality of access transistors 312(0)-312(m) coupled to a corresponding bit line BLo-BL _m among the plurality of bit lines BLo-BL _m and a corresponding NVM storage string circuit 302(0)-302(m) among the plurality of NVM storage string circuits 302(0)-302(m). The plurality of NVM storage string circuits 302(0)-302(m) are coupled to a respective source line SLo-SL _m corresponding to the bit line BLo-BL _m , to electrically couple the corresponding bit line BLo-BL _m to the corresponding NVM storage string circuit 302(0)-302(m) (block 808 in Figure 8A). Figure 8B is a flowchart illustrating an exemplary process 810 of performing a read operation in the NVM matrix circuit 300 in Figure 3A. Examples of write operations to the NVM matrix circuit 300 in Figure 3A were discussed above with regard to Figures 5A and 5B. In this regard, with reference to Figures 3A and 8B, the process 810 includes applying a line voltage to a bit line BLo-BL _m among the plurality of bit lines BLo-BL _m coupled to a corresponding NVM storage string circuit 302(0)-302(m) among the plurality of NVM storage string circuits 302(0)-302(m) (block 812 in Figure 8B). The process 810 also involves applying a second line voltage to a source line SL ₀ -SL _m among the plurality of source lines SLo-SL _m coupled to the corresponding NVM storage string circuit 302(0)-302(m) (block 814 in Figure 8B). The process 810 also involves applying a write activation voltage to a gate node Goo-Gmn of an NVM bit cell circuit Roo-Rmn in the corresponding NVM storage string circuit 302(0)-302(m) to write a memory state based on the write activation voltage applied to the gate node Goo-G _mn of the NVM bit cell circuit Roo-Rmn (block 816 in Figure 8B).

[0058] The NVM matrix circuit 300 in Figure 3A can also be employed and reconfigured to provide reconfigured neuron paths to support universal deep learning or artificial intelligence (AI) tasks for different neuron layers and neurons. In this regard, Figure 9 is an example of an NVM matrix system that includes an NVM matrix circuit 300 in Figure 3A being configured as an n x m NVM matrix circuit 300 like shown in Figure 3A. Another NVM matrix circuit 300A is provided that is similar to the NVM matrix circuit 300, but is configured as an m x k NVM matrix circuit. The NVM matrix circuits 300, 300A can be coupled together to form first and second respective neuron layers 900(1), 900(2) with output vectors So-S _m providing intermediate neurons 902. This allows a dot product output vector So-S _m as a result of the matrix calculation of n x m NVM matrix circuit 300 to be used as an input vector Xo-X _m to the NVM matrix circuit 300A to produce dot produce output vectors Thus, the NVM matrix circuit 300 being coupled to the other NVM matrix circuit 300A is configured to produce currents Io-I _k on a hidden layer according to the following formula: h

where:

h = memory row 0 to m;

1 = memory column 0 to k;

VBL = voltage of bit lines BLo' -BL _m ' ; and

R _h i = channel resistances of an NVM bit cell circuit in the NVM matrix circuit 300A.

[0059] The operation of the matrix calculations and write operations that can be performed in the NVM matrix circuits 300, 300A in Figure 9 can be as previously described for the NVM matrix circuit 300.

[0060] Other types of NVM bit cell circuits can be employed besides NAND NVM flash memory circuits like shown in the NVM matrix circuit 300 in Figure 3A. For example, Figure 10 is a schematic diagram of another exemplary NVM matrix circuit 1000 without need for cross-bar connections between bit lines and word lines like not included the NVM matrix circuit 300 in Figure 3A. However, the NVM matrix circuit 1000 includes NVM storage string circuits 1002(0)- 1002(m) in the form of NAND NVM ferroelectric (Fe) Field-Effect Transistor (FET) (FeFET) circuits in this example. The NVM bit cell circuits Roo-R _mn in each respective NVM storage string circuits 1002(0)-1002(m) are NVM FeFET circuits arranged in memory rows Ro-R _m and memory columns Co-C _n . The NVM matrix circuit 1000 includes a respective bit line BLo-BL _m for each memory row Ro-R _m . Bit line driver circuits 1006(0)- 1006(m) are provided that are each configured to drive a respective line voltage Vo-V _m on the respective bit lines BLo-BL _m . Source lines SLo-SL _m are also provided that are each coupled to a respective output node 1008(0)- 1008(m). The NVM storage string circuits 1002(0)-1002(m) are coupled between a corresponding bit line BLo-BL _m and a corresponding source lines SLo-SL _m in each respective memory row Ro-R _m - The source lines SL ₀ -SL _m are configured to carry a respective current I ₀ -I _m to the respective output nodes 1008(0)-1008(m) as an output vector when their respective NVM bit cell circuits Roo-R _mn are activated. For example, the output vector may be a binary post-synapse vector.

[0061] With continuing reference to Figure 10, the NVM matrix circuit 1000 also includes a respective word line WLo-WL _n for each memory column Co-C _n. Word line driver circuits 1010(0)- 1010(n) are provided that are each configured to drive a respective input vector Xo-X _n comprising a plurality of input voltages on the respective word lines WLo-WL _n . For example, the input vector Xo-X _n may be a binary pre- synapse data vector. The NVM matrix circuit 1000 also includes first access transistors 1012(0)-1012(m) coupled between a respective bit line BLo-BL _m and an NVM storage string circuit 1002(0)-1002(m). The first access transistors 1012(0)-1012(m) each comprise a first access gate node G coupled to a respective first access line 1014 configured to be driven with a first access voltage by a first access line driver circuit 1016. The first access transistors 1012(0)-1012(m) are each configured to control whether a corresponding line voltage V ₀ -V _m applied on a respective bit line BL ₀ -BL _m is applied to a respective NVM storage string circuit 1002(0)- 1002(m) in a corresponding memory row Ro-R _m - The first access transistors 1012(0)-1012(m) are configured to pass a line voltage Vo-V _m on respective bit lines BLo-BL _m in response to a first access signal (voltage) driven by the first access line driver circuit 1016 onto a second access line 1020 to the first access gate node G of the first access transistors 1012(0)-1012(m) sufficient to turn on the first access transistors 1012(0)-1012(m). The NVM matrix circuit 1000 also includes second access transistors 1018(0)-1018(m) coupled between a respective NVM storage string circuit 1002(0)- 1002(m) and a source line SLo-SL _m coupled to the output nodes 1008(0)- 1008(n). The second access transistors 1018(0)- 1018(m) are each configured to couple a respective NVM storage string circuit 1002(0)- 1002(m) to a respective source line SLo-SL _m and a respective output node 1008(0)- 1008(m) in response to a second access signal (voltage) driven by a second access line driver circuit 1022 onto the second access line 1020 to the second access gate node G of the second access transistors 1018(0)-1018(m) sufficient to turn on the second access transistors 1018(0)-1018(m). As shown in Figure 10, there is no cross-bar coupling between the word lines WLo-WL _n and the bit lines BLo-BL _m . The access transistors 1012(0)-1012(m), 1018(0)- 1018(m) of the NVM storage string circuits 1002(0)- 1002(m) provide isolation between the word lines WL ₀ -WL _n and the bit lines BL ₀ -BL _m .

[0062] With continuing reference to Figure 10, each NVM bit cell circuit Roo-Rmn in the NVM matrix circuit 1000 is an NVM FeFET circuit that does not need power to retain data in this example. The NVM bit cell circuits Roo-Rmn in this example are each coupled to each other in a series-coupled, string fashion. Using the NVM storage string circuit 1002(0) in memory row Ro as an example, source nodes of the NVM bit cell circuits Roo-R _n -i are coupled to the drain nodes of an adjacent NVM bit cell circuit Roi- R _0n . The end NVM bit cell circuits R ₀₀ , R _on in the NVM storage string circuit 1002(0) are coupled to respective access transistors 1012(0), 1018(0). Each NVM bit cell circuit Roo-Ron has a resistance representing a stored memory state. Each NVM bit cell circuit Roo-Rmn has a transistor comprising a gate Goo-Go _n that is coupled to a respective word line WLo-WL _n based on in which memory column Co-C _n the NVM bit cell circuit Roo- Rmn is located. Each NVM bit cell circuit Roo-R _mn is configured to be activated to activate a semiconductor channel to couple its resistance on a respective source line SL ₀ -SL _m in its memory row Ro-R _m - The collective memory states in the NVM bit cell circuits Roo-Ron form a data vector stored in the NVM storage string circuit 1002(0). As shown in Figure 10, there is no cross-bar coupling between the word line WLo and the bit line BLo, which is also true between all word lines WLo-WL _n and the respective bit lines BLo-BL _m .

[0063] With continuing reference to Figure 10, when a line voltage is applied to bit line BLo and access voltages are applied to the access gate nodes G of the access transistors 1012(0)-1012(m) sufficient to activate the semiconductor channels C of the access transistors 1012(0)-1012(m), the NVM storage string circuit 1002(0) is coupled to the bit line BLo and the source line SLo. The input voltages as an input vector Xo-X _n applied to the word lines WLo-WL _n and the gate nodes Goo-Go _n as an input vector Xo-X _n control activation of the respective NVM bit cell circuits Roo-Ron- When activated, the NVM bit cell circuits Roo-Ron couple their resistances to the source line SLo. The resistances of the NVM bit cell circuits Roo-Ron are a function of their stored memory states. Thus, the resistances of the NVM bit cell circuits Roo-Ron can represent a weight vector. The current Io flowing on a respective source line SLo to the output node 1008(0) is a function of the sum of the dot product multiplications of the respective input vector Xo-X _n multiplied by the corresponding memory states in the NVM bit cell circuits R ₀ o-Ro _n of the NVM storage string circuit 1002(0). Thus, with reference to Figure 10, all the NVM bit cell circuits Roo-Ro _n for the NVM storage string circuits 1002(0)-1002(m) in the NVM matrix circuit 1000 in Figure 10 can represent a weight matrix. The current Io-I _m flowing from the respective source lines SLo-SL _m of the respective NVM storage string circuits 1002(0)-1002(m) to output nodes 1008(0)- 1008(m) is a function of the respective line voltages Vo-V _m driven by the bit line driver circuits 1006(0)-1006(m) on the respective source lines SLo-SL _m divided by the summed channel resistances of the NVM bit cell circuits Roo-R _mn of the NVM storage string circuits 1002(0)- 1002(m). The currents Io-I _m may be analog representations of a summation of the dot product multiplications which can be converted to binary values. In other words, the NVM matrix circuit 1000 in Figure 10 is configured to produce currents Io-I _m on an input layer according to the following formula: = _BL /∑R _y - j

where:

i = memory row 0 to m;

j = memory column 0 to n;

VBL = voltage V;; and

Ri _j = channel resistance of an NVM bit cell circuit.

[0064] Thus, with continuing reference to Figure 10, the NVM matrix circuit 1000 is configured to perform matrix multiplication of each of the 1 x n weight vectors stored as respective memory states in each of the NVM storage string circuits 1002(0) -1002(m) by the n x 1 input vector Xo-X _n simultaneously. The summed dot product multiplications of these vector multiplications are provided as a function of the respective amplitudes of the currents Io-I _m generated at the output nodes 1008(0)- 1008(m) according to the current formula provided above. [0065] Further, if the word lines WLo-WL _m are coupled to a pre-neuron layer and the output nodes 1008(0)- 1008(m) are coupled to a post-neuron layer, the NVM matrix circuit 1000 is also configured to train the channel resistance of the NVM bit cell circuits R ₀ o-R _m n by supporting backwards propagation of a weight update according to the following formula:

where:

Ri _j = channel resistance of an NVM bit cell circuit; and S = value at source lines of NVM bit cell circuits.

[0066] The weight matrix of the NVM matrix circuit 1000 provided as stored memory states in the NVM bit cell circuits Roo-R _mn can be set to the desired memory states in a write operation to provide the desired weight matrix. The write and read operations previously described for the NVM matrix circuit 300 in Figure 3A can be applied to the NVM matrix circuit 1000 in Figure 10.

[0067] Figure 11 illustrates an NVM matrix circuit 1100 that is a reconfiguration of the NVM matrix circuit 300 in Figure 3A into an n x m matrix by switching the memory rows and columns to have memory rows Ro-R _n and memory columns Co-C _m . The NVM matrix circuit 1100 includes NVM storage string circuits 1102(0)- 1102(m) in the form of AND NVM flash circuits in this example, which are provided in respective memory columns Co-C _m to provide NVM bit cell circuits Roo-R _nm - Thus, each NVM bit cell circuit Roo-Rnm is an NVM flash circuit. The word lines WLo-WL _n and bit lines BLo- BLm are reversed between memory rows Ro-R _n and columns Co-C _m from the NVM matrix circuit 300 in Figure 3A, but are still coupled to the NVM bit cell circuits Roo- Rnm in the same manner as in the NVM matrix circuit 300 in Figure 3A. In this regard, as shown in Figure 11 , word lines WLo-WL _n that receive input vector Xo-X _n in the form of input voltages are provided for each memory row Ro-R _n - The bit lines BLo-BL _m are provided for each memory column Co-C _m . Common components between the NVM matrix circuit 300 in Figure 3 A and the NVM matrix circuit 1100 in Figure 11 are shown with common element numbers and thus will not be re-described. Read and write operations similar to that described above with regard to the NVM matrix circuit 300 can be performed in the NVM matrix circuit 1100 in Figure 11.

[0068] Each NVM bit cell circuit R ₀ o-R _n m has a channel resistance representing a stored memory state. The channel resistances of the NVM bit cell circuits R ₀ o-R _n m represent a weight matrix. Each NVM bit cell circuit Roo-R _nm has a transistor comprising a gate node Goo-G _nm that is coupled to a respective word line WLo-WL _n based on in which memory row Ro-R _n the NVM bit cell circuit Roo-Rnm is located. Each NVM bit cell circuit Roo-Rnm is configured to activate its semiconductor channel to couple its channel resistance (i.e., conductance) between the respective bit lines BLo- BLm the respective source line SLo-SL _m in parallel with other activated NVM bit cell circuits Roo-R _nm in the same memory column Co-C _m . Current Io-I _m flows from a respective source line SL _O -SL _M to output nodes 1108(0)- 1108(m) as a function of the respective line voltage Vo-V _m driven by the bit line driver circuit 1006(0)- 1006(m) to the NVM bit cell circuits Roo-R _nm in their respective memory column Co-C _m divided by the parallel channel resistances of the NVM bit cell circuits Roo-R _nm in a respective memory column Co-C _m . As shown in Figure 11, each NVM bit cell circuit Roo-R _nm in an NVM storage string circuit 1102(0)- 1102(m) comprises a source node (or drain node) coupled to a corresponding bit line BL ₀ -BL _m and a drain node (or source node) coupled to a corresponding source line SLo-SL _m to be configured to be coupled in parallel with other NVM bit cell circuits Roo-R _nm in a respective memory column Co-C _m . Thus, for example, current Io flowing on a respective source line SLo to the output node 1008(0) is a function of the sum of the dot products, meaning a respective input vector Xo-Xn multiplied by the corresponding memory states in the NVM bit cell circuits Roo- Ron in their respective, corresponding memory column Co-C _m . The currents Io-I _m may be analog representations of a summation of the dot product multiplications which can be converted to binary values. In other words, the NVM matrix circuit 1100 is configured to produce currents Io-I _m on an input layer according to the following formula:

where:

i = memory column 0 to m;

j = memory row 0 to n;

V _BL = voltage V;; and

Ri _j = channel resistance of an NVM bit cell circuit.

[0069] If the word lines WLo-WL _m are coupled to a pre-neuron layer and the output nodes 1108(0)- 1108(m) are coupled to a post- neuron layer, the NVM matrix circuit 1100 is also configured to train the channel resistance of the NVM bit cell circuits Roo- Rmn by supporting backwards propagation of a weight update according to the following formula:

where: ' ^' ^ postj ^' ° post+l,j

Ri _j = channel resistance of an NVM bit cell circuit; and S = value at source lines of NVM storage string circuits.

[0070] Figure 12 illustrates an NVM matrix circuit 1200 that is a reconfiguration of the NVM matrix circuit 300 in Figure 3A into an n x m matrix by switching the memory rows and columns to have memory rows Ro-R _n and memory columns Co-C _m . The NVM matrix circuit 1200 includes NVM storage string circuits 1202(0)- 1202(m) in the form of AND NVM FeFET circuits in this example, which are provided in respective memory columns Co-C _m to provide NVM bit cell circuits Roo-R _nm - Thus, each NVM bit cell circuit Roo-Rnm is an NVM FeFET circuit. The word lines WLo-WL _n and bit lines BLo_BL _m are reversed between memory rows Ro-R _n and columns Co-C _m from the NVM matrix circuit 300 in Figure 3A, but are still coupled to the NVM bit cell circuits Roo- Rnm in the same manner as in the NVM matrix circuit 300 in Figure 3A. In this regard, as shown in Figure 12, word lines WLo-WL _n that receive input vector Xo-X _n in the form of input voltages are provided for each memory row Ro-R _n - The bit lines BLo-BL _m are provided for each memory column Co-C _m . Common components between the NVM matrix circuit 300 in Figure 3 A and the NVM matrix circuit 1200 in Figure 12 are shown with common element numbers and thus will not be re-described. Read and write operations similar to that described above with regard to the NVM matrix circuit 300 can be performed in the NVM matrix circuit 1200 in Figure 12.

[0071] Each NVM bit cell circuit R ₀ o-R _n m has a channel resistance representing a stored memory state. The channel resistances of the NVM bit cell circuits Roo-R _nm represent a weight matrix. Each NVM bit cell circuit Roo-R _nm has a transistor comprising a gate node Goo-G _nm that is coupled to a respective word line WLo-WL _n based on in which memory row Ro-R _n the NVM bit cell circuit Roo-R _nm is located. Each NVM bit cell circuit Roo-R _nm is configured to activate its semiconductor channel to couple its channel resistance (i.e., conductance) between the respective bit lines BLo- BL _m and the respective source lines SLo-SL _m in parallel with other activated NVM bit cell circuit Roo-R _nm in the same memory column Co-C _m . Current Io-I _m flows from a respective source line SLo-SL _m to output nodes 1208(0)-1208(m) as a function of the respective line voltage Vo-V _m driven to the NVM bit cell circuits Roo-R _nm in their respective memory column Co-C _m divided by the parallel channel resistances of the NVM bit cell circuits Roo-R _nm in a respective memory column Co-C _m . As shown in Figure 12, each NVM bit cell circuit Roo-R _nm in an NVM storage string circuit 1202(0)- 1202(m) comprises a source node (or drain node) coupled to a corresponding bit line BLo-BL _m and a drain node (or source node) coupled to a corresponding source line SLo- SL _m to be configured to be coupled in parallel with other NVM bit cell circuits Roo-R _nm in a respective memory column Co-C _m . Thus, for example, current Io flowing on a respective source line SLo to the output node 1208(0) is a function of the sum of the dot product multiplications, meaning a respective input vector Xo-X _n multiplied by the corresponding memory states in NVM bit cell circuits Roo-Ro _n in their respective, corresponding memory column Co-C _m . The currents Io-I _m may be analog representations of a summation of the dot product multiplications which can be converted to binary values. In other words, the NVM matrix circuit 1200 is configured to produce currents Io-I _m on an input layer according to the following formula:

where:

i = memory column 0 to m;

j = memory row 0 to n;

VBL = voltage V;; and

Ri _j = channel resistance of an NVM bit cell circuit.

[0072] If the word lines WLo-WL _m are coupled to a pre-neuron layer and the output nodes 1208(0)-1208(m) are coupled to a post-neuron layer, the NVM matrix circuit 1200 is also configured to train the channel resistance of the NVM bit cell circuits Roo- R _nm by supporting backwards propagation of a weight update according to the following formula:

A D _ γ, C C

where: y ' postj post+l,j

Ri _j = channel resistance of an NVM bit cell circuit; and S = value at source lines of NVM storage string circuits.

[0073] Figure 13 illustrates an NVM matrix circuit 1300 that is also a reconfiguration of the NVM matrix circuit 300 in Figure 3A into an n x m matrix by switching the memory rows and columns to have memory row Ro-R _n and memory columns Co-C _m . The NVM matrix circuit 1300 includes NVM storage string circuits 1302(0)-1302(m) in the form of AND NVM magneto-resistive random access memory (MRAM) circuits in this example, which are provided in respective memory columns Co-C _m to provide NVM bit cell circuits Roo-R _nm - Thus, each NVM bit cell circuit Roo-R _nm is an NVM MRAM circuit. The word lines WL ₀ _WL _n and bit lines BL ₀ _BL _m are reversed between memory rows Ro-R _n and columns Co-C _m from the NVM matrix circuit 300 in Figure 3A, but are still coupled to the NVM bit cell circuits Roo-R _nm in the same manner as in the NVM matrix circuit 300 in Figure 3A. In this regard, as shown in Figure 13, word lines WLo- WL _n that receive input vectors Xo-X _n in the form of input voltages are provided for each memory row Ro-R _n - The bit lines BLo-BL _m are provided for each memory column Co- C _m . Common components between the NVM matrix circuit 300 in Figure 3A and the NVM matrix circuit 1300 in Figure 13 are shown with common element numbers and thus will not be re-described. Read and write operations similar to that described above with regard to the NVM matrix circuit 300 can be performed in the NVM matrix circuit 1300 in Figure 13.

[0074] Each NVM bit cell circuit Roo-R _nm has a resistance representing a stored memory state. In this example, the resistances of the NVM bit cell circuits Roo-R _nm are a function of whether a magnetic tunnel junction (MTJ) in the NVM bit cell circuits Roo- R _nm are in a parallel (P) or anti-parallel (AP) magnetization state representing a memory state. The resistances of the NVM bit cell circuits Roo-R _nm represent a weight matrix. Each NVM bit cell circuit Roo-R _nm has a transistor comprising a gate node Goo-G _nm that is coupled to a respective word line WLo-WL _n based on in which memory row Ro-R _n the NVM bit cell circuit Roo-R _nm is located. Each NVM bit cell circuit Roo-R _nm is configured to activate its semiconductor channel to couple the MTJ resistance (i.e., conductance) between the respective bit lines BLo-BL _m and the respective source line SLo-SL _m in parallel with other activated NVM bit cell circuits Roo-R _nm in the same memory column Co-C _m . Current Io-I _m flows from a respective source line SLO-SLM to output nodes 1308(0)-1308(m) as a function of the respective line voltage V ₀ -V _m driven to the NVM bit cell circuits Roo-R _nm in their respective memory column Co-C _m divided by the parallel channel resistances of the NVM bit cell circuits Roo-R _nm in a respective memory column Co-C _m . As shown in Figure 13, each NVM bit cell circuit Roo-R _nm in an NVM storage string circuit 1302(0)- 1302(m) comprises a source node (or drain node) coupled to a corresponding bit line BLo-BL _m and a drain node (or source node) coupled to a corresponding source line SLo-SL _m to be configured to be coupled in parallel with other NVM bit cell circuits Roo-R _nm in a respective memory column Co-C _m . Thus for example, current Io flowing on a respective source line SLo to the output node 1308(0) is a function of the sum of the dot product multiplications, meaning a respective input vector Xo-X _n is multiplied by the corresponding memory states in NVM bit cell circuits Roo-Ro _n in their respective, corresponding memory column Co-C _m . The currents Io-I _m may be analog representations of a summation of the dot product multiplications which can be converted to binary values. In other words, the NVM matrix circuit 1300 is configured to produce currents Io-I _m on an input layer according to the following formula: where:

i = memory column 0 to m;

j = memory row 0 to n;

VBL = voltage V;; and

Ri _j = channel resistance of an NVM bit cell circuit.

[0075] If the word lines WL ₀ -WL _m are coupled to a pre-neuron layer and the output nodes 1308(0)- 1308(m) are coupled to a post- neuron layer, the NVM matrix circuit 1300 is also configured to train the channel resistance of the NVM bit cell circuits Roo- R _mn by supporting backwards propagation of a weight update according to the following formula:

^{~ '} $ postj ^' $ ' post+l,j

where:

Ri _j = channel resistance of an NVM bit cell circuit; and S = value at source lines of NVM storage string circuits.

[0076] Figure 14 illustrates another NVM matrix circuit 1400 that is also a reconfiguration of the NVM matrix circuit 300 in Figure 3A into an n x m matrix by switching the memory rows and columns to have memory row Ro-R _n and memory columns Co-C _m . The NVM matrix circuit 1400 includes NVM storage string circuits 1402(0)-1402(m) in the form of AND NVM resistive random access memory (RRAM) circuits in this example, which are provided in respective memory columns Co-C _m to provide NVM bit cell circuits Roo-R _nm - Thus, each NVM bit cell circuit Roo-R _nm is an NVM RRAM circuit. The word lines WL ₀ _WL _n and bit lines BL ₀ _BL _m are reversed between memory rows Ro-R _n and columns Co-C _m from the NVM matrix circuit 300 in Figure 3A, but are still coupled to the NVM bit cell circuits Roo-R _nm in the same manner as in the NVM matrix circuit 300 in Figure 3A. In this regard, as shown in Figure 14, word lines WLo-WL _n that receive input vectors Xo-X _n in the form of input voltages are provided for each memory row Ro-R _n - The bit lines BLo-BL _m are provided for each memory column Co-C _m . Common components between the NVM matrix circuit 300 in Figure 3 A and the NVM matrix circuit 1400 in Figure 14 are shown with common element numbers and thus will not be re-described. Read and write operations similar to that described above with regard to the NVM matrix circuit 300 can be performed in the NVM matrix circuit 1400 in Figure 14.

[0077] Each NVM bit cell circuit Roo-R _nm has a resistance representing a stored memory state. In this example, the resistances of the NVM bit cell circuits Roo-R _nm are a function of the resistance of the NVM bit cell circuits Roo-R _nm based on their memory state. The resistances of the NVM bit cell circuits Roo-R _nm represent a weight matrix. Each NVM bit cell circuit Roo-R _nm has a transistor comprising a gate node Goo-G _nm that is coupled to a respective word line WLo-WL _n based on in which memory row Ro-R _n the NVM bit cell circuit Roo-R _nm is located. Each NVM bit cell circuit Roo-R _nm is configured to activate its semiconductor channel to couple the MTJ resistance (i.e., conductance) between the respective bit lines BLo-BL _m and the respective source lines SLo-SL _m in parallel with other activated NVM bit cell circuit Roo-R _nm in the same memory column Co-C _m . Current Io-I _m flows from a respective source line SLo-SL _m to output nodes 1408(0)- 1408(m) as a function of the respective line voltage Vo-V _m driven to the NVM bit cell circuits R ₀ o-R _nm in their respective memory column Co-C _m divided by the parallel channel resistances of the NVM bit cell circuits R ₀ o-R _nm in a respective memory column Co-C _m . As shown in Figure 14, each NVM bit cell circuit Roo-R _nm in an NVM storage string circuit 1402(0)-1402(m) comprises a source node (or drain node) coupled to a corresponding bit line BLo-BL _m and a drain node (or source node) coupled to a corresponding source line SLo-SL _m to be configured to be coupled in parallel with other NVM bit cell circuits Roo-R _nm in a respective memory column Co-C _m . Thus for example, current Io flowing on a respective source line SLo to the output node 1408(0) is a function of the sum of the dot product multiplications, meaning a respective input vector Xo-X _n is multiplied by the corresponding memory states in NVM bit cell circuits Roo-Ro _n in their respective, corresponding memory column Co-C _m . The currents Io-I _m may be analog representations of a summation of the dot product multiplications which can be converted to binary values. In other words, the NVM matrix circuit 1400 is configured to produce currents Io-I _m on an input layer according to the following formula: 'j =∑v

i «. '«v

where:

i = memory column 0 to m;

j = memory row 0 to n;

VBL = voltage V;; and

Ri _j = channel resistance of an NVM bit cell circuit.

[0078] If the word lines WLo-WL _m are coupled to a pre-neuron layer and the output nodes 1408(0)-1408(m) are coupled to a post-neuron layer, the NVM matrix circuit 1400 is also configured to train the channel resistance of the NVM bit cell circuits Roo- Rmn by supporting backwards propagation of a weight update according to the following formula:

Rjj - Spostj ^' Spost+l

where:

Ri _j = channel resistance of an NVM bit cell circuit; and S = value at source lines of NVM storage string circuits.

[0079] Figure 15 is a schematic diagram of another exemplary NVM matrix circuit 1500 that can perform matrix multiplication without the use of cross-bar connections employing OR-based NVM storage string circuits 1502(0)- 1502(m) provided as NOR NVM flash circuits in this example. In this manner, as discussed below, the summed channel conductances affect the currents Io-I _m to flow to output nodes 1508(0)- 1508(m) representing dot product matrix multiplication calculations. In this regard, the NVM matrix circuit 1500 employs NVM storage string circuits 1502(0)-1502(m) in 'm+ memory rows Ro-R _m that each include a plurality of NVM bit cell circuits Roo-Rmn- Thus, the NVM bit cell circuits Roo-Rmn are arranged in memory rows Ro-R _m and memory columns Co-C _n . The NVM matrix circuit 1500 includes a respective word line WLo-WL _m for each memory row Ro-R _m - Word line driver circuits 1506(0)- 1506(m) are provided that are each configured to drive a respective voltage Vo-V _m on the respective word lines WLo-WL _m . Source lines SLo-SL _m for each NVM storage string circuit 1502(0)-1502(m) include respective output nodes 1508(0)-1508(m). The source lines SLo-SL _m are configured to provide a respective current Io-I _m to the respective output nodes 1508(0)- 1508(m) to be provided as an output vector So-S _m . For example, the output vector So-S _m may be a binary post-synapse vector. The NVM matrix circuit 1500 also includes a respective bit line BLo-BL _n for each memory column Co-C _n in this example. For example, the input vector Xo-X _n may be a binary pre-synapse vector. Bit line driver circuits 1510(0)-1510(n) are provided that are each configured to drive a respective input vector Xo-X _n in the form of input voltages on the respective bit lines BLo-BL _n in this example. Note however that alternatively, the word lines WLo-WL _m provided in the respective memory rows Ro-R _m could be configured to receive the input vector X, and respective fixed voltages be applied to the bit lines BLo-BL _n in the respective memory columns Co-C _n with the respective voltages Vo-V _m applied.

[0080] With continuing reference to Figure 15, each NVM bit cell circuit Roo-Rmn has a conductance representing a stored memory state. The series conductances of the NVM bit cell circuits Roo-R _mn in Figure 15 represent a weight matrix. Each NVM bit cell circuit Roo-Rmn in this example has a transistor comprising a gate node Goo-G _mn that is coupled to a respective word line WL ₀ -WL _m based on which memory row Ro-R _m the NVM bit cell circuit R ₀ o-R _m n is located. Each NVM bit cell circuit R ₀ o-Rmn is configured to activate its respective semiconductor channel on a respective source line SLo-SL _m to couple its conductance on the respective source line SLo-SL _m . The current Io-Im flowing from the respective NVM storage string circuits 1502(0)-1502(m) on the respective source lines SLo-SL _m to output nodes 1508(0)- 1508(m) is a function of the respective voltages Vo-V _m driven by the word line driver circuits 1506(0)-1506(m) on respective word lines WLo-WL _m divided by the summed conductances of the NVM bit cell circuits Roo-Rmn- Thus for example, current Io flowing on a respective source line SLo to the output node 1508(0) is a function of the sum of the dot product multiplications, meaning an input vector Xo-X _n is multiplied by the corresponding memory states in the NVM bit cell circuits Roo-Ron- The currents Io-I _m rnay be analog representations of a summation of the dot product multiplications which can be converted to binary values. In other words, the NVM matrix circuit 1500 is configured to produce currents Io-I _m according to the following formula:

j

where:

i = memory row 0 to m;

j = memory column 0 to n;

V _BL = voltage V _j ; and

Gi _j = conductance of an NVM bit cell circuit.

[0081] The conductances Gi _j of the respective NVM bit cell circuits Roo-Rmn correlate to the voltages Vo-V _m applied to the word lines WLo-WL _m . If the bit lines BLo-BL _n are coupled to a pre-neuron layer and the output nodes 1508(0)-1508(m) are coupled to a post-neuron layer, the NVM matrix circuit 1500 is also configured to train the channel resistance of the NVM bit cell circuits Roo-R _mn by supporting backwards propagation of a weight update according to the following formula:

— J] - S postj ^' Spost+l,j where:

Gi _j = conductance of an NVM bit cell circuit; and

S = source lines of NVM storage string circuits.

[0082] Read and write operations similar to that described above with regard to the NVM matrix circuit 300 in Figure 3 A can be performed in the NVM matrix circuit 1500 in Figure 15.

[0083] Other types of NVM bit cell circuits can be employed besides NOR flash circuits like shown in the NVM matrix circuit 1500 in Figure 15. For example, Figure 16 is a schematic diagram of another exemplary matrix circuit 1600 without need for cross-bar connections like the NVM matrix circuit 1500 in Figure 15. However, the NVM matrix circuit 1600 in Figure 16 includes NVM storage string circuits 1602(0)- 1602(m) in the form of NOR NVM FeFET circuits. Each NVM storage string circuit 1602(0)-1602(m) includes an NVM matrix circuit Roo-Rmn in the form of NVM Fe-FET circuits in this example. Common components between the NVM matrix circuit 1500 in Figure 15 and the NVM matrix circuit 1600 in Figure 16 are shown with common element numbers and thus will not be re-described. Read and write operations similar to that described above with regard to the NVM matrix circuit 300 in Figure 3A can be performed in the NVM matrix circuit 1600 in Figure 16.

[0084] Figure 17 is a schematic diagram of another exemplary NVM matrix circuit 1700 that can perform matrix multiplication without the use of cross-bar connections employing OR-based NVM storage string circuits 1702(0)-1702(m) provided as NOR NVM MRAM circuits in this example. In this manner, as discussed below, the summed conductances of the MTJs in the NVM storage string circuits 1702(0)-1702(m) affect the currents Io-I _m to flowing to output nodes 1708(0)- 1708(m) representing dot product matrix multiplication calculations. In this regard, the NVM matrix circuit 1700 employs NVM storage string circuits 1702(0)-1702(m) in 'm+ memory rows Ro-R _m that each include a plurality of NVM bit cell circuits Roo-R _mn - Thus, the NVM bit cell circuits Roo-Rmn are arranged in memory rows Ro-R _m and memory columns Co-C _n . The NVM matrix circuit 1700 includes a respective word line WLo-WL _m for each memory row Ro- Rm. Word line driver circuits 1706(0)-1706(m) are provided that are each configured to drive a respective voltage Vo-V _m on the respective word lines WLo-WL _m . Source lines SL ₀ -SL _m for each NVM storage string circuit 1702(0)- 1702(m) include respective output nodes 1708(0)-1708(m). The source lines SL ₀ -SL _m are configured to provide a respective current Io-I _m to the respective output nodes 1708(0)-1708(m) to be provided as an output vector So-S _m . For example, the output vector So-S _m may be a binary post- synapse vector. The NVM matrix circuit 1700 also includes a respective bit line BLo- BLn for each memory column Co-C _n in this example. Bit line driver circuits 1710(0)- 1710(n) are provided that are each configured to drive a respective input vector Xo-X _n in the form of input voltages on the respective bit lines BLo-BL _n in this example. Note however that alternatively, the word lines WLo-WL _m provided in the respective memory rows Ro-Rm could be configured to receive the input vector X, and respective fixed voltages be applied to the bit lines BLo-BLn in the respective memory columns Co-C _n with the respective voltages Vo-V _m applied. For example, the input vector Xo-X _n may be a binary pre-synapse vector.

[0085] With continuing reference to Figure 17, each NVM bit cell circuit Roo-Rmn has a conductance representing a stored memory state. The series conductances of the NVM bit cell circuits Roo-Rmn in Figure 17 represent a weight matrix. Each NVM bit cell circuit Roo-R _mn in this example has a transistor comprising a gate node Goo-G _mn that is coupled to a respective word line WLo-WL _m based on which memory row Ro-R _m the NVM bit cell circuit R ₀ o-R _mn is located. Each NVM bit cell circuit R ₀ o-R _mn is configured to activate its respective semiconductor channel on a respective source line SLo-SL _m to couple the conductance of its respective MTJ on the respective source line SLo-SL _m . The current Io-I _m flowing from the respective NVM storage string circuits 1702(0)-1702(m) on the respective source lines SLo-SL _m to output nodes 1708(0)- 1708(m) is a function of the respective voltages Vo-V _m driven by word line driver circuits 1706(0)- 1706(m) on respective word lines WLo-WL _m divided by the summed conductances of the NVM bit cell circuits Roo-R _mn - Thus for example, current Io flowing on a respective source line SLo to the output node 1708(0) is a function of the sum of the dot product multiplications, meaning input vector Xo-X _n is multiplied by the corresponding memory states in the NVM bit cell circuits Roo-Ro _n - The currents Io-I _m may be analog representations of a summation of the dot product multiplications which can be converted to binary values. In other words, the NVM matrix circuit 1700 is configured to produce currents Io-I _m according to the following formula: where:

i = memory row 0 to m;

j = memory column 0 to n;

VBL = voltage V _j ; and

Gij = conductance of an NVM bit cell circuit.

[0086] The conductances Gy of the respective NVM bit cell circuits Roo-R _mn correlate to the voltages Vo-V _m applied to the word lines WLo-WL _m . If the bit lines BLo-BL _n are coupled to a pre-neuron layer and the output nodes 1708(0)- 1708(m) are coupled to a post-neuron layer, the NVM matrix circuit 1700 is also configured to train the channel resistance of the NVM bit cell circuits Roo-R _mn by supporting backwards propagation of a weight update according to the following formula: post,i post+l,j where:

= conductance of an NVM bit cell circuit; and source lines of NVM storage string circuits.

[0087] Figure 18 is a schematic diagram of another exemplary NVM matrix circuit 1800 that can perform matrix multiplication without the use of cross-bar connections employing OR-based NVM storage string circuits 1802(0)- 1802(m) provided as NOR NVM RRAM circuits in this example. In this manner, as discussed below, the summed conductances of the NVM storage string circuits 1802(0)- 1802(m) affect the currents ¾- I _m to flowing to output nodes 1808(0)- 1808(m) representing dot product matrix multiplication calculations. In this regard, the NVM matrix circuit 1800 employs NVM storage string circuits 1802(0)- 1802(m) in 'm+ memory rows Ro-R _m that each include a plurality of NVM bit cell circuits Roo-Rmn- Thus, the NVM bit cell circuits Roo-Rmn are arranged in memory rows Ro-R _m and memory columns Co-C _n . The NVM matrix circuit 1800 includes a respective word line WL ₀ -WL _m for each memory row Ro-R _m - Word line driver circuits 1806(0)- 1806(m) are provided that are each configured to drive a respective voltage Vo-V _m on the respective word lines WLo-WL _m . Source lines SLo-SL _m for each NVM storage string circuit 1802(0)- 1802(m) include respective output nodes 1808(0)- 1808(m). The source lines SLo-SL _m are configured to provide a respective current Io-I _m to the respective output nodes 1808(0)- 1808(m) to be provided as an output vector So-S _m . For example, the output vector So-S _m may be a binary post- synapse vector. The NVM matrix circuit 1800 also includes a respective bit line BLo- BLn for each memory column Co-C _n in this example. Bit line driver circuits 1810(0)- 1810(n) are provided that are each configured to drive a respective input vector Xo-X _n in the form of input voltages on the respective bit lines BLo-BL _n in this example. Note however that alternatively, the word lines WLo-WL _m provided in the respective memory rows Ro-Rm could be configured to receive the input vector X, and respective fixed voltages be applied to the bit lines BLo-BLn in the respective memory columns Co-C _n with the respective voltages Vo-V _m applied. For example, the input vector Xo-X _n may be a binary pre-synapse vector. [0088] With continuing reference to Figure 18, each NVM bit cell circuit Roo-R _mn has a conductance representing a stored memory state. The series conductances of the NVM bit cell circuits R ₀ o-R _mn in Figure 18 represent a weight matrix. Each NVM bit cell circuit R ₀ o-R _mn in this example has a transistor comprising a gate node Goo-G _mn that is coupled to a respective word line WLo-WL _m based on which memory row Ro-R _m the NVM bit cell circuit Roo-R _mn is located. Each NVM bit cell circuit Roo-Rmn is configured to activate its respective semiconductor channel on a respective source line SLo-SL _m to couple the conductance of its respective MTJ on the respective source line SLo-SL _m . The current Io-I _m flowing from the respective NVM storage string circuits 1802(0)- 1802(m) on the respective source lines SLo-SL _m to output nodes 1808(0)- 1808(m) is a function of the respective voltages Vo-V _m driven by the word line driver circuits 1806(0)- 1806(m) on respective word lines WLo-WL _m divided by the summed conductances of the NVM bit cell circuits Roo-R _mn - Thus for example, current Io flowing on a respective source line SLo to the output node 1808(0) is a function of the sum of the dot product multiplications, meaning input vector Xo-X _n is multiplied by the corresponding memory states in the NVM bit cell circuits Roo-Ro _n - The currents Io-I _m may be analog representations of a summation of the dot products which can be converted to binary values. In other words, the NVM matrix circuit 1800 is configured to produce currents Io-I _m according to the following formula:

where:

i = memory row 0 to m;

j = memory column 0 to n;

VBL = voltage V _j ; and

Gij = conductance of an NVM bit cell circuit.

[0089] The conductances Gy of the respective NVM bit cell circuits Roo-R _mn correlate to the voltages Vo-V _m applied to the word lines WLo-WL _m . If the bit lines BLo-BL _n are coupled to a pre-neuron layer and the output nodes 1808(0)- 1808(m) are coupled to a post-neuron layer, the NVM matrix circuit 1800 is also configured to train the channel resistance of the NVM bit cell circuits Roo-R _mn by supporting backwards propagation of a weight update according to the following formula:

— J] - S postj ^' Spost+l,j where:

Gi _j = conductance of an NVM bit cell circuit; and

S = source lines of NVM storage string circuits.

[0090] Figure 19 is a block diagram of an exemplary chip package 1900 that can include a dedicated matrix circuit chip 1902 that has an NVM matrix circuit 1904 for performing matrix computations without need for cross-bar connections and according to aspects disclosed herein including without limitation the NVM matrix circuits in Figures 3A-18. In this regard, a system-on-a-chip (SoC) 1906 may be included that can contain a microprocessor and other supporting circuitry to provide a computer system. An external system memory chip 1908, such as a dynamic RAM (DRAM) memory chip may be provided in the chip package 1900 and coupled to the SoC 1906 through through- silicon vias (TSVs) 1910. The dedicated matrix circuit chip 1902 may also be coupled to the SoC 1906 through the TSVs 1910. Solder bumps 1912 may be provided on the SoC 1906 to be able to solder-bond the chip package 1900 to a circuit board. The system memory chip 1908 could be connected to the dedicated matrix circuit chip 1902 through a dedicated local bus to improve performance. The dedicated matrix circuit chip 1902 could also be embedded into the SoC 1906 to save power and improve performance.

[0091] In another aspect, an NVM matrix circuit may be provided that includes a plurality of means for applying a plurality of input voltages representing an input vector. As non- limiting examples, the means for applying a plurality of input voltages representing an input vector may be the word lines WLo-WL _n in the NVM matrix circuit 300 in Figures 3A-7B, the word lines WL ₀ -WL _n in the NVM matrix circuit 1100 in Figure 11, the word lines WLo-WL _n in the NVM matrix circuit 1200 in Figure 12, the word lines WLo-WL _n in the NVM matrix circuit 1300 in Figure 13, the word lines WLo- WL _n in the NVM matrix circuit 1400 in Figure 14, the word lines WLo-WL _m in the NVM matrix circuit 1500 in Figure 15, the word lines WLo-WL _m in the NVM matrix circuit 1600 in Figure 16, the word lines WLo-WL _m in the NVM matrix circuit 1700 in Figure 17, or the word lines WLo-WL _m in the NVM matrix circuit 1800 in Figure 18.

[0092] The NVM matrix circuit may also include a plurality of means for applying a plurality of line voltages. As non-limiting examples, the means for applying a plurality of line voltages may be the bit lines BLo-BL _m in the NVM matrix circuit 300 in Figures 3A-7B, the bit lines BLo-BL _m in the NVM matrix circuit 1100 in Figure 11, the bit lines BLo-BL _m in the NVM matrix circuit 1200 in Figure 12, the bit lines BLo-BL _m in the NVM matrix circuit 1300 in Figure 13, the bit lines BLo-BL _m in the NVM matrix circuit 1400 in Figure 14, the bit lines BL ₀ -BL _n in the NVM matrix circuit 1500 in Figure 15, the bit lines BLo-BL _n in the NVM matrix circuit 1600 in Figure 16, the bit lines BLo- BL _n in the NVM matrix circuit 1700 in Figure 17, or the bit lines BL ₀ -BL _n in the NVM matrix circuit 1800 in Figure 18. As other non- limiting examples, the means for applying a plurality of line voltages may be the source lines SLo-SL _m in the NVM matrix circuit 300 in Figures 3A-7B, the source lines SLo-SL _m in the NVM matrix circuit 1100 in Figure 11, the source lines SLo-SL _m in the NVM matrix circuit 1200 in Figure 12, the source lines SLo-SL _m in the NVM matrix circuit 1300 in Figure 13, the source lines SL ₀ -SL _m in the NVM matrix circuit 1400 in Figure 14, the source lines SLo- SL _n in the NVM matrix circuit 1500 in Figure 15, the source lines SL ₀ -SL _n in the NVM matrix circuit 1600 in Figure 16, the source lines SLo-SL _n in the NVM matrix circuit 1700 in Figure 17, or the source lines SLo-SL _n in the NVM matrix circuit 1800 in Figure 18.

[0093] The NVM matrix circuit may also include a plurality of means for providing a plurality of output currents representing an output vector. As non-limiting examples, the means for providing a plurality of output currents may be the source lines SLo-SL _m in the NVM matrix circuit 300 in Figures 3A-7B, the source lines SLo-SL _m in the NVM matrix circuit 1100 in Figure 11, the source lines SLo-SL _m in the NVM matrix circuit 1200 in Figure 12, the source lines SLo-SL _m in the NVM matrix circuit 1300 in Figure 13, the source lines SLo-SL _m in the NVM matrix circuit 1400 in Figure 14, the source lines SLo-SL _n in the NVM matrix circuit 1500 in Figure 15, the source lines SLo-SL _n in the NVM matrix circuit 1600 in Figure 16, the source lines SLo-SL _n in the NVM matrix circuit 1700 in Figure 17, or the source lines SLo-SL _n in the NVM matrix circuit 1800 in Figure 18. As other non-limiting examples, the means for providing a plurality of output currents may be the bit lines BLo-BL _m in the NVM matrix circuit 300 in Figures 3A-7B, the bit lines BLo-BL _m in the NVM matrix circuit 1100 in Figure 11, the bit lines BLo-BL _m in the NVM matrix circuit 1200 in Figure 12, the bit lines BL ₀ -BL _m in the NVM matrix circuit 1300 in Figure 13, the bit lines BL ₀ -BL _m in the NVM matrix circuit 1400 in Figure 14, the bit lines BL ₀ -BL _n in the NVM matrix circuit 1500 in Figure 15, the bit lines BLo-BL _n in the NVM matrix circuit 1600 in Figure 16, the bit lines BLo- BLn in the NVM matrix circuit 1700 in Figure 17, or the bit lines BL ₀ -BL _n in the NVM matrix circuit 1800 in Figure 18.

[0094] The NVM matrix circuit may also include a plurality of NVM storage string means each electrically coupled to a corresponding means for applying an input voltage among the plurality of means for applying the plurality of input voltages and a corresponding means for providing an output current among the plurality of means for providing the plurality of output currents. As non-limiting examples, the plurality of NVM storage string means may include the NVM storage string circuits 302(0)-302(m) in Figures 3A-7B, the NVM storage string circuits 1002(0)- 1002(m) in Figure 10, the NVM storage string circuits 1102(0)-1102(m) in Figure 11, the NVM storage string circuits 1202(0)- 1202(m) in Figure 12, the NVM storage string circuits 1302(0)- 1302(m) in Figure 13, the NVM storage string circuits 1402(0)- 1402(m) in Figure 14, the NVM storage string circuits 1502(0)-1502(n) in Figure 15, the NVM storage string circuits 1602(0)- 1602(n) in Figure 16, the NVM storage string circuits 1702(0)- 1702(n) in Figure 17, or the NVM storage string circuits 1802(0)- 1802(n) in Figure 18.

[0095] Each of the plurality of NVM storage string means may comprise a plurality of NV means for storing a memory state each having a resistance representing the stored memory state to form a data vector for a corresponding NVM storage string means, each plurality of plurality NV means for storing the memory state, and comprising a means for electrically coupling the resistance of the NV means for storing the memory state to a means for providing the output current among the plurality of means for providing the plurality of output currents; and a means for controlling coupling of the resistance of the plurality of NV means for storing the memory state to the means for providing the output current among the plurality of means for providing the plurality of output currents. As non-limiting examples, the plurality of NV means for storing a memory state may include the NVM bit cell circuits Roo-R _mn in Figures 3A-7B, the NVM bit cell circuits Roo-R _mn in Figure 10, the NVM bit cell circuits Roo-R _mn in Figure 11 , the NVM bit cell circuits Roo-R _nm in Figure 12, the NVM bit cell circuits Roo-R _nm in Figure 13, the NVM bit cell circuits Roo-Rnm in Figure 14, the NVM bit cell circuits Roo-Rmn in Figure 15, the NVM bit cell circuits R ₀ o-R _m n in Figure 16, the NVM bit cell circuits Roo- Rmn in Figure 17, or the NVM bit cell circuits Roo-R _mn in Figure 18.

[0096] The NVM matrix circuit may also include a plurality of access means for controlling the means for electrically coupling the corresponding means for applying the input voltage among the plurality of means for applying the plurality of input voltages to a corresponding NVM storage string means in the coupling of the resistance of the plurality of NV means for storing the memory state to the means for providing the output current among the plurality of means for providing the plurality of output currents. Non-limiting examples of the plurality of access means include the access transistor(s) 312(0)-312(m), 318(0)-318(m) in the NVM matrix circuit 300 in Figures 3A and 4A-7B or the access transistor(s) 312(0)-312(m), 1018(0)-1018(m) in the NVM matrix circuit 1000 in Figure 10.

[0097] NVM matrix circuits employing NVM matrix circuits for performing matrix computations without need for cross-bar connections and according to aspects disclosed herein, may be provided in or integrated into any processor-based device. Examples, without limitation, include a set top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smart phone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device (e.g., a smart watch, a health or fitness tracker, eyewear, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, avionics systems, a drone, and a multicopter.

[0098] In this regard, Figure 20 illustrates an example of a processor-based system 2000 that can be included in an IC 2002. The processor-based system 2000 can include NVM matrix circuits 2004 employing NVM bit cell circuits for performing matrix computations without need for cross-bar connections and according to any aspects disclosed herein. The IC 2002 may be included in or provided as a SoC 2006. The processor-based system 2000 includes a CPU 2008 that includes one or more processors 2010. The CPU 2008 may have a cache memory 2012 coupled to the processor(s) 2010 for rapid access to temporarily stored data. The cache memory 2012 can include the NVM matrix circuits 2004 according to any of the examples disclosed herein. The CPU 2008 is coupled to a system bus 2014 and can intercouple master and slave devices included in the processor-based system 2000. As is well known, the CPU 2008 communicates with these other devices by exchanging address, control, and data information over the system bus 2014. Although not illustrated in Figure 20, multiple system buses 2014 could be provided, wherein each system bus 2014 constitutes a different fabric. For example, the CPU 2008 can communicate bus transaction requests to a memory system 2016 as an example of a slave device. The memory system 2016 may include a memory array 2018 that includes memory bit cells 2020. The memory bit cells 2020 may be MRAM bit cells for example. The memory array 2018 can include the NVM matrix circuits 2004.

[0099] Other master and slave devices can be connected to the system bus 2014. As illustrated in Figure 20, these devices can include the memory system 2016, and one or more input devices 2022. The input device(s) 2022 can include any type of input device, including but not limited to input keys, switches, voice processors, etc. The other devices can also include one or more output devices 2024, and one or more network interface devices 2026. The output device(s) 2024 can include any type of output device, including but not limited to audio, video, other visual indicators, etc. The other devices can also include one or more display controllers 2030 as examples. The network interface device(s) 2026 can be any devices configured to allow exchange of data to and from a network 2028. The network 2028 can be any type of network, including but not limited to a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTH™ network, and the Internet. The network interface device(s) 2026 can be configured to support any type of communications protocol desired.

[00100] The CPU 2008 may also be configured to access the display controller(s) 2030 over the system bus 2014 to control information sent to one or more displays 2032. The display controller 2030 can include the NVM matrix circuits 2004. The display controller(s) 2030 sends information to the display(s) 2032 to be displayed via one or more video processors 2034, which process the information to be displayed into a format suitable for the display(s) 2032. The display(s) 2032 can include any type of display, including but not limited to a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, etc.

[00101] Those of skill in the art will further appreciate that the various illustrative logic blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein may be implemented as electronic hardware, instructions stored in memory or in another computer readable medium and executed by a processor or other processing device, or combinations of both. The master devices and slave devices described herein may be employed in any circuit, hardware component, integrated circuit (IC), or IC chip, as examples. Memory disclosed herein may be any type and size of memory and may be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends upon the particular application, design choices, and/or design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

[00102] The various illustrative logic blocks, modules, and circuits described in connection with the aspects disclosed herein may be implemented or performed with a processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration). [00103] The aspects disclosed herein may be embodied in hardware and in instructions that are stored in hardware, and may reside, for example, in Random Access Memory (RAM), flash memory, Read Only Memory (ROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), registers, a hard disk, a removable disk, a CD-ROM, or any other form of computer readable medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. In the alternative, the processor and the storage medium may reside as discrete components in a remote station, base station, or server.

[00104] It is also noted that the operational steps described in any of the exemplary aspects herein are described to provide examples and discussion. The operations described may be performed in numerous different sequences other than the illustrated sequences. Furthermore, operations described in a single operational step may actually be performed in a number of different steps. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It is to be understood that the operational steps illustrated in the flowchart diagrams may be subject to numerous different modifications as will be readily apparent to one of skill in the art. Those of skill in the art will also understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[00105] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.