NOVEL METALLIZATION SIDEWALL PASSIVATION

TECHNOLOGY FOR DEEP SUB-HALF MICROMETER

IC APPLICATIONS

TECHNICAL FIELD

The present invention relates generally to aluminum interconnects which are used for connecting IC (integrated circuit) devices formed in semiconductor wafers, and, more particularly , to electromigration-induced pile-up in aluminum interconnects

BACKGROUND ART

Several trends in state of the art integrated circuit design have been proposed or are already being incor¬ porated in current integrated circuits In one approach, in order to increase integrated circuit speed, circuit design¬ ers have proposed to reduce the chip size, thereby lowering the RC time constant of the integrated circuits In an¬ other approach, process technologists have proposed the use of low dielectnc constant insulating mateπal to lower the capacitive coupling between metal interconnects In still another approach, the spacing between the metal m- terconnects in the same metal layer is becoming smaller and smaller in order to accommodate higher packing density

Additionally, to accommodate higher packing density in present integrated circuits, metal connections to integrated circuit devices formed in a semiconductor substrate are made by multilayer interconnects Aluminum- based metallization is typically used in current technology to form the metal layers which are patterned into the aluminum lines or aluminum interconnects These aluminum interconnects are used to connect integrated circuit devices Each level of multilayer interconnects is supported over the semiconductor substrate by an interlevel di¬ electnc

Low dielectnc constant insulating mateπal can be used to provide both lower inter-metal layer capaci¬ tance coupling and lower intra-metal layer capacitance coupling Inter-metal layer capacitance coupling corre- sponds to capacitive coupling between different layers of aluminum separated by an mterlayer dielectric To lower the inter-metal capacitive coupling, low dielectric constant insulating mateπal is used to form the mterlayer dielec-

tne Intra-metal layer capacitance coupling corresponds to capacitive coupling between aluminum interconnects with a single layer of aluminum To lower the intra-metal capacitive coupling, these aluminum interconnects are also separated by the low dielectnc constant insulating mateπal

Use of low dielectnc constant insulating matenal, as well as reduction in chip size and reduction in spacing between aluminum interconnects in the same layer of aluminum, all reduce the reliability of the integrated circuits Integrated circuits which have incoφorated these three trends in integrated circuit design have been re¬ ported to be sensiUve to an electromigration failure mode This electromigration failure mode involves the forma¬ Uon of lateral shorts between aluminum interconnects produced by electromigration These lateral shorts are pro¬ duced by the formation of pile-ups, hillocks, or extrusions in aluminum interconnects caused by electromigration Pile-ups, hillocks, and extrusions refer to a physical deformations in the aluminum interconnects The terms "pile-up", "hillock", and "extrusion" are just different descnptions of the same observaϋon It will be readily apparent to those skilled in the art that these terms can be used interchangeably In particular, these terms refer to the build-up of aluminum in one location of the aluminum interconnect The build-up of aluminum in the case of the electromigration failure mode discussed above results from the transport of aluminum to one location via elec- tromigration

Low Young's modulus for low dielectnc constant insulating mateπals is cited as the reason for the in¬ creased sensiUvity to this electromigration failure mode Young's modulus is generally low for low dielectnc con¬ stant matenal Accordingly, these low dielectnc constant insulating mateπals are not strong enough to resist pile- up of matenal transported under electromigration The reduced chip size and the accompanying reduction in spacing between aluminum interconnects in the same layer of aluminum increases the likelihood that a pile-up will result in a lateral short

Two solutions have been offered by many technologists to prevent the formation of the lateral shorts be¬ tween aluminum interconnects as a result of electromigration The first solution is to dope the aluminum-based metallization with alloying additions such as Cu, Ti, etc Evidence shows that several such alloying additions re- tard the failure processes such as voiding and pile-up formaUon caused by electromigraϋon The second solution is to provide a strong liner comprising either Sι0 ₂ or Sι ₃ N ₄ which surrounds each aluminum interconnect The strong liner is deposited on the aluminum interconnects prior to the deposition of the low dielectnc constant insu¬ lating matenal The strong liner resists pile-up of aluminum transported via electromigration Both solutions, however, have drawbacks The first solution may prevent the voiding and pile-up problems caused by electromigration The effects of these alloying additions, however, on the stress-induced voiding failure mechanism is unclear Stress-induced voiding is more complicated than electromigration-induced voiding Stress-induced voiding aπses due to the thermal mismatch of the matenals employed in the formaUon of the aluminum interconnects and the surrounding dielectnc Voids form in the aluminum, thereby relaxing the stress caused by the thermal mismatch Another drawback of the use of alloyed-aluminum in the first solution is that the etchability of these new aluminum alloys is unclear

The second solution is a workable solution The trade-off, however, is more complex processing Addi- Uonally, the effective dielectnc constant of the resultant mateπal system will be higher The dielectnc

constant includes contributions from the dielectric constants for the low dielectric constant insulating material and for the strong liner. The dielectric constant for Si0 ₂ is about 4.0. The dielectric constant for Si ₃ N ₄ is about 8.0. These values of the dielectric constants for Si0 ₂ and for Si ₃ N ₄ exceed the values of the dielectric constants of low dielectric constant insulating materials. Accordingly, the effective dielectric constant, which as described above includes contributions from the constituent dielectrics, is higher than the dielectric constant of the low dielectric constant insulating material alone.

Thus, there remains a need for a method for preventing the formation of lateral shorts between aluminum interconnects caused by electromigration which avoids most, if not all, the foregoing problems.

DISCLOSURE OF INVENTION

In accordance with the invention, a method is provided for forming at least one metal interconnect struc¬ ture which resists the formation of pile-ups caused by electromigration. The metal interconnect structure is formed on an insulating layer formed over a semiconductor substrate. The method comprises the steps of: (a) forming a first refractory metal layer on the insulating layer;

(b) forming a layer of aluminum on the first refractory metal layer;

(c) forming a second refractory metal layer on the layer of aluminum;

(d) patterning the second refractory metal layer, the layer of aluminum and the first refractory layer, thereby forming at least one aluminum interconnect sandwiched between the patterned first refractory metal layer and the patterned second refractory metal layer, each aluminum interconnect having sidewalls comprising exposed aluminum; and

(e) forming a layer of aluminum intermetallic alloy comprising aluminum-refractory metal alloy on the sidewalls of the aluminum interconnects by reacting the exposed aluminum on the sidewalls wilh at least one refractory metal-containing precursor material, the layer of aluminum intermetallic alloy providing reinforce- ment for the sidewalls to enable the sidewalls to resist the formation of pile-ups caused by electromigration.

The method of the present invention provides a technique for strengthening the sidewalls of aluminum interconnects against the formation of electromigration-induced pile-ups. After the formation of the layer of alu¬ minum intermetallic alloy on the sidewalls, the formation of pile-ups will be suppressed. Thus, the lifetime of the aluminum interconnects is extended despite electromigration. Accordingly, the method of the present invention improves the reliability and wear resistance of integrated circuits employing aluminum interconnects. The method of the present invention will be especially useful when used in conjunction with softer low dielectric constant insu¬ lating materials. Soft dielectric offers little resistance to the formation of pile-ups. Thus, softer low dielectric con¬ stant insulating materials are more susceptible to the formation of electromigration-induced lateral shorts.

The method ofthe present invention enables low dielectric constant insulating material to be used without sacrificing reliability and wear resistance of the aluminum interconnects. The used of low dielectric constant insu¬ lating material improves the signal-to-noisc ratio of the integrated circuit. As described above, the use of the low dielectric constant insulating material reduces capacitance. Thus, the use of low dielectric constant insulating ma-

tenal provides lower coupling between interconnect lines Lower coupling results in reduced overshoot and under¬ shoot of signals Accordingly, the signal-to-noise ratio is improved

Finally, the method ofthe present invention provides an efficient means for strengthening the sidewalls of the aluminum interconnects The present invention provides a method for providing sidewall reinforcement to re- sist the formaUon of pile-ups caused by electromigration that is simpler than pnor art methods The metal inter¬ connect structure of the present invention involves simpler construction than pnor art metal interconnect struc¬ tures that provide sidewall reinforcement Accordingly, the method for forming the metal interconnect structure of the present invention requires a simpler manufactunng process than pnor art solutions for preventing the forma¬ Uon of electromigration-induced pile-ups and subsequent lateral shorts Other objects, features, and advantages of the present invention will become apparent upon consideration of the following detailed descnption and accompanying drawings, in which like reference designations represent like features throughout the Figures

BRIEF DESCRIPTION OF THE DRAWINGS

The drawings referred to in this descπption should be understood as not being drawn to scale except if specifically noted Moreover, the drawings are intended to illustrate only one portion of an integrated circuit fabπ- cated in accordance with the present invention

FIG 1 is a cross-sectional view depicUng a metal interconnect structure representative of a conventional metal interconnect This metal interconnect structure is formed on an insulating layer formed over a semiconduc¬ tor substrate,

FIG 2 is a cross-secϋonal view depicting a metal interconnect structure of the present invention This metal interconnect structure is also formed on an insulating layer formed over a semiconductor substrate, and

FIG 3 is a cross-sectional view depicting a metal interconnect structure of the present invention after forming a layer of low dielectric constant insulating mateπal on the metal interconnect structure and on the insu¬ lating layer

BEST MODES FOR CARRYING OUT THE INVENTION

Reference is now made in detail to a specific embodiment of the present invention, which illustrates the best mode presently contemplated by the inventors for practicing the invenUon AlternaUve embodiments are also bnefly descπbed as applicable

Refemng now to FIG 1, wherein like reference numerals designate like elements throughout, a semicon¬ ductor substrate 10 is depicted having an insulation layer 12 formed thereon A metal interconnect structure 14 is formed on the insulation layer 12 While one metal interconnect structure 14 is shown, it will be readily apparent to those skilled in the art that in fact any number of such metal interconnect structures are formed The insulaUng layer 12 separates and electncally isolates the metal interconnect structure 14 from conducting regions (not shown) beneath the metal interconnect structure These conductive regions may comprise doped regions in the

semiconductor substrate 10, polysilicon, or patterned metal such as other metal interconnect structures 14 The in¬ sulating layer 12 may compπse field oxide foπned on the semiconductor substrate 10 or may compπse an inter- layer dielectric formed over the semiconductor substrate 10

The metal interconnect structure 14 shown in FIG 1 is representative of a conventional metal mtercon- nect which is well-known in state of the art integrated circuits The metal interconnect structure 14 compnses an aluminum interconnect 16 sandwiched between two refractory metal layers as is conventional for many aluminum interconnects The refractory metal layers include a Ti TiN stack (first refractory metal layer) 18, and an anti- reflecϋon layer (second refractory metal layer) 20 compnsing TiN, a layer of Ti and a layer TiN (1 e , Ti TiN), or a TiN/Ti/TiN stack The Ti/TiN stack 18 compπsing the first refractory metal layer is on the bottom of the alumi- num interconnect 16 The anti-reflection layer 20 compπsing the second refractory metal layer is on the top of the aluminum interconnect 16

Conventional processing techniques are employed to form the Ti TiN stack 18, the aluminum intercon¬ nect 16, and the anti-reflection layer 20 Typically the Ti TiN stack 18 is deposited, followed by the deposition of a layer of aluminum and the anti-reflection layer 20 A mask is formed on the anti-reflection layer 20 The mask (not shown) delineates a desired pattern for the metal interconnect structure 14 Conventional etching techniques are employed to etch the anti-reflection layer 20, the aluminum interconnect 16, and the Ti/TiN stack 18, thus forming the metal interconnect structure 14 FIG 1 depicts the integrated circuit after the formation of the metal interconnect structure 14 With the Ti/TiN stack 18 on the bottom of the aluminum interconnect 16 and the anti- reflection layer 20 on the top of the aluminum interconnect, the sidewalls 22 of the aluminum interconnect are ex- posed The exposed aluminum on the sidewalls 22 represents the weakest surfaces thereof Consequently, the ex¬ posed aluminum on the sidewalls 22 is prone to the formation of electromigration-induced pile-ups

The method of the present invention consists of forming on the sidewalls 22 a thin layer of hard alumi¬ num intermetallic alloy 24, as shown in FIG 2 The thin layer of hard aluminum intermetallic alloy 24, compπses an aluminum-refractory metal alloy Examples of aluminum-refractory metal alloys suitably employed as the layer of hard aluminum intermetallic alloy 24 include TιAl ₃ , WA1 ₃ , and WA1 ₆ The layer of aluminum intermetallic al¬ loy 24 is formed by allowing the exposed aluminum on the side walls 22 to react with an appropnate refractory metal-containing precursor matenal Examples of matenals suitably employed as refractory metal-containing pre¬ cursor matenals include Utanium or tungsten-containing compounds

A vaπety of these refractory metal-containing precursor mateπals exist in the foπn of metal organics or metal carbonyls Examples of mateπals suitably employed as metal carbonyls include tungsten carbonyl, molybde¬ num carbonyl, chromium carbonyl, titanium carbonyl, nickel carbonyl, maganese carbonyl, and tantalum car¬ bonyl These metal organics or metal carbonyls can be delivered in gaseous form into a reaction chamber Refrac¬ tory metal-containmg precursor mateπals are selected that will react with aluminum and not with Ti or TiN

In one embodiment of the present invention, the aluminum interconnect 16 is exposed to the refractory metal-containing precursor matenal, which is in the form of metal organics or metal carbonyls The metal organ¬ ics or metal carbonyls are delivered in gaseous form into a reaction chamber containing the aluminum intercon¬ nect 16 formed over the semiconductor substrate 10 These metal organics or metal carbonyls are allowed to react with the exposed aluminum on the sidewalls 22, using a low temperature or plasma-enhanced reaction A thermal

cycle is employed which will form an aluminum-refractory metal alloy that resists the formation of the electromi- gration-induced pile-ups

The melting point of the metal carbonyls are low, 1 e , below 200°C Additionally, some metal carbonyls such as chromium carbonyl and tungsten carbonyl sublime in vacuum As such, tπggeπng a reaction between the metal carbonyls and the exposed aluminum on the sidewalls 22 in a vacuum reaction chamber is not difficult If the reaction rate is not high enough, plasma can be employed to enhance the reaction Reaction energy is supplied in the form of plasma energy thereby speeding up the reaction rates

As shown in FIG 3, a layer of low dielectnc constant insulaUng matenal 26 is then foπned on the metal interconnect structure 14 and on the insulating layer 12 The layer of low dielectric constant insulating matenal 26 serves to electncally isolate the metal interconnect structure 14

In another embodiment of the present invention, an alternative approach is employed to react the refrac¬ tory metal-containing precursor mateπal with the exposed aluminum on the sidewalls 22 The refractory metal- containing precursor matenal is not delivered in the form of gaseous metal organics or metal carbonyls In this alternative embodiment, the layer of low dielectric constant insulating matenal 26 compnses a spin-on dielectnc The appropnate form of the refractory metal-containing precursor matenals are added into the spin-on dielectnc pnor to deposition thereof Examples of mateπals suitably employed as spm-on-dielectπcs include spin-on glasses, polyimides, fluonnated polyimides, or other types of curable polymers

In this alternative embodiment, as desenbed above, a metal interconnect structure 14 such as the one shown in FIG 1 is first formed The metal interconnect structure 14 compπses the aluminum interconnect 16 sandwiched between the

Ti/TiN stack 18, and the anϋ-reflection layer 20 The Ti TiN stack 18 is formed on the bottom of the aluminum interconnect 16 The anti-reflection layer 20 is formed on the top of the aluminum interconnect 16 As such, alu¬ minum is exposed on the sidewalls 22 of the aluminum interconnect 16

In this alternative embodiment, a spin-on dielectnc containing a refractory metal-containing precursor mateπal is then formed on the metal interconnect structure 14 and on the insulating layer 12 This spin-on dielec¬ tnc serves as the layer low dielectnc constant insulating matenal 26 The spin-on dielectnc electncally isolates the metal interconnect structure 14

The spin-on dielectnc is cured at elevated temperatures The preferred temperature for cunng the spin-on dielectnc is a temperature greater than about 350°C The maximum cure temperature is typically limited to less than about 400°C Temperatures higher than about 400°C will cause the aluminum to form hillocks which is un¬ desirable Upon cunng, the refractory metal-containing precursor matenal contained within the spin-on dielectnc reacts with the exposed aluminum on the sidewalls 22 of the aluminum interconnect 16 This reaction between re¬ fractory metal-containing precursor matenal and the exposed aluminum on the sidewalls 22 forms the layer of aluminum intermetallic alloy 24 This layer of aluminum intermetallic alloy 24 compnses aluminum refractory alloy As described above, this layer of aluminum intermetallic alloy 24 resists the formation of electromigration induced pile-ups An example of aluminum refractory alloy suitably employed as the layer of aluminum inter¬ metallic alloy 24 includes TιAl ₃

The refractory metal-containing precursor matenal added to the spin-on dielectnc must be insulating it¬ self Any unreacted fracUon of the refractory metal -contaimng precursor matenal within the spin-on dielectnc must remain insulating after cunng Accordingly, the insulating properties of the spin-on dielectnc are not signifi¬ cantly compromised Process simplicity is provided by this alternative embodiment of the present invenUon This alternative embodiment is no more complex than current processes for forming conventional metal interconnects which are not reinforced to prevent pile-up No extra processing steps are involved in this alternative embodiment

Both embodiments of the present invention provide a technique for strengthening the sidewalls 22 of aluminum interconnects 16 against the formation of electromigration-induced pile-ups In the method of the pres- ent invention, the layer of aluminum intermetallic alloy 24 is harder than the aluminum employed to form the aluminum interconnects 16 After the formation of the layer of aluminum intermetallic alloy 24 on the sidewalls 22, the formation of pile-ups will be suppressed The lifetime of aluminum-based metallization is extended despite electromigration Thus, the method of the present invention improves the reliability and wear resistance of inte¬ grated circuits employing metal interconnects The method of the present invention will be especiallj useful when used in conjunction with softer low dielectnc constant insulating mateπals The soft dielectnc offers little resis¬ tance to the formaUon of pile-ups Accordingly, softer low dielectnc constant insulating mateπals are more sus¬ ceptible to the formaUon of electromigration-induced lateral shorts

The method of the present invenUon enables low dielectnc constant insulating matenal to be used without sacrificing reliability and wear resistance of the aluminum interconnects 16 The used of low dielectnc constant insulating mateπal improves the signal-to-noise ratio of the integrated circuit As descπbed above, the use of the low dielectnc constant insulating mateπal reduces capacitance Thus, the use of low dielectric constant insulating matenal provides lower coupling between interconnect lines Lower coupling results in reduced overshoot and un¬ dershoot of signals Accordingly, the signal-to-noise ratio is improved

Finally, the method of the present invention provides an efficient means for strengthening the sidewalls 22 of the aluminum interconnects 16 The present invention provides a method for providing sidewall reinforce¬ ment to resist electromigration that is simpler than pnor art methods The metal interconnect structure 14 of the present invention involves simpler construction than pnor art metal interconnect structures which resist the for¬ mation electromigration-induced pile-ups Accordingly, the method for forming the metal interconnect structure 14 of the present invention requires a simpler manufacturing process than pnor art solutions for preventing the formation electromigration-induced pile-ups

INDUSTRIAL APPLICABILITY

The method of the invention for forming a metal interconnect structure 14 which resists the formation of pile-ups caused by electromigration is expected to find use in the fabπcation of all deep sub-micrometer IC tech¬ nology

The foregoing description of the preferred embodiment of the present invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Obviously, many modifications and variations will be apparent to practitioners skilled in this art. Many variations of films and materials are possible. It is possible that the invention may be practiced in other fabrica- tion technologies in MOS or bipolar processes. Similarly, any process steps described might be interchangeable with other steps in order to achieve the same result. The embodiment was chosen and described in order to best explain the principles ofthe invention and its practical application, thereby enabling others skilled in the art to understand the invention for various embodiments and with various modifications as are suited to the particular use contem¬ plated. It is intended that the scope of the invention be defined by the claims appended hereto and their equiva- lents.