Title:
NOVEL ROW AND COLUMN SELECT PRE-DECODING SCHEME FOR SEMICONDUCTOR MEMORIES
Document Type and Number:
WIPO Patent Application WO2005081629
Kind Code:
A3
Abstract:
A novel row and column pre-decoding scheme for semiconductor memories is disclosed. The address lines are translated to a special code where for every address combination, k of m bits are at Logic High. This coding slightly increases the number of address lines, but allows a simpler decoding scheme where the complements of the address lines are not needed for the decoding. Thus the number of global address lines in the decoder decreases sharply, along with the total number of transistors. The result is smaller size, less power and faster operation.
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Inventors:
LAVI YOAV (IL)
Application Number:
PCT/IL2005/000214
Publication Date:
March 02, 2006
Filing Date:
February 22, 2005
Export Citation:
Assignee:
LAVI YOAV (IL)
International Classes:
G06F13/40; (IPC1-7): H03K19/094
Foreign References:
| US5369621A | 1994-11-29 | |||
| US4176287A | 1979-11-27 |
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