Title:
OFFSET CALIBRATION CIRCUIT AND MEMORY
Document Type and Number:
WIPO Patent Application WO/2024/032136
Kind Code:
A1
Abstract:
Disclosed in embodiments of the present disclosure are an offset calibration circuit and a memory. The offset calibration circuit comprises an adjustable delay circuit, a phase detection circuit and a phase adjustment control circuit. The adjustable delay circuit is used for receiving an initial differential signal and calibrating the initial differential signal to an i-th differential signal according to an i-th delay amount. The phase detection circuit is used for performing preset delay processing on the i-th differential signal to obtain a reference differential signal, and performing logic processing and comparison on the i-th differential signal and the reference differential signal to obtain a comparison result. The phase adjustment control circuit is used for determining an (i+1)-th differential signal having a minimum offset and a corresponding (i+1)-th delay amount from the i-th differential signal and the reference differential signal on the basis of the comparison result. The adjustable delay circuit is further used for updating the i-th delay amount to the (i+1)-th delay amount to calibrate the initial differential signal to the (i+1)-th differential signal.
Inventors:
LUO JIACHENG (CN)
Application Number:
PCT/CN2023/099925
Publication Date:
February 15, 2024
Filing Date:
June 13, 2023
Export Citation:
Assignee:
CXMT CORP (CN)
International Classes:
H03K5/13
Foreign References:
| CN115051693A | 2022-09-13 | |||
| CN113764024A | 2021-12-07 | |||
| JP2006014352A | 2006-01-12 | |||
| US20200321915A1 | 2020-10-08 |
Attorney, Agent or Firm:
CHINA PAT INTELLECTUAL PROPERTY OFFICE (CN)
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