Title:
OPEN CAVITY PACKAGE USING CHIP-EMBEDDING TECHNOLOGY
Document Type and Number:
WIPO Patent Application WO/2017/011252
Kind Code:
A8
Abstract:
In described examples of a method for fabricating packaged semiconductor devices with an open cavity (110a) in panel format, the method includes: placing on an adhesive carrier tape a panel-sized grid of metallic pieces having a flat pad (230) and symmetrically placed vertical pillars (231); attaching semiconductor chips (101) with sensor systems face-down onto the tape; laminating and thinning low CTE insulating material to fill gaps between chips and grid; turning over assembly to remove tape; plasma-cleaning assembly front side, sputtering and patterning uniform metal layer across assembly and optionally plating metal layer to form rerouting traces and extended contact pads for assembly; laminating (212) insulating stiffener across panel; opening (213) cavities in stiffener to access the sensor system; and singulating (214) packaged devices by cutting metallic pieces.
Inventors:
MAO JIE (US)
NGUYEN HAU (US)
NGUYEN LUU (US)
PODDAR ANINDYA (US)
NGUYEN HAU (US)
NGUYEN LUU (US)
PODDAR ANINDYA (US)
Application Number:
PCT/US2016/041231
Publication Date:
August 10, 2017
Filing Date:
July 07, 2016
Export Citation:
Assignee:
TEXAS INSTRUMENTS INC (US)
TEXAS INSTRUMENTS JAPAN (JP)
TEXAS INSTRUMENTS JAPAN (JP)
International Classes:
H01L21/52
Attorney, Agent or Firm:
DAVIS, Michael, A., Jr. et al. (US)
Download PDF:
Previous Patent: ARTICLE CARRIER AND BLANK THEREFOR
Next Patent: FIBROUS STRUCTURES COMPRISING A SURFACE SOFTENING COMPOSITION
Next Patent: FIBROUS STRUCTURES COMPRISING A SURFACE SOFTENING COMPOSITION