Title:
OPERATING SYSTEM COORDINATED THERMAL MANAGEMENT
Document Type and Number:
WIPO Patent Application WO2003050663
Kind Code:
A3
Abstract:
A processor's (12) performance state may be adjusted based on processor temperature. On transitions to a lower performance state due to the processor (12) getting hotter, the processor's frequency is reduced prior to reducing the processor voltage. Thus, the processor's performance, as seen by the operating system, is reduced immediately. Conversely, on transitions to a higher performance state, due to the processor cooling down, the processor's frequency is not increased until the voltage is changed to a higher level. An interrupt event may be generated anytime the processor's phase locked loop relocks at a new frequency level. Thus, when the interrupt fires, the operating system can read the processor's performance state. As a result, interrupts are not generated that would cause processor performance to lag the interrupt event.
Inventors:
COOPER BARNES
Application Number:
PCT/US2002/036708
Publication Date:
January 15, 2004
Filing Date:
November 15, 2002
Export Citation:
Assignee:
INTEL CORP (US)
International Classes:
G06F1/20; G06F1/32; (IPC1-7): G06F1/20; G06F1/32
Foreign References:
| US5723998A | 1998-03-03 | |||
| US6182232B1 | 2001-01-30 | |||
| US5838578A | 1998-11-17 | |||
| US6219723B1 | 2001-04-17 | |||
| US6243656B1 | 2001-06-05 | |||
| EP1085399A1 | 2001-03-21 |
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