FIELD OF DISCLOSURE

The present disclosure relates in general to circuits for electronic devices, including without limitation personal portable devices such as wireless telephones and media players, and more specifically, to an operational amplifier that may be used within a coulomb counter circuit.

BACKGROUND

Portable electronic devices, including wireless telephones, such as mobile/cellular telephones, tablets, cordless telephones, mp3 players, and other consumer devices, are in widespread use. Such portable electronic devices are often powered by a battery (e.g., a lithium-ion battery). In battery-powered devices, it is often desirable to measure an amount of electrical charge drawn from a battery and delivered to the battery, which may be used to determine a state of charge of the battery.

A circuit referred to as a coulomb counter may be used to measure an amount of electrical charge drawn from a battery and delivered to the battery. In operation, a coulomb counter may detect an electrical current flowing in and out of the battery and integrate such current continuously over time, in order to calculate a total electrical charge drawn from and delivered to the battery. Because coulomb counters continuously integrate, extremely low direct-current (DC) offset in coulomb counter circuitry is desired.

FIGURE 1 illustrates a block diagram of an example coulomb counter, as is known in the art. As shown in FIGURE 1 , a coulomb counter 1 may include a sense resistor 2 for measuring a sense voltage VSNS which is indicative of an electrical current ISNS flowing through the sense resistor. For example, electrical current ISNS may comprise a current drawn from a battery. As also shown in FIGURE 1 , coulomb counter 1 may include an integrator 4 implemented in part with an amplifier 6, such integrator 4 configured to integrate electrical current ISNS over time, providing an indication of net electrical charge that has flowed through sense resistor 2. To prevent integrator saturation, a quantum of charge may be subtracted from integrator 4 using a feedback path having a gain element 50, which may be implemented in whole or part with a digital-to-analog converter (DAC). These feedback events may be counted by a digital accumulator 20 and the result may be a digital quantity Q proportional to the input sense charge flowing through sense resistor 2. Thus, if sense resistor 2 is coupled to the output of a battery, coulomb counter 1 may calculate a net electrical charge drawn from the battery.

As also shown in FIGURE 1 , coulomb counter 1 may implement both system- level chopping using chopping blocks 8 and block-level chopping within integrator 4, using chopping blocks 10. Block-level chopping blocks 10 may operate at a first chopping frequency (e.g., one-half the sampling frequency F _s of coulomb counter 1) to reduce DC offset and inverse frequency noise (also known as 1/f noise) of amplifier 6, and system- level chopping blocks 8 may operate at a second chopping frequency (e.g., F _s /512) to provide residual DC offset for coulomb counter 1.

In summary, coulomb counter 1 may essentially comprise a discrete-time input, switched capacitor feedback sigma-delta modulator. The switched capacitor feedback sigma-delta modulator may receive voltage at its input and generate a pulse-density modulated signal at its output which has a period proportional to the voltage at the input. However, architectures using a continuous time input may also be used.

For better clarity, coulomb counter 1 depicted in FIGURE 1 may be represented as a signal processing block diagram as shown in FIGURE 2. As shown in FIGURE 2, system-level chopping blocks 8 are represented as mixers 12, each having a chopping frequency U _hsys , at the input and output of a sigma-delta analog to digital converter (ADC) 14 that comprises integrator 4 and a three-level quantizer 16. Block- level chopping blocks 10 are not depicted in FIGURE 2.

Coulomb counter 1 as shown in FIGURES 1 and 2 may have disadvantages. Among such disadvantages are an elevated quantization error, offset voltages, and/or ripple voltages. To illustrate, coulomb counter 1 depicted in FIGURE 1 may be represented by the circuit diagram of FIGURE 3A, in which system-level chopping blocks 8, block-level chopping blocks 10, and one or more other components are not depicted for purposes of clarity and exposition. As shown in FIGURE 3A, coulomb counter 1 may be implemented as an anti-aliasing filter that filters sense voltage VSNS, an integrator comprising two-stage feedforward-compensated operational transconductance amplifier (FFCOTA) 6 and an integrating capacitor having capacitance C _mt , followed by a 3-level quantizer 16 and an accumulator 20. As shown in FIGURE 3A, coulomb counter 1 may also include a feeback path with a feedback gain element 50 which may be implemented in whole or part with a DAC.

As shown in FIGURE 3B, the anti-aliasing filter may be implemented using a resistive voltage divider and an anti-aliasing capacitor. Further as shown in FIGURE 3B, two-stage FFCOTA 6 may include a negative gain stage of gain -g _mi followed by a gain stage of gain g _m 2- In parallel with the series combination of gains -g _mi and g _m 2 may be a feedforward gain -g _m 3- Inputs to each of the respective gain stages may be chopped by a respective chopper 30, 32, and 34. A disadvantage of the architecture shown in FIGURE 3B may be the presence of an offset ripple voltage at the input terminal of two-stage FFCOTA 6.

Approaches that overcome such disadvantages are desired.

SUMMARY

In accordance with the teachings of the present disclosure, certain disadvantages and problems associated with existing sensor systems may be reduced or eliminated.

In accordance with embodiments of the present disclosure, a circuit may include a two-stage feedforward compensated operational transconductance integrated amplifier, and the two-stage feedforward compensated operational transconductance integrated amplifier may include an input terminal, an output terminal, a signal path between the input terminal and the output terminal, the signal path comprising a first signal path gain stage and a second signal path gain stage, and ripple rejection circuitry coupled between the input terminal and an intermediate node of the signal path located between the first signal path gain stage and the second signal path gain stage. The ripple rejection circuitry may include a first ripple rejection circuitry gain stage coupled at its input to the input terminal and coupled at its output to an input terminal of a chopper circuit, a notch filter coupled at its input to an output terminal of the chopper circuit, and a second ripple rejection circuitry gain stage coupled at its input to an output terminal of the notch filter and coupled at its output to the intermediate node.

In accordance with these and other embodiments of the present disclosure, a circuit may include an amplifier comprising an input terminal and an output terminal, a filter having its output coupled to the input terminal, the filter configured to receive an input signal and generate a filtered input signal to the input terminal, a digital-to-analog converter having its output coupled to the input terminal, the digital-to- analog converter configured to receive a digital signal and generate an equivalent analog signal to the input terminal, and a signal assist path gain stage coupled at its input to the filter and coupled at its output to the output terminal and configured to inject a current from the filter into an integrating capacitor of the amplifier.

In accordance with these and other embodiments of the present disclosure, a circuit may include an amplifier comprising an input terminal and an output terminal, a filter having its output coupled to the input terminal, the filter configured to receive an input signal and generate a filtered input signal to the input terminal; a digital-to-analog converter having its output coupled to the input terminal, the digital-to-analog converter configured to receive a digital signal and generate an equivalent analog signal to the input terminal; a replica digital-to-analog converter identical to the digital-to-analog converter; and a DAC assist path gain stage coupled at its input to an output of the replica digital-to-analog converter and at its output to the output terminal and configured to inject a current from the DAC assist gain stage into the output terminal·

In accordance with these and other embodiments of the present disclosure, a method may include, in a two-stage feedforward compensated operational transconductance integrated amplifier, the two-stage feedforward compensated operational transconductance integrated amplifier comprising an input terminal, an output terminal, and a signal path between the input terminal and the output terminal, and the signal path having a first signal path gain stage and a second signal path gain stage, coupling ripple rejection circuitry between the input terminal and an intermediate node of the signal path located between the first signal path gain stage and the second signal path gain stage. The ripple rejection circuitry may include a first ripple rejection circuitry gain stage coupled at its input to the input terminal and coupled at its output to an input terminal of a chopper circuit, a notch filter coupled at its input to an output terminal of the chopper circuit, and a second ripple rejection circuitry gain stage coupled at its input to an output terminal of the notch filter and coupled at its output to the intermediate node.

In accordance with these and other embodiments of the present disclosure, a method may include coupling a filter at its output coupled to an input terminal of an amplifier, wherein the filter is configured to receive an input signal and generate a filtered input signal to the input terminal, coupling a digital-to-analog converter at its output coupled to the input terminal, wherein the digital-to-analog converter is configured to receive a digital signal and generate an equivalent analog signal to the input terminal, and coupling a signal assist path gain stage at its input to the filter and coupling the signal assist path gain stage at its output to an output terminal of the amplifier, wherein the signal assist path gain stage is configured to inject a current from the filter into an integrating capacitor of the amplifier.

In accordance with these and other embodiments of the present disclosure, a method may include coupling a filter at its output to an input terminal of an amplifier, wherein the filter is configured to receive an input signal and generate a filtered input signal to the input terminal; coupling a digital-to-analog converter at its output to the input terminal, wherein the digital-to-analog converter is configured to receive a digital signal and generate an equivalent analog signal to the input terminal; and coupling a DAC assist path gain stage at its input to an output of a replica digital-to-analog converter identical to the digital-to- analog converter and coupling the DAC assist path at its output to the output terminal, wherein the DAC assist path is configured to inject a current from the DAC assist gain stage into the output terminal·

Technical advantages of the present disclosure may be readily apparent to one skilled in the art from the figures, description and claims included herein. The objects and advantages of the embodiments will be realized and achieved at least by the elements, features, and combinations particularly pointed out in the claims. It is to be understood that both the foregoing general description and the following detailed description are examples and explanatory and are not restrictive of the claims set forth in this disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

A more complete understanding of the example, present embodiments and certain advantages thereof may be acquired by referring to the following description taken in conjunction with the accompanying drawings, in which like reference numbers indicate like features, and wherein:

FIGURE 1 illustrates a circuit diagram of selected components of a coulomb counter, as is known in the art;

FIGURE 2 illustrates a block diagram of the coulomb counter of FIGURE 1, as is known in the art;

FIGURE 3A illustrates a simplified circuit diagram of the coulomb counter of FIGURE 1, as is known in the art;

FIGURE 3B illustrates the simplified circuit diagram of the coulomb counter of FIGURE 3A, with detail shown of an anti-aliasing filter and operational amplifier, as is known in the art;

FIGURE 4A illustrates a block diagram of an example coulomb counter, in accordance with embodiments of the present disclosure;

FIGURE 4B illustrates the simplified circuit diagram of the coulomb counter of FIGURE 4A, with detail shown of an anti-aliasing filter and an operational amplifier, in accordance with embodiments of the present disclosure;

FIGURE 5A illustrates a block diagram of an example coulomb counter, in accordance with embodiments of the present disclosure;

FIGURE 5B illustrates the simplified circuit diagram of the coulomb counter of FIGURE 5A, with detail shown of an anti-aliasing filter, gain stage, and feedback digital- to-analog converter, in accordance with embodiments of the present disclosure;

FIGURE 6A illustrates a block diagram of an example coulomb counter, in accordance with embodiments of the present disclosure;

FIGURE 6B illustrates the simplified circuit diagram of the coulomb counter of FIGURE 6A, with detail shown of a gain stage, in accordance with embodiments of the present disclosure;

FIGURE 6C illustrates a graph depicting an example advantage of including the gain stage shown in FIGURES 6 A and 6B, in accordance with embodiments of the present disclosure; and FIGURE 7 illustrates a block diagram of an example coulomb counter, in accordance with embodiments of the present disclosure.

DETAILED DESCRIPTION

FIGURE 4A illustrates a block diagram of an example coulomb counter 100A, in accordance with embodiments of the present disclosure. In some embodiments, coulomb counter 100A may be implemented within a portable electronic device, such as a smart phone, tablet, game controller, and/or other suitable device. As shown in FIGURE 4A, coulomb counter 100A may include an anti-aliasing filter 102, an integrator comprising a two-stage FFCOTA 106A and an integrating capacitor 104, a 3-level quantizer 116, an accumulator 120, and a feedback path comprising a gain element 190, wherein such gain element may be implemented with a DAC.

Anti-aliasing filter 102 may be located at the input of coulomb counter 100A and may be configured to filter an input signal to coulomb counter 100A indicative of an electrical current (e.g., a sensed voltage across a sense resistor).

A sigma-delta analog-to-digital converter (ADC) may in effect be implemented by a two-stage FFCOTA 106A and integrating capacitor 104, a 3-level quantizer 116, and a feedback path comprising gain element 190, such ADC operable to convert an analog signal received at its input to an equivalent digital signal at its output. Accumulator 120 may receive the quantized digital output signal generated by 3-level quantizer 116 and digitally integrate the quantized digital output signal over time to calculate a net amount of charge Q flowing through the sense resistor from which the input of coulomb counter 100A is obtained.

As shown in FIGURE 4A, two-stage FFCOTA 106A may include ripple reduction circuitry (RRC) 118. RRC 118 is described in greater detail below with respect to FIGURE 4B.

FIGURE 4B illustrates a circuit diagram of the coulomb counter 100A, with detail shown of anti-aliasing filter 102 and two-stage FFCOTA 106A, in accordance with embodiments of the present disclosure. As shown in FIGURE 4B, anti-aliasing filter 102 may be implemented using a resistive voltage divider (e.g., resistors each having resistances of Ri _n /2) and an anti-aliasing capacitor 122. Further as shown in FIGURE 4B, two-stage FFCOTA 106A may include a negative gain stage 124 with gain -g _mi followed by a gain stage 126 having gain g _m 2. In parallel with the series combination of gain stages 124 and 126 is a feedforward gain stage 128 having gain -g _m 3· An input to gain stage 124 may be chopped by a chopper 130 and an input to gain stage 126 may be unchopped by chopper 132.

As mentioned above, FFCOTA 106A may include RRC 118. As shown in FIGURE 4B, RRC 118 may include a negative gain stage 125 with gain -g _mn , followed by a chopper 140, a notch filter 142, and a gain stage 144 having gain g _mNa . Accordingly, RRC 118 may effectively serve as a chopped ripple reduction servo which may monitor a voltage present at the input of negative gain stage 124 and may remove offset voltage (and its associated ripple) present at the input of negative gain stage 124 by injecting a compensating current into the output terminal of negative gain stage 124, to which capacitor 146 may be coupled. Because the chopped ripple reduction servo has offset voltages associated with itself, its output signal may also be chopped by chopper 140. Chopper 140 may serve to mix input signal ripple down to direct current, and mix up the unwanted offset of negative gain stage 125. Further, notch filter 142 and capacitor 148 may attenuate any undesired signal components, thus filtering out any residual ripple.

FIGURE 5 A illustrates a block diagram of an example coulomb counter 100B, in accordance with embodiments of the present disclosure. In some embodiments, coulomb counter 100B may be implemented within a portable electronic device, such as a smart phone, tablet, game controller, and/or other suitable device. As shown in FIGURE 5A, coulomb counter 100B may include an anti-aliasing filter 102, an integrator comprising a two-stage FFCOTA 106B and an integrating capacitor 104, a 3-level quantizer 116, a feedback path comprising a gain element 190 (which may be implemented using a DAC), an accumulator 120, a signal assist path comprising a gain stage 152, and a feedback digital- to-analog converter (DAC) 150.

Anti-aliasing filter 102 may be located at the input of coulomb counter 100B and may be configured to filter an input signal to coulomb counter 100B indicative of an electrical current (e.g., a sensed voltage across a sense resistor).

A sigma-delta analog-to-digital converter (ADC) may in effect be implemented by a two-stage FFCOTA 106B and integrating capacitor 104, and a 3-level quantizer 116, such ADC operable to convert an analog signal received at its input to an equivalent digital signal at its output. Accumulator 120 may receive the quantized digital output signal generated by 3-level quantizer 116 and digitally integrate the quantized digital output signal over time to calculate a net amount of charge Q flowing through the sense resistor from which the input of coulomb counter 100B is obtained.

FIGURE 5B illustrates a circuit diagram of the coulomb counter 100B, with detail shown of anti-aliasing filter 102, gain stage 152, and feedback digital-to-analog converter 150, in accordance with embodiments of the present disclosure. As shown in FIGURE 5B, anti-aliasing filter 102 may be implemented using a resistive voltage divider (e.g., resistors each having resistances of Rj _n /2) and an anti-aliasing capacitor 122. Further, although not explicitly shown in FIGURE 4B, two-stage FFCOTA 106B may be similar in topology to two-stage FFCOTA 106A. Thus, two-stage FFCOTA 106B may include a negative gain stage 124 with gain -g _mi followed by a gain stage 126 having gain g _m 2, may include in parallel with the series combination of gain stages 124 and 126 a feedforward gain stage 128 having gain -g _m 3, and may include respective choppers 130 and 132 for chopping and unchopping signals at inputs to each of the respective gain stages 124 and 126. In some embodiments, RRC 118 present in two-stage FFCOTA 106A may be absent from two-stage FFCOTA 106B. In other embodiments, RRC 118 present in two-stage FFCOTA 106A may also be present in two-stage FFCOTA 106B, such that two-stage FFCOTA 106A may be identical to two-stage FFCOTA 106B in such embodiments.

Gain stage 152 may have a gain equal to negative gain -g _mS a and may be coupled between the midpoint of the voltage divider of anti-aliasing filter 102 and the output terminal of two-stage FFCOTA 106B, forming a signal assist path such that the current that would otherwise flow into the input terminal of two-stage FFCOTA 106B (via one of the resistors of anti-aliasing filter 102) and contribute to a voltage V _x present at the input terminal of two-stage FFCOTA 106B, may instead be supplied to the output of two-stage FFCOTA 106B via such signal assist path. Negative gain -g _mS a may be equal to l/2Rin, wherein Rin is twice the value of the resistances present in anti-aliasing filter 102.

Such signal assist path may inject a current with value equal to the current flowing in a resistor of anti-aliasing filter 102, such that two-stage FFCOTA 106B need not provide such current via integrating capacitor 104. As a result, the virtual ground node V _x may have no presence of sense voltage VSNS.

Feecback DAC 150 may receive a digital input signal D.V _Ref , and may convert such digital input signal D.V _Ref into analog equivalent reference voltage injected into voltage V _x· Digital input signal D.V _Ref may be a digital representation of a reference voltage V _Ref input to a second input terminal of two-stage FFCOTA 106B (wherein such reference voltage V _Ref may be a ground potential in some embodiments), multiplied by the quantized output D of 3-level quantizer 116 (e.g., D may equal -1, 0, or +1). DAC 150 may serve to convert digital input signal D.VRef into an analog charge of value D· VRefCint, and add such charge to the integrator of coulomb counter 100B.

FIGURE 6A illustrates a block diagram of an example coulomb counter lOOC, in accordance with embodiments of the present disclosure. In some embodiments, coulomb counter lOOC may be implemented within a portable electronic device, such as a smart phone, tablet, game controller, and/or other suitable device. As shown in FIGURE 6A, coulomb counter lOOC may include an anti-aliasing filter 102, an integrator comprising a two-stage FFCOTA 106B and an integrating capacitor 104, a 3-level quantizer 116, an accumulator 120, a signal assist path comprising a gain stage 156, a feedback digital-to- analog converter (DAC) 150, and a replica DAC 154. Coulomb counter lOOC may be similar in many respects to coulomb counter 100B, except that coulomb counter lOOC includes gain stage 156 and replica DAC 154 in lieu of gain stage 152. FIGURE 6B illustrates the simplified circuit diagram of coulomb counter lOOC, with detail shown of gain stage 156 having a gain of -g _m da (which may be the same as gain -g _m da depicted in FIGURE 5B) in accordance with embodiments of the present disclosure. As shown in FIGURE 6B, gain stage 156 may be coupled between the output of replica DAC 154 and the output of two-stage FFCOTA 106B to form a DAC assist path. Replica DAC 154 may be identical to feedback DAC 150 with the exception that replica DAC 154 may receive an input which is the inverse of that received by feedback DAC 150.

In operation, gain stage 156 and replica DAC 154 may combine to generate, at the output of two-stage FFCOTA 106B, a current opposite to a current generated by DAC 150. Current generated by DAC 150 may pass through integrating capacitor 104 and sum with the node at the output of two-stage FFCOTA 106B with opposite current output by gain stage 156. Such combined currents may be approximately equal, and thus may minimize an output current required from two-stage FFCOTA 106B, thus minimizing disturbance at the electrical node of voltage V _x . Stated in another manner, the combination of replica DAC 154 and gain stage 156 may assist in lowering an apparent impedance at the output of two-stage FFCOTA 106B, meaning two-stage FFCOTA 106B may have to do less “work” to supply current at its output, minimizing disturbance at the electrical node of voltage V _x . FIGURE 6C illustrates a graph depicting an example advantage of including the DAC assist path shown in FIGURES 6A and 6B, in accordance with embodiments of the present disclosure.

FIGURE 7 illustrates a block diagram of an example coulomb counter 100D, in accordance with embodiments of the present disclosure. As shown in FIGURE 7, coulomb counter 100D combines the features of coulomb counter 100B and coulomb counter lOOC, thus providing advantages of both coulomb counter 100B and coulomb counter lOOC. In some embodiments, coulomb counter 100D may be implemented with two-stage FFCOTA 106A comprising RRC 118 in lieu of two-stage FFCOTA 106B, thus also providing the advantages of RRC 118.

As used herein, when two or more elements are referred to as “coupled” to one another, such term indicates that such two or more elements are in electronic communication or mechanical communication, as applicable, whether connected indirectly or directly, with or without intervening elements.

This disclosure encompasses all changes, substitutions, variations, alterations, and modifications to the example embodiments herein that a person having ordinary skill in the art would comprehend. Similarly, where appropriate, the appended claims encompass all changes, substitutions, variations, alterations, and modifications to the example embodiments herein that a person having ordinary skill in the art would comprehend. Moreover, reference in the appended claims to an apparatus or system or a component of an apparatus or system being adapted to, arranged to, capable of, configured to, enabled to, operable to, or operative to perform a particular function encompasses that apparatus, system, or component, whether or not it or that particular function is activated, turned on, or unlocked, as long as that apparatus, system, or component is so adapted, arranged, capable, configured, enabled, operable, or operative. Accordingly, modifications, additions, or omissions may be made to the systems, apparatuses, and methods described herein without departing from the scope of the disclosure. For example, the components of the systems and apparatuses may be integrated or separated. Moreover, the operations of the systems and apparatuses disclosed herein may be performed by more, fewer, or other components and the methods described may include more, fewer, or other steps. Additionally, steps may be performed in any suitable order. As used in this document, “each” refers to each member of a set or each member of a subset of a set.

Although exemplary embodiments are illustrated in the figures and described below, the principles of the present disclosure may be implemented using any number of techniques, whether currently known or not. The present disclosure should in no way be limited to the exemplary implementations and techniques illustrated in the drawings and described above.

Unless otherwise specifically noted, articles depicted in the drawings are not necessarily drawn to scale. All examples and conditional language recited herein are intended for pedagogical objects to aid the reader in understanding the disclosure and the concepts contributed by the inventor to furthering the art, and are construed as being without limitation to such specifically recited examples and conditions. Although embodiments of the present disclosure have been described in detail, it should be understood that various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the disclosure.

Although specific advantages have been enumerated above, various embodiments may include some, none, or all of the enumerated advantages. Additionally, other technical advantages may become readily apparent to one of ordinary skill in the art after review of the foregoing figures and description.

To aid the Patent Office and any readers of any patent issued on this application in interpreting the claims appended hereto, applicants wish to note that they do not intend any of the appended claims or claim elements to invoke 35 U.S.C. § 112(f) unless the words “means for” or “step for” are explicitly used in the particular claim.