OPTICAL NODE

This invention concerns a node that is suitable for use as a switching element in a network, in particular, a node that is suitable for switching in a short-range optical interconnection of a network.

In the field of high-performance computing, electronic interconnections are approaching their fundamental limitations in terms of wiring, power density and bit rate. To overcome these fundamental limitations, optical-electrical interconnections are being used; for example, optical fibres are used with switching nodes that convert the optical signals received from the optical fibres into electronic signals for processing, such as label processing. These nodes can be the source of bottlenecks within the system, limiting the bit rate of the interconnection.

According to a first aspect of the invention there is provided a node for a network which transmits optical data signals having data indicating the destination for the optical data signal in the network, the node comprising means to receive the optical data signals and processing means for processing destination data in the optical data signal to determine a destination for the optical data signal and sending the optical data signal to an output dependent upon the determined destination, wherein the processing is carried out in its entirety in the photonic domain.

The node of the invention may reduce latency time because the node does not convert the optical data signal into an electronic signal in order to determine the destination for the optical data signal.

The destination data may indicate the output of the node to which the optical data signal is to be sent and/or the next device, such as the next node, on the network to which the optical data signal is to be sent or/and

the destination data may indicate a final destination device on the network to which the optical signal is to be sent.

The optical signals may comprise packets with headers or labels that includes the destination data. The packets may comprise one or more packet identifying bits that allow packets to be identified. The destination data may comprise one or more further bits following the one or more packet identifying bits that identify the destination for the optical signal. The node may be arranged to read the optical signal in the photonic domain to identify packets by detecting the packet identifying bits.

The optical signal may be read in the photonic domain by exploiting nonlinear effects of optical signals in semiconductor devices.

The node may comprise an optical pump that generates an optical clock signal. The optical clock signal may have a repetition rate that is equal to the packet rate of the optical signal.

The node may comprise an optical switch that can be switched between at least two states to direct the optical signal to one of at least two outputs.

The processing means may comprise a control unit arranged to generate optical control signals to control the optical switch based on the destination data. The control unit may be arranged to generate optical control signals to control the optical switch based on the destination data and the packet identifying bits. In this way, packets of one type can be prioritised over packets of another type.

The processing means may further comprise packet recognising means for reading the optical signal and generating an optical packet recognition signal dependent on identified packet-identifying bits in the optical signal and the control unit may generate the optical control signal in response to

the packet recognition signal. The packet recognition signal may be generated by extracting the packet-identifying bits from the optical data signal. The packet recognising means may use optical clock signals generated by the optical pump and may comprise means to synchronise the optical clock signal with a first bit of the one or more packet identifying bits.

The processing means may further comprise extraction means to generate an optical destination signal dependent on the destination data in each packet and the control unit may generate the optical control signal in response to the packet recognition signal. The extraction means may use the optical clock signal generated by the optical pump and comprise means to synchronise the optical clock signal with a first bit corresponding to the destination data.

The node may comprise inputs for receiving first and second optical data signals and the optical switch is operable to direct the first and second optical data signals received at the inputs to any one of at least two outputs. The control unit may control the switch such that when a first optical data signal is received simultaneously with a second optical data signal, the first optical signal is transmitted to one of the outputs based on the destination data contained therein and the second optical data signal, based on the destination data contained therein, is either transmitted to a further one of the outputs or, if the output for the first and second optical signals is the same, the second optical data signal is not transmitted to one of the outputs. In this way, first optical data signals are given priority in the node over second optical data signals.

The control unit may control the switch based on the destination signal received from the extraction means and packet recognition signal received from the packet recognising means. The control unit may comprise optical

logic gates that process the destination signal and the packet recognition signal in the photonic domain to generate the optical control signal.

The node may comprise a contention resolution unit operable to selectively cancel the second optical data signal. The control unit may control the contention resolution unit based on the destination signal and the packet recognition signal. The control unit may control the contention resolution unit to cancel the second optical data signal if the output for the first and second optical signals is the same.

The contention resolution unit may comprise an optical amplifier arranged to receive the second optical data signal and a gate signal such that cross gain modulation occurs between the second optical data signal and the gate signal resulting in cancellation of the second optical data signal (i.e. substantially no output from the contention resolution unit).

The control unit may generate optical signals to control the switch and the contention resolution unit. In one embodiment, the node comprises two outputs and the destination data of the optical data signals comprises a high or a low bit, A, to indicate which one of the two outputs the optical data signal is to be transmitted to.

In one arrangement, an optical packet recognition signal is generated for the first optical data signal and comprise a bit, P, to represent the presence or absence of the first optical data signal. In this arrangement, the control unit comprises optical logic gates that generate an optical control signal, SCG, to control the switch using the following logic function: -

SCG = AH v PH A AL ,

wherein AH is the high or low bit of the destination data for the first optical data signal, AL is the high or low bit of the destination data for the second optical data signal and PH is the packet recognition bit for the first optical data signal, wherein high represents the presence of a first optical data signal and low represents the absence of the first optical data signal.

The control unit may further generate optical signals to control the switch and the contention resolution unit. The control unit may comprise optical logic gates that generate an optical control signal, CRC, to control the contention resolution unit using the following logic function: -

CRC = AH ® AL A PH ,

wherein AH is the high or low bit of the destination data for the first optical data signal, AL is the high or low bit of the destination data for the second optical data signal and PH is the packet recognition bit for the first optical data signal, wherein high represents the presence of a first optical data signal and low represents the absence of the first optical data signal.

It will be understood that v , λ and θ represent the OR, AND and XOR logic functions respectively and the line represents the logic function NOT. Furthermore, the terms high and low are simply used to refer to different binary states and the invention is not to be limited to high being a high energy state of the optical data signal or low being a low energy state of the optical data signal. High and low could be represented by high and low energy states of the optical data signal or visa- versa or could be represented by transitions between different states of the optical data signal. Furthermore, even though this is not preferable, high and low could be represented in different ways for different signals.

An embodiment of the invention will now be described, by example only, with reference to the accompanying drawings, in which

Figure 1 shows an all optical node;

Figure 2 shows an arrangement of logic gates for the contention detection unit of the all optical node;

Figure 3 shows the logic table for the logic gates shown in Figure 2; and

Figure 4 shows the optical components of the logic gates of Figure

2.

Figure 1 illustrates the main components of an all-optical switched optical node 100 for use, amongst other things, in an optical communication network. The all-optical node of the invention comprises means, in the form of two inputs (2) and (3) each for receiving an optical data signal A and B respectively. The all-optical node further comprises a processing means, generally designated (1) for processing the optical data signals to determine a destination for the optical data signals and sending the optical data signals to one of two outputs (4) and (5) dependent upon the determined destination. All of the processing is carried out in the photonic domain.

In this embodiment, the optical data signals comprise packets headed by a packet recognition bit, P, which identifies the start of a packet, a label Li to L _n , which contains destination data identifying the intended destination for the packet and the payload.

The processing means (1) comprises a packet recogniser (6) and a label extractor (7) for reading the optical data signal A and identifying a packet

of the optical data signal and extracting a label, L, of the packet respectively. The processing means (1) also comprises a further label extractor (8) for extracting the label from optical B.

In use, the packet recogniser (6) generates a packet recognition signal, PH, and makes the signal high on detecting a packet recognition bit, Pb. The label extractors (7), (8), extracts the label proceeding the packet recognition bit and forwards this label to a contention detection unit (9) as optical destination signals AH and AL. In this embodiment, the label is either high to indicate that the optical data signal is to be sent to output (4) or low to indicate that the optical data signal is to be sent to output (5).

The packet recogniser (6) and label extractors (7,8) pass the signals AH, AL and PH to a contention detection unit (9). The contention detection unit (9) comprises a series of logic gates that process the signals received from the packet recogniser (6) and label extractors (7,8) to generate two optical signals CRC and SCG. Signal CRC is used to control a contention resolution unit (10) and signal SCG is used to control a 2x2 optical fabric switch (1 1). The optical fabric switch (1 1) directs the optical signals A and B to one of the two outputs (4,5) as dictated by signal SRG. The contention resolution unit (10) maintains or cancels optical data signal B in response to signal CRC.

The contention detection circuit (9) implements processing logic so as to determine the correct values of CRC and SCG for any given combination of input signals AH, AL and PH were each signal can have a value of 0 or 1 in this embodiment. The contention detection circuit comprises all optical logic gates so that all processing is performed in the optical domain. The outputs CRC and SCG are also optical signals. The logic is shown in the truth table of Figure 3, and the implementation using logical components is shown in Figure 2 and, in block diagram form with optical components in

Figure 4. It can be seen that the circuit is compact and requires only 6 logic

gates- 3 NOR gates 310.311 ,312, 2 AND gates 321 ,322 and 1 OR gate 331. Each of the gates is implemented using a semiconductor optical amplifier except for the OR gate 331 which is implement using an optical coupler.

In use, the node receives optical data signals A and B that are read by packet recogniser (6) and label extractors (7,8). Based on the signals AH, AL and PH, the contention detection unit (9) generates appropriate signals CRC and SCG. In this embodiment, if optical signal A and optical signal B are to be sent to the same output (4,5) there is a contention and this is resolved by contention detection unit (9) sending a CRC optical signal to the contention resolution unit (10) which causes the contention resolution unit (10) to cancel optical signal B while the contention exists. The optical switch (11) is controlled by the contention detection unit (9) to direct optical signal A to the appropriate output (4,5) and, if possible, also direct optical signal B to the appropriate output (4,5) as indicated by the destination data contained in the labels.

As the node carries out all processing of the optical signals in the photonic domain, delays in the node are avoided.