Technical field

The present invention generally relates to a reference oscillator arrangement, an oscillator arrangement, methods of controlling such arrangements, a computer program for implementing the methods, and a communication device including such arrangements. Background

Radio frequency (RF) transmitters (TX) and receivers (RX) use RF local oscillators (LO) driving mixers that in turn are used to up-convert and down-convert signals. The LO signals, generated by frequency synthesizers such as phase-locked- loops (PLLs), exhibit phase noise and that ultimately limits the attainable performance of a radio link. The problem with phase noise is two-fold. Firstly, the phase noise at smaller frequency offsets from the LO frequency generally leads to a limit on error- vector magnitude (EVM) and in the case of orthogonal-frequency division multiplexing, OFDM, transmission it is readily understood that sub-carriers will interfere with one another. Secondly, phase noise at higher offsets is generally a problem in radio communication systems, like cellular radio, with very crowded spectrum and where a strong signal, adjacent in frequency to a desired signal, will mix with the phase noise and generate co-channel interference, which is commonly referred to as reciprocal mixing. Thus, the issue of phase noise needs to be considered.

Designing hardware for radio communication using mm wavelength frequencies (e.g. 60GHz), especially battery operated user equipment or low power access nodes, is challenging for many reasons. LO phase noise is one such aspect that when compared with cellular radio standards or WiFi, e.g. 802.1 ln,ac, etc., operating in the 0.5-5GHz regime it will be much worse in the mm wavelength regime. For a given power consumption budget for a controlled oscillator the phase noise in dBc/Hz at a given offset roughly scales with 20*log(f _L o). To obtain decent phase noise performance from an LO synthesizer, incorporating a controlled oscillator, CO, providing an oscillating signal at a frequency based on a control signal, without increasing CO power consumption excessively compared with the low-GHz regime, one can increase the loop bandwidth of the LO synthesizer. Increasing the LO synthesizer loop bandwidth will also lead to faster frequency lock and tracking behaviour. On the other hand, this will increase the requirements on the frequency reference generator, typically a crystal oscillator accordingly such that its associated power consumption may reach that of the LO synthesizer or even become larger, on the order of 100 's of mW instead of a few mW as is common for the low-GHz range user equipment. Such high reference oscillator power consumption is not desired in battery operated equipment or in other equipment on a low power budget.

Circuits designed for very low phase noise may have relatively high power consumption compared with circuits where more phase noise is accepted. It is therefore a desire to provide an approach providing both acceptable phase noise and relatively low power consumption.

Summary

The invention is based on the understanding by having a reconfigurable reference oscillator, it is feasible to save power when possible based how much the reference oscillator phase noise is allowed to deteriorate the desired signal in

transmission and/or reception. This may depend on for example at least one of error- vector magnitude, signal-to-noise ratio, modulation format, or any other parameter that indicate quality of the desired signal. These are normally known for a given transport format, i.e. a format for transmission of information which both the transmitter at a transmitting side and a receiver at a receiving side use. The reference oscillator performance may thus be adjusted as these parameters in turn depend on transmission and reception conditions.

According to a first aspect, there is provided a reference oscillator arrangement for a communication apparatus capable of communicating according to a plurality of transport formats. The reference oscillator arrangement comprises a reference oscillator controller; a resonator core comprising a reference resonator and a driving circuit for the reference resonator, wherein the resonator core is arranged to provide an oscillating signal at a frequency of the reference resonator; and a reference oscillator buffer arrangement, connected to the resonator core, comprising an active circuit arranged to provide a reference oscillator output based on the oscillating signal. The reference oscillator controller is arranged to receive information about an applied transport format and control the driving circuit and/or the active circuit based on the information about the applied transport format.

The reference resonator may be a crystal resonator or a microelectromechanical system, MEMS, resonator. The reference oscillator controller may be arranged to perform the control by controlling bias of the driving circuit and/or the active circuit.

The reference oscillator buffer arrangement may comprise a plurality of buffers for providing output signals to different circuits of the communication apparatus, each buffer comprising an active circuit, wherein the active circuits of at least a set of the buffers may be individually controllable.

The controller may comprise a look-up table arranged to map transport formats to control settings of the driving circuit and/or the active circuit.

The controller may be arranged to control to adjust the driving circuit once for a transmission burst of the communication apparatus.

The controller may be arranged to control to adjust the active circuit at a plurality of instances during a transmission burst of the communication apparatus.

According to a second aspect, there is provided an oscillator arrangement for a communication apparatus capable of communicating according to a plurality of transport formats. The oscillator arrangement comprises a reference oscillator arrangement according to the first aspect capable of adjusting phase noise of the generated reference oscillator output; and a phase-locked loop circuit comprising a phase detector arranged to receive an output signal from the reference oscillator arrangement.

The phase-locked loop circuit may be arranged to adjust a loop bandwidth of a phase-locked loop thereof such that an increase in phase noise of the generated reference oscillator output implies a decrease in loop bandwidth, and a decrease in phase noise of the generated reference oscillator output implies an increase in loop bandwidth.

The phase-locked loop circuit may comprise a controlled oscillator which is arranged to provide an oscillator signal based on a filtered output from the phase detector. The controlled oscillator may be arranged to receive different settings from the reference oscillator controller for providing different levels of phase noise such that an increase in phase noise of the generated reference oscillator output implies an increase in phase noise of the controlled oscillator, and a decrease in phase noise of the generated reference oscillator output causes a decrease in phase noise of the controlled oscillator.

The reference oscillator arrangement may be arranged to be controlled such that a decrease in a loop bandwidth of a phase-locked loop of the phase-locked loop circuit implies an increase in phase noise of the generated reference oscillator output, an increase in the loop bandwidth implies and a decrease in phase noise of the generated reference oscillator output.

According to a third aspect, there is provided a method of controlling a oscillator arrangement for a communication apparatus capable of communicating according to a plurality of transport formats. The method comprises providing an oscillating signal at a frequency of a reference resonator of a resonator core comprising the reference resonator and a driving circuit for the reference resonator; providing a reference oscillator output based on the oscillating signal by a reference oscillator buffer arrangement connected to the resonator core; receiving information about an applied transport format; and controlling the driving circuit and/or the active circuit based on the information about the applied transport format.

The controlling may comprise controlling bias of the driving circuit and/or the active circuit.

The reference oscillator buffer arrangement may comprise a plurality of buffers for providing output signals to different circuits of the communication apparatus, each buffer comprising an active circuit, wherein the method may comprise controlling active circuits of at least a set of the buffers individually.

The method may comprise controlling settings of the driving circuit and/or the active circuit by mapping transport formats to control settings from a look-up table.

The method may comprise controlling the driving circuit to adjust once for a transmission burst of the communication apparatus.

The method may comprise controlling the active circuit to adjust at a plurality of instances during a transmission burst of the communication apparatus.

The oscillator arrangement may comprise a phase-locked loop circuit comprising a phase detector arranged to receive an output signal from a reference oscillator arrangement. The method may comprise adjusting a loop bandwidth of a phase-locked loop of the phase-locked loop circuit such that an increase in phase noise of the generated reference oscillator output implies a decrease in loop bandwidth, and that a decrease in phase noise of the generated reference oscillator output implies an increase in loop bandwidth.

The oscillator arrangement may comprise a phase-locked loop circuit comprising a phase detector arranged to receive an output signal from a reference oscillator arrangement, and the phase-locked loop circuit may comprise a controlled oscillator which is arranged to provide an oscillator signal based on a filtered output from the phase detector, and wherein the controlled oscillator may be arranged to receive different settings from the reference oscillator controller for providing different levels of phase noise. The method may comprise controlling the controlled oscillator such that an increase in phase noise of the generated reference oscillator output implies an increase in phase noise of the controlled oscillator, a decrease in phase noise of the generated reference oscillator output implies a decrease in phase noise of the controlled oscillator.

The oscillator arrangement may comprise a phase-locked loop circuit and a reference oscillator arrangement, wherein the reference oscillator arrangement comprises the reference resonator core and the reference buffer arrangement. The method may comprise controlling the reference oscillator arrangement such that an increase in a loop bandwidth of the phase-locked loop circuit implies a decrease in phase noise of the generated reference oscillator output, and a decrease in the loop bandwidth implies an increase in phase noise of the generated reference oscillator output.

According to a fourth aspect, there is provided a computer program comprising instructions which, when executed on a processor of a controller for an oscillator arrangement, causes the oscillator arrangement to perform the method according to the third aspect.

According to a fifth aspect, there is provided a communication device for operating with a radio access network and capable of communicating according to a plurality of transport formats. The communication device comprises a transceiver arranged to transmit or receive one or more data messages over a wireless channel; and an oscillator arrangement according to the first or second aspects.

Brief description of the drawings

The above, as well as additional objects, features and advantages of the present invention, will be better understood through the following illustrative and non-limiting detailed description of preferred embodiments of the present invention, with reference to the appended drawings.

Fig. 1 schematically illustrates a reference oscillator arrangement according to an embodiment.

Fig. 2 schematically illustrates an example of a resonator core.

Fig. 3 schematically illustrates an example of a reference oscillator buffer.

Fig. 4 schematically illustrates a controller according to an embodiment. Fig. 5 schematically illustrates an oscillator arrangement according to an embodiment.

Fig. 6 is a flow chart illustrating a method according to an embodiment.

Fig. 7 is a flow chart illustrating a method according to an embodiment.

Fig. 8 is a block diagram schematically illustrating a communication device according to an embodiment.

Fig. 9 schematically illustrates a computer-readable medium and a processing device.

Fig. 10 is an illustrative view of phase noise contributions from reference oscillator and controlled oscillator with balanced choice of loop bandwidth.

Fig. 11 is an illustrative view of phase noise contributions from reference oscillator and controlled oscillator with low loop bandwidth.

Fig. 12 is an illustrative view of phase noise contribution from reference oscillator and controlled oscillator with high bandwidth.

Detailed description

PLLs include a loop filter that limits the bandwidth of the loop, carefully designed to shape the overall phase noise according to given specifications and that overall phase noise in turn is composed of contributions from controlled oscillator (CO), other building blocks within the PLL, as well as the reference oscillator (RO), which here is not considered as a part of the PLL. Lowering the bandwidth will lead to that the CO's contribution to integrated phase noise will increase and increasing the bandwidth will conversely lead to a decreased contribution from the CO. The opposite applies to the RO serving as a reference within the loop bandwidth. The larger the loop bandwidth the larger the frequency range over which the PLL will track the behaviour of the RO. Increasing the loop bandwidth at least has one advantage, the PLL will lock faster. In case of schemes where reception and/or transmission is not continuous, commonly referred to as discontinuous reception (DRX) and transmission (DTX), there is an opportunity to save power by turning of transceiver blocks when not in use. As the PLL will take some time to lock it must be turned on a certain time ahead of its anticipated use. For today's cellular equipment in the low-GHz regime the PLL bandwidth is typically a few hundred kHz and cold start, i.e. being powered on, to lock may take 100- 200us. If the power consumption of the PLL is high the ability to lock PLL fast may lead to significant savings in power when using DRX and/or DTX schemes. In other words, having a large PLL bandwidth is beneficial in this respect. A large PLL bandwidth inevitably increases the phase noise contribution from the RO and in case of mm wavelength (mmW) LO frequencies this becomes even worse due to the multiplication factor of the phase noise when transformed from the reference oscillator frequency to the LO frequency, i.e. phase noise increase as 20 x logl0(N)

Fig. 10 is an illustrative view of phase noise contributions from reference oscillator and controlled oscillator with balanced choice of loop bandwidth. The CO noise is assumed to drop by 20dB/decade over the frequency of interest while the RO phase noise is rather constant. The loop bandwidth is defined here as the bandwidth over which the PLL tracks the RO behaviour. From Fig. 10 it is readily understood that it may be selected roughly around the crossing of the multiplied RO phase noise and the CO phase noise (as illustrated) to minimize the overall phase noise.

Fig. 11 is an illustrative view of phase noise contributions from reference oscillator and controlled oscillator with low loop bandwidth. Fig. 12 is an illustrative view of phase noise contribution from reference oscillator and controlled oscillator with high bandwidth. If the loop bandwidth is chosen to be smaller or larger it leads to the principle phase noise shapes as illustrate in Figs 11 and 12, respectively.

The following examples aim to further illustrate the relation between RO and CO phase noise when used in a PLL and it should be understood that these examples are highly simplified; with simple phase noise models for RO and CO and that omit other significant phase noise contributors within a PLL like the divider and the phase detector. The loop bandwidth is primarily determined by the loop filter (Figure 4) of the PLL and the integrating property of the CO.

Below, f denotes a frequency, N denotes transform factor given by the PLL,

PN denotes phase noise and IPN denotes integrated phase noise. Index 1 denotes that the value is related to Example 1 , i.e. to distinguish from Example 2 which

consequently has index 2.

Example 1 :

Cellular UE radio: ¾ ROl - 26MHz, f _LO i = 2.6GHz. Ni = f _L oi/f _R oi = 100

40dB

PNROI@IROI = -140dBc/Hz→ PN _R oi@fLoi = ΡΝ _ΚΟ Ι@Η ΟΙ + N _dB ,i = -lOOdBc/Hz PNcoi@fLoi = -120dBc/Hz @f ₀ ff _se t,i = lMHz→

PN _RO i@fLoi = PNcoi@fLoi = - lOOdBc/Hz @f ₀ ff _S et,i = BWi _oop ,i = 100kHz

Integrated phase noise:

IPNi = - lOOdBc/Hz + 10 logl0(BWi _oop ,i)+ 10 logl0(7i/2) = -48dBc The π/2 factor is the equivalent noise bandwidth for a first order system.

When most of the phase noise power resides within the bandwidth of the signal the integrated phase noise power roughly defines the minimum attainable EVM or the reciprocal of the maximum attainable SNR. Thus, in the example above the SNR can never be better than 48dB (assumes no correction/tracking of the phase noise frequency range considered).

Example 2:

mmW radio: f _R02 = 60MHz, f _L02 = 60GHz. N ₂ = f _L o ₂ /f _R o ₂ = 1000→

N _dB,2 =60dB

PNRo ₂ (¾fRo ₂ ⁼ -160dBc/Hz→ PN _R02 (®fL02 - PNR02(¾fR0 ₂ + N _dB , ₂ = -100dBc/Hz

PN _c02 @fLo ₂ = -130dBc/Hz @f ₀ ff _S et, ₂ = 10MHz→

PN _R02 @fLo ₂ = PN _c02 @fLo ₂ = -100 dBc/Hz @f ₀ ff _S et, ₂ = BWi _oop , ₂ = 316kHz

Integrated phase noise:

IPN ₂ = - lOOdBc/Hz + 10 loglO(BWi _oop , ₂ ) + 10 logl0(7i/2) = - 43dBc

In this example the IPN is 5dB worse than in Example 1, yet the RO phase noise specification is very much tougher, 20dB lower phase noise with an operating frequency that is more than twice as high. Also, the CO figure of merit, defined as

FoMco=PN@f _offS et+20-loglO(f _offse t/fco) + 10-logl0(Pdc,mw/lmW),

(the lower, the higher performance) is somewhat different in the two cases (assuming same Pdc,mw):

FoM _c02 - FoMcoi = -130 + (-68.3) - (-120 + (-75.6) ) -2.7dB

Thus C0 ₂ would need a FoM some 3dB better than COi. Since the FoM for a mmW CO reasonably cannot be expected to be any higher than a state-of-the-art CO operating at low-GHz frequencies it is concluded that the power consumption will need to be higher in the mmW CO too.

All in all, achieving the same integrated phase noise at mmW as in low-GHz range leads to substantially higher requirements and foremost this comes at the cost of increased power consumption in the RO. In the above two cases the RO would typically consume a few mW in Example 1 whereas in Example 2 that would jump to 100's of mW. The impact of the RO can be reduced by lowering the loop bandwidth but then comes at the expense of higher requirements on the CO and consequently higher power consumption in the CO. Furthermore, a small loop bandwidth will result in longer time to lock for the PLL. In battery operated transceivers, power is saved by turning off blocks that are not used. This can be done on a very small time scale, say between receptions of data bursts, say with a cycle of 10's of ms to 10's of μβ. This means that a slow PLL, i.e. with small loop bandwidth, needs to be powered on a long time relative to the time it is actually being used, i.e. during reception/transmission, to reach lock before use. This will negatively affect the power saved by switching off the PLL between uses.

Fig. 1 schematically illustrates a reference oscillator arrangement 100 according to an embodiment. The reference oscillator arrangement 100 comprises a controller 102 and a reference oscillator 105 comprising a resonator core 104 and a buffer arrangement 106.

The resonator core 104 comprises a reference resonator, e.g. a crystal or MEMS resonator. The resonator core further comprises a driving circuit for the reference resonator. An example of a resonator core will be demonstrated with reference to Fig. 2.

The buffer arrangement 106 is connected to the resonator core 104 to receive an oscillating signal provided by the resonator core 104, and comprises an active circuit for providing an output of the reference oscillator arrangement 100.

The reference oscillator arrangement 100 is arranged to provide a reference signal for a communication apparatus capable of communicating according to a plurality of transport formats, and may then be adapted to provide suitable properties of the reference signal, and then particularly in sense of sufficiently low phase noise for the different transport formats while keeping power consumption reasonable. The controller 102 is arranged to receive information about an applied transport format and control the driving circuit of the resonator core 104 and/or the active circuit of the reference oscillator buffer arrangement 106.

The resonator core 104 may be controlled by providing suitable biasing, wherein flicker noise is controlled, and thereby phase noise.

The reference oscillator buffer arrangement 106 is arranged to provide a reference oscillator output with adapted properties of the oscillating signal. The one or more buffers of the reference buffer arrangement comprises an active circuit which may include an inverter. The properties of the oscillating signal may be slope, amplitude, flicker noise, thermal noise, shot noise, slew rate, etc. For example, by adjusting driving capability, e.g. by selecting size of the inverter of the used buffer, slope and/or amplitude may be adjusted. By selecting size of an active circuit, e.g. amplifier, flicker noise may be adjusted. By selecting DC current in the active circuit, slew rate, amplitude, flicker noise, thermal noise and shot noise may be controlled. Other adjustments that may be made are supply voltage, operating point, sizes of selected devices (e.g. transistors), etc.

The reference oscillator buffer arrangement 106 may comprise a plurality of buffers for providing a corresponding plurality of output signals to different circuits of the communication apparatus, e.g. to a receiver and to a transmitter. Thus, in

embodiments, each buffer comprises its own active circuit, wherein they may be individually controllable, e.g. based on different demands from the respective circuits.

The controlling of the resonator core 104 may be sensitive to changes during operation, i.e. transmission and/or reception of a communication burst, and the adaption of control settings for the resonator core 104 may therefore be set for the burst and then not changed until next burst. The controlling of the buffer arrangement on the other hand may be changed essentially instantaneously, wherein adaptions may be made during a burst. An approach for the control in light of this is further elucidated with reference to Fig. 7. The controlling may be made based on different models of requirements from the circuit or circuits provided with reference signal(s). An approach is to provide control to the resonator core 104 in line with the demands of the circuit and/or transport format putting the most critical requirements, and then provide control to the buffer(s) based on respective actual demands. According to an embodiment, the controller 102 comprises a look-up table comprising a mapping between transport formats and control setting suitable for the respective transport formats.

Fig. 2 schematically illustrates an example of a resonator core 200 The resonator core 200 comprises a driver circuit 202, a reference resonator 204, and circuitry 206, 208 for shunting output terminals. The driver circuit 102 drives the reference resonator 104 to oscillate at a particular frequency to define a differential output signal across the output terminals.

Fig. 3 schematically illustrates an example of a reference oscillator buffer 300. The example illustrates a differential amplifier, where the oscillating signal from the resonator core is provided to inputs Vi _p , Vi _n and the oscillator output is provided at outputs V _0p , V _on . The differential amplifier comprises a current generator transistor 302, a pair of serially connected transistors, where each pair includes an inverting transistor 304, 305 and a load transistor 306, 307.

Other examples of resonator core and/or buffer may be feasible.

Fig. 4. schematically illustrates a controller 400 according to an embodiment. The controller 400 is controlling a reference oscillator 402 as demonstrated above. The controller 400 is arranged to receive information about transport formats applied by a communication device in which the reference oscillator arrangement operates, and comprises a look-up table 404 where transport formats TF0, TF1, ..., TFn are mapped to control settings CS0, CS 1 , ... , CSn, wherein the control setting corresponding to the received transport format information is provided to the oscillator 402. For cases where e.g. multiple circuits, multiple transport formats, etc. are actual at the same time, the look-up table may be a more complex structure, e.g. an n-dimensional matrix.

Fig. 5 schematically illustrates an oscillator arrangement 500 according to an embodiment. The oscillator arrangement 500 comprises a controller 502, a reference oscillator 504, and a phase-locked loop, PLL, circuit 506. The controller 502 controls the reference oscillator 504 according to any of the approaches demonstrated above. The PLL circuit 506 comprises a phase detector 508, a loop filter 510, a controlled oscillator 512 and a divider circuit 514. The phase detector 508 is arranged to detect a phase difference between a signal provided from the reference oscillator 504 and a signal provided from the divider circuit 514. The output may be a charge based on the detected phase difference which is provided to the loop filter 510 which may low-pass filter the signal and provide a control signal to the controlled oscillator 512, e.g. a control voltage to a voltage controlled oscillator. The controlled oscillator 512 generates a frequency based on the control signal which is provided as output of the oscillator arrangement 500, but is also fed back via the divider circuit 514 to the phase detector 508. The PLL circuit 506 will lock to a frequency that is determined by the reference oscillator frequency and the division factor of the divider circuit 514. The time to lock to this frequency is very much depending on loop bandwidth as defined by the loop filter 510, but also on controllability of the controlled oscillator 512 and the ability to detect large phase errors by the phase detector 508. The loop bandwidth also has an impact on phase noise, where large loop bandwidth may provide large phase noise, and vice versa. In line with the discussion above about how to adapt settings of the reference oscillator to phase noise demands, this may also be applied to the PLL circuit 506, wherein the oscillator arrangement 500. Thus, the controller 502 is arranged to control the PLL circuit 506 to achieve desired phase noise output by the oscillator arrangement 500. This is performed by providing a control set to the PLL circuit 506, which may comprise settings for the loop filter 510 and/or the controlled oscillator 512. Similar as demonstrated above, the control settings may be based on different control models, and may also utilize a look-up table with suitable control settings for different transport formats. The look-up table may be formed by pre-calculated and/or simulated values for the different transport formats, and also other more complex configurations, as has been discussed above with reference to provision of signals to different circuits and for different demands simultaneously.

Fig. 6 is a flow chart illustrating a method according to an embodiment.

Information about one or more applied transport formats is received 600, wherein the resonator core and/or the one or more reference oscillator buffers are controlled 602 accordingly, as has been discussed above. The resonator core is then enabled to provide 604 an oscillating signal to the reference oscillator buffer arrangement, wherein the reference oscillator buffer arrangement provides 606 the oscillator output. Optionally, as has been discussed with reference to Fig. 6 above, the PLL circuit may also be controlled 608.

Fig. 7 is a flow chart illustrating a method according to an embodiment. The controlling of the resonator core may be sensitive to changes during operation, i.e. transmission and/or reception of a communication burst, and the adaption of control settings for the resonator core may therefore be set for the burst and then not changed until next burst. The controlling of the buffer arrangement on the other hand may be changed essentially instantaneously, wherein adaptions may be made during a burst.

The method comprises receiving 700 information about one or more applied transport formats, wherein the resonator core is controlled 702 and the control buffer arrangement is controlled 704 according to any of the approaches that have been discussed above. Optionally, the PLL circuit may also be controlled 706, as discussed above. The reference oscillator arrangement or oscillator arrangement may then provide 708 a signal. Reception of new transport format information is monitored 710. As long as no new information about transport formats is received, the reference oscillator arrangement or oscillator arrangement provides 708 a signal according to the current control settings. If new information about transport format is received, it is checked 712 if a new burst is to commence. If within an ongoing burst, the procedure returns to controlling the buffer arrangement 704 according to new control settings being based on the new transport format information, and possible controlling 706 of PLL circuit, and the monitoring 710 of new transport format information while providing 708 the signal accordingly. If a new burst is about to commence the procedure also includes controlling 702 the resonator core, as well as the controlling the buffer arrangement 704 according to new control settings being based on the new transport format information, and possible controlling 706 of PLL circuit, and the monitoring 710 of new transport format information while providing 708 the signal accordingly. Upon use of a look-up table for the embodiment demonstrated with reference to Fig. 7, the table may include control settings where a certain control setting for the resonator core is presumed, wherein the control settings for the buffer arrangement, and possibly the PLL circuit, are mapped accordingly to new received information about transport format. Furthermore, the impact on phase and frequency stability may differ depending on controlling the resonator core and buffers, which may be considered when forming the control model and/or look-up table.

An alternative to changing the loop bandwidth is to change the phase noise performance also of the CO in accordance with the RO phase noise, with a maintained loop bandwidth, so that an increase in RO phase noise is also accompanied by an increase of CO phase noise and vice versa.

Fig. 8 is a block diagram schematically illustrating a communication device 800 according to an embodiment. The communication device comprises an antenna arrangement 802, a receiver 804 connected to the antenna arrangement 802, a transmitter 806 connected to the antenna arrangement 802, a processing element 808 which may comprise one or more circuits, one or more input interfaces 810 and one or more output interfaces 812. The interfaces 810, 812 may be user interfaces and/or signal interfaces, e.g. electrical or optical. The communication device 800 is arranged to operate with a radio access network. For example, the communication device 800 may be arranged to operate in a cellular communication network, a wireless local area network, a wireless mesh network, etc. The communication device 800 is further arranged to communicate according to a plurality of transport formats. The processing element 808 may fulfill a multitude of tasks, ranging from signal processing to enable reception and transmission since it is connected to the receiver 804 and transmitter 806, executing applications, controlling the interfaces 810, 812, etc. The processing element 808 may for example provide information about transport format to be used for transmission and/or reception.

The methods according to the present invention is suitable for implementation with aid of processing means, such as computers and/or processors, especially for the case where the controllers demonstrated above comprises a processor handling control settings of a reference oscillator and/or oscillator arrangement. Therefore, there is provided computer programs, comprising instructions arranged to cause the processing means, processor, or computer to perform the steps of any of the methods according to any of the embodiments described with reference to Figs 5 or 6. The computer programs preferably comprises program code which is stored on a computer readable medium 900, as illustrated in Fig. 9, which can be loaded and executed by a processing means, processor, or computer 902 to cause it to perform the methods, respectively, according to embodiments, preferably as any of the embodiments described with reference to Figs 5 or 6. The computer 902 and computer program product 900 can be arranged to execute the program code sequentially where actions of the any of the methods are performed stepwise. The processing means, processor, or computer 902 is preferably what normally is referred to as an embedded system. Thus, the depicted computer readable medium 900 and computer 902 in Fig. 9 should be construed to be for illustrative purposes only to provide understanding of the principle, and not to be construed as any direct illustration of the elements.