Title:
OSCILLATOR CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2023/145242
Kind Code:
A1
Abstract:
The interval between an input node (Na) of a first logic circuit (10) which includes a first logic inversion circuit and a second logic circuit (30) which has one or more second logic inversion circuits is provided with a plurality of signal paths (IPT1-IPTM) in parallel which are configured so as to pass through the first logic inversion circuit. A selection unit (20) selects one of the plurality of signal paths (IPT1-IPTM), and inputs an output signal from the first logic inversion circuit (10) into the second logic circuit (20). A feedback resistor (40) and a feedback capacitor (50) form a signal feedback path between the second logic circuit 30 and the input node (Na). The plurality of signal paths (IPT1-IPTM) are formed in a manner such that the inversion threshold voltage of the first logic inversion circuit and/or the difference between the transmission delay time at the leading edge of the output signal from the first logic inversion circuit and at the trailing edge thereof are different from one another.
Inventors:
ISHIHARA TAKAHIRO (JP)
KOJIMA TOMOKAZU (JP)
KAMIMURAI AKIO (JP)
KOJIMA TOMOKAZU (JP)
KAMIMURAI AKIO (JP)
Application Number:
PCT/JP2022/043959
Publication Date:
August 03, 2023
Filing Date:
November 29, 2022
Export Citation:
Assignee:
MITSUBISHI ELECTRIC CORP (JP)
International Classes:
H03K3/017; H03K3/03; H03K3/354
Foreign References:
| JPH07202687A | 1995-08-04 | |||
| JPH08116239A | 1996-05-07 | |||
| JP2005051673A | 2005-02-24 |
Attorney, Agent or Firm:
FUKAMI PATENT OFFICE, P.C. (JP)
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