TECHNICAL FIELD

The present disclosure relates generally to the field of oscillator management. More particularly, it relates to collective management of a plurality of oscillators.

BACKGROUND

Power consumption and implementation footprint (e.g., chip area) are concerns that are often highly relevant for communication hardware. Such concerns may be particularly relevant for large-scale systems.

For example, controlling a multi-antenna system (e.g., for beamforming) may require a plurality of antenna element controlling functions (e.g., including phase-locked loop, PLL, functionality) to operate in parallel, wherein power consumption and implementation footprint typically increases when the number of antenna elements increases. Thus, for large-scale multi-antenna systems (e.g., massive multiple-input multiple-output, MIMO, systems) power consumption and implementation footprint may become very cumbersome.

Therefore, there is a need for alternative approaches to implementation of communication hardware.

Preferably, such communication hardware implementation approaches enable lower power consumption and/or smaller implementation footprint than other approaches; particularly for large-scale systems.

SUMMARY

It should be emphasized that the term "comprises/comprising" (replaceable by "includes/including") when used in this specification is taken to specify the presence of stated features, integers, steps, or components, but does not preclude the presence or addition of one or more other features, integers, steps, components, or groups thereof. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Generally, when an arrangement is referred to herein, it is to be understood as a physical product; e.g., an apparatus. The physical product may comprise one or more parts, such as controlling circuitry in the form of one or more controllers, one or more processors, or the like.

It is an object of some embodiments to solve or mitigate, alleviate, or eliminate at least some of the above or other disadvantages.

A first aspect is an oscillator management circuitry for controlling a plurality of oscillators. The oscillator management circuitry comprises a phase detector configured to determine a difference between a first periodic signal and a second periodic signal. The oscillator management circuitry also comprises selection circuitry configured to feed an output signal of the phase detector to a selected oscillator of the plurality of oscillators, and to provide a feedback signal from the selected oscillator as the second periodic signal. Furthermore, the oscillator management circuitry comprises controlling circuitry configured to provide timesharing of the phase detector among the plurality of oscillators by varying over time which of the plurality of oscillators is selected.

In some embodiments, the phase detector is a time-to-digital converter (TDC).

In some embodiments, the selection circuitry comprises a de-multiplexer for feeding the output signal of the phase detector to the selected oscillator, and an oscillator selection multiplexer for providing the feedback signal from the selected oscillator as the second periodic signal.

In some embodiments, the controlling circuitry is configured to operate the selection circuitry based on the varying oscillator selection.

In some embodiments, the controlling circuitry is configured to let each oscillator of the plurality of oscillators be selected exactly once during a time-sharing cycle.

In some embodiments, an order of oscillator selection is the same for each time-sharing cycle.

In some embodiments, an order of oscillator selection is different between at least two timesharing cycles.

In some embodiments, the order of oscillator selection is randomized for each time-sharing cycle. In some embodiments, the plurality of oscillators is between two and a maximum amount.

In some embodiments, the maximum amount of oscillators is lower than, or equal to, a ratio between periods of the first and second periodic signals.

In some embodiments, the oscillator management circuitry further comprises a multi-phase generator configured to provide a plurality of differently delayed instances of an input signal, and the selection circuitry is further configured to provide a selected instance of the differently delayed instances as the first periodic signal.

In some embodiments, the selection circuitry comprises an instance selection multiplexer for providing the selected instance as the first periodic signal.

In some embodiments, the controlling circuitry is further configured to vary over time which of the differently delayed instances is selected.

In some embodiments, the controlling circuitry is configured to operate the selection circuitry based on the varying instance selection.

In some embodiments, the controlling circuitry is configured to let each instance of the differently delayed instances be selected exactly once during a time-sharing cycle.

In some embodiments, an order of instance selection is the same for each time-sharing cycle.

In some embodiments, an order of instance selection is different between at least two timesharing cycles.

In some embodiments, the order of instance selection is randomized for each time-sharing cycle.

In some embodiments, each selected oscillator is combined with the same selected instance for each time-sharing cycle.

In some embodiments, each selected oscillator is combined with different selected instances between at least two time-sharing cycles.

In some embodiments, the combination between selected oscillator and selected instance is randomized for each time-sharing cycle. In some embodiments, the oscillator management circuitry further comprises compensation circuitry for the output signal of the phase detector.

In some embodiments, the compensation circuitry is configured to counteract the delay of the selected instance.

In some embodiments, the controlling circuitry is configured to operate the compensation circuitry based on the varying instance selection.

In some embodiments, the controlling circuitry is further configured to operate the compensation circuitry based on a calibration value for the selected oscillator.

In some embodiments, the controlling circuitry is further configured to determine the calibration value for each oscillator of the plurality of oscillators as an average periodicity count of the second periodic signal per period of the first periodic signal during an activation of the oscillator, wherein identical tuning is applied for the plurality of oscillators.

In some embodiments, the oscillator management circuitry further comprises the plurality of oscillators.

In some embodiments, the oscillator management circuitry is implemented on a single circuit tile.

A second aspect is a phase-locked loop (PLL) arrangement for functionally implementing a plurality of parallel digital PLLs. The PLL arrangement comprises the oscillator management circuitry of the first aspect, and each oscillator of the plurality of oscillators is comprised in a respective one of the plurality of parallel digital PLLs.

In some embodiments, the first periodic signal represents a PLL reference frequency signal and the second periodic signal represents a PLL variable clock signal.

In some embodiments, the oscillator management circuitry further comprises an accumulator configured to provide a PLL control signal based on a target frequency and a reference frequency.

In some embodiments, the accumulator is a single accumulator shared by the parallel digital PLLs. In some embodiments, the oscillator management circuitry further comprises a frequency- locked loop (FLL) for the PLL arrangement. For example, the oscillator management circuitry may further comprise a counter configured to provide an FLL for the PLL arrangement.

In some embodiments, the FLL is a single FLL shared by the parallel digital PLLs. For example, a single counter may be shared by the parallel PLLs, thereby forming a single FLL

A third aspect is a multi-antenna system controller comprising the PLL arrangement of the second aspect.

A fourth aspect is a communication device comprising one or more of: the multi-antenna system controller of the third aspect, the PLL arrangement of the second aspect, and the oscillator management circuitry of the first aspect.

A fifth aspect is an oscillator management method for providing time-sharing of a phase detector among a plurality of oscillators, wherein the phase detector is configured to determine a difference between a first periodic signal and a second periodic signal. The oscillator management method comprises selecting an oscillator among the plurality of oscillators, wherein it is varied over time which of the plurality of oscillators is selected, feeding (434) an output signal of the phase detector to the selected oscillator, and providing a feedback signal from the selected oscillator as the second periodic signal.

In some embodiments, any of the above aspects may additionally have features identical with or corresponding to any of the various features as explained above for any of the other aspects.

An advantage of some embodiments is that alternative approaches to implementation of communication hardware are provided.

An advantage of some embodiments is decreased power consumption.

An advantage of some embodiments is decreased implementation footprint.

An advantage of some embodiments is that communication hardware implementation is provided which is suitable for large-scale systems (e.g., having lower power consumption and/or smaller implementation footprint than other implementations of large-scale systems). An advantage of some embodiments is that a plurality of antenna element controlling functions operating in parallel can be efficiently implemented (e.g., in terms of power consumption and/or implementation footprint).

An advantage of some embodiments is that, since a phase detector (e.g., a time-to-digital converter, TDC) can be shared among a plurality of oscillators, the functionality relating to the phase detector (e.g., the phase detector itself, the linearization of the phase detector, etc.) need not be multiplied to the same extent as the oscillators. This can be particularly beneficial since the functionality relating to phase detectors (e.g., a phase detector itself, the linearization of a phase detector, etc.) typically have relatively high power consumption and/or relatively large implementation footprint. Thus, if the number of phase detectors can be decreased, power consumption and/or implementation footprint may be substantially decreased.

An advantage of some embodiments is that architecture planning can be simple. For example, less phase detectors are needed than in other solutions (e.g., a single phase detector may be sufficient). Furthermore, only non-time critical signals need to be routed to each oscillator.

Generally, it should be noted that when power consumption is referred to herein, the associated statement is equally applicable to energy consumption; and vice versa.

BRIEF DESCRIPTION OF THE DRAWINGS

Further objects, features and advantages will appear from the following detailed description of embodiments, with reference being made to the accompanying drawings. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the example embodiments.

Figure 1 is a schematic block diagram illustrating an example arrangement comprising oscillator management circuitry according to some embodiments;

Figure 2 is a schematic block diagram illustrating an example phase-locked loop (PLL) arrangement according to some embodiments;

Figure 3 is a schematic block diagram illustrating an example communication device according to some embodiments; and

Figure 4 is a flowchart illustrating example method steps according to some embodiments. DETAILED DESCRIPTION

As already mentioned above, it should be emphasized that the term "comprises/comprising" (replaceable by "includes/including") when used in this specification is taken to specify the presence of stated features, integers, steps, or components, but does not preclude the presence or addition of one or more other features, integers, steps, components, or groups thereof. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

Embodiments of the present disclosure will be described and exemplified more fully hereinafter with reference to the accompanying drawings. The solutions disclosed herein can, however, be realized in many different forms and should not be construed as being limited to the embodiments set forth herein.

As already mentioned, there is a need for alternative approaches to implementation of communication hardware, to enable low power consumption and/or small implementation footprint; particularly for large-scale systems.

One example context where this need arises is multi-antenna large-scale systems (e.g., massive multiple-input multiple-output, MIMO, systems), where power consumption and implementation footprint typically increases when the number of antenna elements increases.

It should be noted that, even if some problems and some embodiments are described herein with reference to multi-antenna systems such as MIMO systems, this is not intended as limiting. Contrarily, such problems and/or such embodiments may be equally applicable in any context where a plurality of oscillators are to be managed (e.g., when two or more oscillators reside on the same chip, and/or when two or more oscillators are included in respective phase-locked loops, PLLs, configured to operate in parallel).

Generally, it should be noted that when a (hardware, HW) chip is referred to herein, the associated statement is equally applicable to any type of circuit tile.

Figure 1 schematically illustrates an example arrangement comprising oscillator management circuitry 100 according to some embodiments. The oscillator management circuitry 100 may be implemented on a single chip according to some embodiments. The oscillator management circuitry 100 is for controlling a plurality of oscillators (OSC) 191, 192. For example, the oscillator management circuitry 100 may be configured to control the plurality of oscillators 191, 192. In some embodiments, the oscillator management circuitry comprises the plurality of oscillators.

Each oscillator may be any suitable oscillator; examples including a voltage controlled oscillator (VCO), and a digitally controlled oscillators (DCO). Each oscillator of the plurality of oscillators 191, 192 may, for example, be an oscillator of a corresponding phase-locked loop (PLL); e.g., associated with the control of a respective antenna element of a multi-antenna system.

Optionally, each of the plurality of oscillators 191, 192 is preceded by a low-pass filter (LPF) 181, 182.

The oscillator management circuitry 100 comprises a phase detector (PD; e.g., a time-to-digital converter, TDC) 110. As will be explained in the following, the phase detector 110 (and typically also associated circuitry, such as circuitry for linearization of the phase detector) is shared among the plurality of oscillators 191, 192. Thereby, reduced power consumption and/or reduced implementation footprint is enabled compared to solutions where each oscillator is associated with a corresponding dedicated phase detector. In some embodiments, time-sharing of the phase detector is achieved by assigning, to each oscillator, a respective time slot within a time-sharing cycle, wherein the phase detector is dedicated to the corresponding oscillator. For example, a time slot may be defined by (e.g., comprise, or be equal to, a period of a first periodic signal input to the phase detector.

In the following, embodiments will be exemplified where a single phase detector 110 is shared by a plurality of oscillators 191, 192. However, this should not be understood as limiting. Generally, a single phase detector may be shared among all oscillators to be managed (e.g., among all oscillators of PLLs configured to operate in parallel), or two or more phase detectors may be shared among all oscillators to be managed (where the number of phase detectors is less than the number of oscillators).

For example, all oscillators to be managed that are implemented on a same chip may share a single phase detector, or a subset of the oscillators to be managed that are implemented on the same chip may share a single phase detector (e.g., 16 oscillators may share two phase detectors by being divided into two subsets of eight oscillators each, wherein each subset shares one of the two phase detectors; or 16 oscillators may share four phase detectors by being divided into four subsets of four oscillators each, wherein each subset shares one of the four phase detectors).

Furthermore, it should be noted that the plurality of oscillators may refer to all oscillators sharing a phase detector, or to a subset thereof. For example, when a set of oscillators are implemented to share a phase detector and one or more of the oscillators are configured to be dynamically active/inactivate (e.g., to reduce power consumption), the plurality of oscillators may refer to the currently active oscillators. Dynamic activation/inactivation may, for example, be performed via configuration setting when oscillator operation is initiated.

The number of oscillators that share the same phase detector may be limited to a maximum amount according to some embodiments. Thus, the plurality of oscillators may be between two and the maximum amount.

The phase detector 110 is configured to determine a difference between a first periodic signal

102 and a second periodic signal 103. This function of the phase detector 110 may be implemented using any suitable approach (e.g., a phase detection approach according to the prior art).

Generally, the difference between the first periodic signal 102 and the second periodic signal

103 may be a time difference and/or a phase difference.

Typically, the difference between the first periodic signal and the second periodic signal is determined as a difference in time between corresponding reference points of the first and second periodic signals. For example, corresponding reference points may be up flank zerocrossings (rising edges) or down flank zero-crossings (falling edges) of the first and second periodic signals.

A representation of the determined difference (e.g., a difference in time and/or phase) between the first periodic signal and the second periodic signal is output from the phase detector.

The oscillator management circuitry 100 also comprises selection circuitry. The selection circuitry comprises a first selection circuitry portion 121 (SEL1; e.g., a de-multiplexer) configured to feed an output signal of the phase detector to a selected oscillator of the plurality of oscillators 191, 192. The selection circuitry also comprises a second selection circuitry portion 122 (SEL2; e.g., an oscillator selection multiplexer) configured to provide a feedback signal from the selected oscillator as the second periodic signal 103.

Typically, the maximum amount of oscillators that share the same phase detector is lower than, or equal to, a ratio between the period P _± of the first periodic signal 102 and the period P ₂ second periodic signal 103. For example, the maximum amount of oscillators that share the same phase detector may be determined as where M > 0 represents a margin. This approach enables the phase detector 110 to capture at least one period of the second periodic signal 103 for each of the plurality of oscillators 191, 192 during a period of the first periodic signal 102; thereby enabling proper function (e.g., for a PLL arrangement).

The oscillator management circuitry 100 also comprises controlling circuitry (CNTR) 130 configured to provide time-sharing of the phase detector 110 among the plurality of oscillators 191, 192 by varying over time which of the plurality of oscillators is selected. The controlling circuitry 130 may be implemented using any suitable approach (e.g., by a suitably programmed digital signal processor, DSP).

The controlling circuitry 130 may provide the time-sharing of the phase detector among the plurality of oscillators by operating the selection circuitry based on the varying oscillator selection. For example, the controlling circuitry 130 may operate the first and second selection circuitry portions 121, 122 by corresponding first and second control signals 106, 107. Thus, the first and second control signals 106, 107 may be indicative of the selected oscillator. The first and second control signals 106, 107 may be implemented as a single signal provided to both first and second selection circuitry portions 121, 122, or as separate signals.

A time-sharing cycle may be defined as a period of time during which the controlling circuitry 130 provides time-sharing of the phase detector 110 among the plurality of oscillators 191, 192. For example, a time-sharing cycle may be equal to (or shorter than) the period P _± of the first periodic signal 102.

Typically, the controlling circuitry 130 is configured to let each oscillator 191, 192 of the plurality of oscillators be selected exactly once during a time-sharing cycle (i.e., all oscillators of the plurality of oscillators are selected a first time before any oscillator of the plurality of oscillators is selected a second time, etc.).

The order of oscillator selection may be the same for each time-sharing cycle (i.e., the oscillators may be selected in the same sequence, iteratively repeated for each time-sharing cycle), or the order of oscillator selection may be different between at least two time-sharing cycles (e.g., the order of oscillator selection may be randomized for each time-sharing cycle; for example, using some suitable pseudo-random sequence generator). Randomizing the order of oscillator selection may be beneficial to mitigate the effect of non-linearities in the PLL feedback paths.

Optionally, the oscillator management circuitry 100 may comprise a multi-phase generator (MPG; e.g., an N-phase generator, a polyphase filter, or a digital-to-time converter, DTC) 140 configured to provide a plurality of differently delayed instances of an input signal 101. For example, the input signal 101 may be a PLL reference frequency signal, FREF, and the multiphase generator 140 may be configured to provide a plurality of FREF instances with different phase shifts. The function of the multi-phase generator 140 may be implemented using any suitable approach (e.g., a multi-phase generator approach according to the prior art).

When a multi-phase generator 140 is comprised in the oscillator management circuitry 100, the selection circuitry may comprise a third selection circuitry portion 123 (SEL3; e.g., an instance selection multiplexer) configured to provide a selected instance of the differently delayed instances provided by the multi-phase generator 140 as the first periodic signal 102.

When the oscillator management circuitry 100 does not comprise a multi-phase generator 140, the input signal 101 may be directly provided as the first periodic signal 102.

According to some embodiments, the multi-phase generator 140 may be excluded when the input signal 101 has a sufficiently short period (e.g., shorter than an input signal period threshold). Then, a time-sharing cycle may correspond to (or be longer than) a multiple of the period of the input signal 101, wherein the multiple is at least as large as the number of oscillators, and each period of the input signal 101 can accommodate one oscillator selection of the time-sharing cycle. Thus, each of the feedback signals from the oscillators can be selected as the second periodic signal 103 for a time duration that corresponds to (or is longer than) a period of the input signal 101. For example, the input signal period threshold may correspond to a period duration for which the frequency of the input signal 101 is larger than a value relating to the PLL bandwidth (e.g., the frequency of the input signal 101 being at least ten times larger than the PLL bandwidth multiplied by the number of oscillators of the plurality).

When a multi-phase generator 140 is comprised in the oscillator management circuitry 100, the controlling circuitry 130 may be configured to vary over time which of the differently delayed instances is selected, e.g., by operating the selection circuitry based on the varying instance selection. For example, the controlling circuitry 130 may operate the third selection circuitry portion 123 by a corresponding third control signal 108. Thus, the third control signal 108 may be indicative of the selected instance.

Typically, the controlling circuitry 130 is configured to let each instance of the differently delayed instances be selected exactly once during a time-sharing cycle.

The order of instance selection may be the same for each time-sharing cycle (i.e., the instance may be selected in the same sequence, iteratively repeated for each time-sharing cycle), or the order of instance selection may be different between at least two time-sharing cycles (e.g., the order of instance selection may be randomized for each time-sharing cycle; for example, using some suitable pseudo-random sequence generator).

In some embodiments, each selected oscillator is combined with the same selected instance for each time-sharing cycle (i.e., during different time-sharing cycles, a selected oscillator is always operated based on the same instance of the input signal 101). In such embodiments, the first, second, and third control signals 106, 107, 108 may be implemented as a single signal provided to the first, second, and third selection circuitry portions 121, 122, 123; or as separate signals.

In some embodiments, each selected oscillator is combined with different selected instances between at least two time-sharing cycles (i.e., during two different time-sharing cycles, a selected oscillator is operated based on different instances of the input signal 101). For example, the combination between selected oscillator and selected instance may be randomized for each time-sharing cycle (e.g., using some suitable pseudo-random sequence generator). These embodiments may be particularly useful when there is error propagation (e.g., due to nonlinearity) from the multi-phase generator to the phase detector and the selected oscillator. For example, combining a selected oscillator with different selected instances between at least two time-sharing cycles may provide dithering of any propagated errors, thereby reducing their negative impact.

Optionally, the oscillator management circuitry 100 may comprise compensation circuitry (COMP) 150 for the output signal of the phase detector 110.

This may be particularly beneficial when a multi-phase generator 140 is comprised in the oscillator management circuitry 100. For example, the compensation circuitry 150 may be configured to counteract the delay of the selected instance (e.g., by adding a phase correction to the output of the phase detector 110, wherein the phase correction corresponds to removal of the delay of the selected instance). When each selected oscillator is combined with the same selected instances for all time-sharing cycles, and no counteraction of the delay of the selected instance is made, proper function of the plurality of oscillators (e.g., for parallel PLL functionality) may be achieved despite the resulting offset between the different oscillators. When each selected oscillator is combined with different instances between at least two timesharing cycles, counteraction of the delay of the selected instance may be more important to achieve proper function of the plurality of oscillators.

When compensation circuitry 150 is comprised in the oscillator management circuitry 100, the controlling circuitry 130 may be configured to operate the compensation circuitry 150 (e.g., by a corresponding fourth control signal 109).

For example, the controlling circuitry 130 may operate the compensation circuitry 150 based on the varying instance selection. Thus, the fourth control signal 109 may be indicative of the selected instance. In such embodiments, the third and fourth control signals 108, 109 may be implemented as a single signal provided to both third selection circuitry portion 123 and the compensation circuitry 150, or as separate signals.

Alternatively or additionally, the controlling circuitry 130 may be configured to operate the compensation circuitry 150 based on a calibration value for the selected oscillator. Thus, the fourth control signal 109 may be indicative of the calibration value. In such embodiments, the third control signal 109 may be implemented as a separate signal. The controlling circuitry 130 may be configured to determine the calibration value for each oscillator 191, 192 of the plurality of oscillators (e.g., during a calibration procedure, wherein identical tuning is applied forthe plurality of oscillators 191, 192) as an average periodicity count of the second periodic signal 103 per period of the first periodic signal 102 during an activation of the oscillator.

It should be noted that the controlling circuitry 130 may be used for application of the calibration value regardless of whether or not a multi-phase generator 140 is comprised in the oscillator management circuitry 100.

Some example contexts where the oscillator management circuitry 100 may be applicable include phase-locked loop (PLL; particularly digital PLL, DPLL) contexts, delay-locked loop (DLL) contexts, and synthesizer contexts.

Furthermore, it should be noted that - although not shown in Figure 1 -the controlling circuitry 130 typically works synchronously with the oscillator loops (e.g., by being operated based on a common clocking signal). For example, the controlling circuitry 130 may operate in synchronization with the input signal 101.

Figure 2 schematically illustrates an example phase-locked loop (PLL) arrangement 200 according to some embodiments. The PLL arrangement 200 may be implemented on a single chip according to some embodiments.

The PLL arrangement 200 comprises a plurality of oscillators 291, 292 (e.g., local oscillators, LO) for functionally implementing a plurality of parallel digital PLLs, wherein each oscillator 291, 292 is comprised in a respective one of the plurality of parallel digital PLLs.

Optionally, each of the plurality of parallel digital PLLs also comprises a low-pass filter (LPF) 281, 282 preceding the corresponding oscillator 291, 292 and/or pre-scaler circuitry (PS) 271, 272 succeeding the corresponding oscillator 291, 292.

The PLL arrangement 200 also comprises oscillator management circuitry (e.g., an exemplification of the oscillator management circuitry 100 of Figure 1) for controlling the plurality of oscillators 291, 292. The PLL arrangement 200 comprises a time-to-digital converter (TDC) 210. The TDC 210 is shared among the plurality of oscillators 291, 292. Thereby, reduced power consumption and/or reduced implementation footprint is enabled compared to solutions where each oscillator is associated with a corresponding TDC.

The TDC 210 is configured to determine a difference (e.g., a difference in time and/or phase) between a PLL reference frequency signal 202 (FREF; compare with the first periodic signal 102 of Figure 1) and a PLL variable clock signal 203 (CKV; compare with the second periodic signal 103 of Figure 1), and output a representation of the determined difference.

Typically, the difference between the first periodic signal and the second periodic signal is determined as a difference in time between corresponding reference points of the first and second periodic signals. For example, corresponding reference points may be up flank zerocrossings (rising edges) or down flank zero-crossings (falling edges) of the first and second periodic signals.

The PLL arrangement 200 also comprises a de-multiplexer (DEMUX) 221 configured to feed an output signal of the phase detector to a selected oscillator of the plurality of oscillators 291, 292 (compare with the first selection circuitry portion 121 of Figure 1), and an oscillator selection multiplexer (MUX) 222 configured to provide a feedback signal from the selected oscillator as the PLL variable clock signal 203 (compare with the second selection circuitry portion 122 of Figure 1).

The PLL arrangement 200 also comprises a digital signal processor (DSP) 230 configured to provide time-sharing of the TDC 210 among the plurality of oscillators 291, 292 by varying over time which of the plurality of oscillators is selected (compare with the controlling circuitry 130 of Figure 1).

Optionally, the PLL arrangement 200 may comprise a multi-phase generator 240 (MPG; compare with 140 of Figure 1) configured to provide a plurality of differently delayed instances of an input PLL reference frequency signal 201 (FREF; compare with the input signal 101 of Figure 1).

In relation to a multi-phase generator 240, the PLL arrangement 200 may comprise an instance selection multiplexer (MUX) 223 which is configured to provide a selected instance of the differently delayed instances provided by the multi-phase generator 240 as the PLL reference frequency signal 202 (compare with the third selection circuitry portion 123 of Figure 1).

When the PLL arrangement 200 does not comprise a multi-phase generator 240, the input PLL reference frequency signal 201 may be directly provided as the PLL reference frequency signal 202.

When a multi-phase generator 240 is comprised in the PLL arrangement 200, the DSP 230 may be configured to vary over time which of the differently delayed instances is selected.

For example, the DSP 230 may operate the DEMUX 221 and the MUX(es) 222, 223 by corresponding control signal(s) indicative of the selected oscillator and - when applicable - the selected instance.

Numerous variations are possible for the selection of oscillator and instance as already exemplified in connection to Figure 1.

The input PLL reference frequency signal 201 may stem from any suitable source. In some embodiments, the input PLL reference frequency signal 201 is provided by an output of a preceding PLL arrangement when the PLL arrangement 200 is comprised in a sequence of cascaded PLL arrangements. In some embodiments, the input PLL reference frequency signal 201 is an external reference signal (which may be buffered or un-buffered).

Optionally, the PLL arrangement 200 may comprise compensation circuitry 250 for the output signal of the TDC 210 (compare with 150 of Figure 1). The compensation circuitry 250 is exemplified by addition circuitry in Figure 2.

For example, the compensation circuitry 250 may be configured to counteract the delay of the selected instance (e.g., by adding a phase correction 209 to the output of the TDC 210, wherein the phase correction 209 is provided by the DSP 230 and corresponds to removal of the delay of the selected instance; compare with 109 of Figure 1).

Alternatively or additionally, the compensation circuitry 250 may be configured to apply a calibration value for the selected oscillator as exemplified in connection with Figure 1.

The PLLarrangement 200 mayfurther comprise an accumulator (ACC) 260 configured to provide a PLL control signal 205 based on a target frequency (e.g., provided by a target frequency signal 204 indicating a frequency control word, FCW) and a reference frequency (e.g., indicated by the input PLL reference frequency signal 201). The accumulator may be a single accumulator shared by the parallel digital PLLs (more generally, the number of accumulators may be the same as the number of TDCs).

The PLL control signal 205 typically comprises an integer portion and a fractional portion. The fractional portion of the PLL control signal 205 may be provided to the compensation circuitry 250 for subtraction from the output signal of the TDC 210.

The PLL arrangement 200 may further comprise a frequency-locked loop (FLL) for the PLL arrangement 200. The FLL may be a single FLL shared by the parallel digital PLLs (more generally, the number of FLLs may be the same as the number of TDCs), or there may be one FLL per oscillator.

To implement the FLL, the PLL arrangement 200 may comprise a counter (CNT) 265 configured to provide the FLL for the PLL arrangement 200. The counter may be a single counter shared by the parallel digital PLLs, thereby forming a single FLL (more generally, the number of counters may be the same as the number of TDCs), or there may be one counter per oscillator.

The counter 265 operates based on the PLL variable clock signal 203 and the output may be subtracted from the integer portion of the PLL control signal 205 in combination circuitry 267. The resulting difference may be provided to the compensation circuitry 250 for combination with (e.g., addition to, or subtraction from) the output signal of the TDC 210.

When the frequency of FREF is large enough (e.g., larger than an FREF frequency threshold; for example, corresponding to that process, voltage, and temperature, PVT, effects on the oscillator frequencies are within the range LO±FREF), then the FLL loop which is exemplified by the counter 265 can be used to program all the oscillators and the TDC is able to handle the fractional error.

A calibration procedure may be used to handle situations where the frequency of FREF is not large enough (e.g., not larger than the FREF frequency threshold), and frequency variations are caused which causes the oscillator frequencies to fall outside the range LO±FREF.

For example, a calibration procedure may be implemented by setting the same tuning word for all oscillators and activating each oscillator at a time, wherein - for each activation - a high- speed counter (e.g., the counter 265) is used to estimate the ratio CKV/FREF. The ratio CKV/FREF may, for example, be estimated by counting how many CKV cycles occur during each of multiple (e.g., M = 2 ^X ) periods of FREF and taking the average. The estimated ratios, or corresponding correction words, may be stored as calibration values and used by the DSP 230 for calibration during frequency acquisition. This may be seen as one example of determining a calibration value for each oscillator of the plurality of oscillators as an average periodicity count of the second periodic signal per period of the first periodic signal during an activation of the oscillator, wherein identical tuning is applied for the plurality of oscillators.

It should be noted that the optional features of Figures 1 and 2 may be used in any suitable combination. For example, the accumulator 260 and the corresponding portion of the compensation circuitry 250 may be used in an implementation where the multi-phase generator 240 and the instance selection multiplexer 223 are excluded, as well as in an implementation where the multi-phase generator 240 and the instance selection multiplexer 223 are included. The FLL (e.g., the counter 265 and the addition circuitry 267) may be applied together with any other combination of optional features. Correspondingly, the low-pass filters 281, 282 and/or the pre-scaler circuitries 271, 272 may be applied together with any other combination of optional features.

It should be noted that - although not shown in Figure 2 - the controlling circuitry 230 typically works synchronously with the PLLs (e.g., by being operated based on a common clocking signal). For example, the controlling circuitry 230 may operate in synchronization with the input signal 201.

To further exemplify the benefits of some embodiments, it may be noted that there is a need for accurate local oscillator (LO) signals in wireless transceivers, and that LO signals are typically generated using phase locked loops (PLLs).

Digital PLLs are advantageous since they do not require any analog loop filter (which typically have large area capacitors), since they can support digital algorithms to speed up frequency hops, and since they are suitable for technology scale down (e.g., reduced supply voltage and increased channel length modulation having less impact on linearity than for analog PLLs). For any PLL application, it may be desired to achieve sufficiently low phase noise with limited power consumption and implementation footprint. A digital PLL typically relies on a time-to- digital converter (TDC) to provide phase error measurements for forming of an oscillator control signal of the PLL (compare with the difference in time and/or phase between the first periodic signal and the second periodic signal mentioned earlier). For proper PLL performance, the TDC typically needs to have high performance (e.g., low noise and high resolution to minimize phase noise, and high linearity to minimize spurs).

In multi-antenna systems a large number of wireless transceivers front-ends - each with a corresponding PLL - are typically deployed in parallel (e.g., performing frequency conversion). Beam steering functionality may, for example, be provided by the front-ends by configuring each of the PLLs to perform a respective phase shifting of its LO signal. Digital PLLs are advantageous also in this respect since beam steering may be accomplished by adding digital direct current (DC) offsets directly to the phase error provided by the TDC (i.e., the determined difference between the first periodic signal and the second periodic signal).

However, the TDCs tend to consume a substantial part of the power for a digital PLL arrangement (e.g., due to linearization and other implementation issues).

For example, the TDC may need to measure signal timing over a time interval that is typically at least as long as a LO cycle, with relatively high resolution. To achieve low in-band PLL phase noise, the timing resolution of the TDC is often required to be less than one inverter delay, which may prevent use of an implementation with a single delay line of inverters. Furthermore, the thermal noise and the 1// noise should also be low for the TDC, which is difficult to realize with long delay lines. The linearity of the TDC should be high when operating in fractional-N mode (i.e., when generating output frequencies that are non-integer multiples of the reference frequency) since non-linearities result in so-called fractional spurs. Fractional spurs may end up at frequencies close to the carrier frequency and they can be relatively strong. An example approach for handling of spurs is described in "A wideband 3.6 GHz Digital AZ fractional-N PLL with phase interpolation divider and digital spur cancellation", by M. Zanuso, et al., IEEE Journal of Solid-State Circuits, vol. 46, no. 3, March 2011, pp. 627-638. High linearity typically means that the matching accuracy must be high between delay line cells, which may entail increased physical sizes. Hence, achieving TDC functionality with high performance and low power consumption is cumbersome for digital PLL approaches; and particularly so for PLL approaches with multiple parallel PLL functionality, where each PLL may require its own linearization algorithm.

Some embodiments address this problem by sharing (reusing) a TDC among two or more different oscillators as described above.

Figure 3 schematically illustrates an example communication device (CD) 310 according to some embodiments (e.g., a radio access node such as a base station, BS, or an access point, AP; or a user device such as a user equipment, UE, or a station, STA).

The communication device 310 is associated with (e.g., connected, or connectable, to) a multiantenna system 340 (e.g., a matrix array of antenna elements). The communication device 310 comprises a transceiver (TX/RX) 320 which, in turn, comprises a multi-antenna system controller (MAS CNTR) 300.

The multi-antenna system controller 300 is configured to control the operation of the transceiver 320 in relation to the multi-antenna system 340 (e.g., for steering of beams according to a beamforming approach).

To this end, the multi-antenna system controller 300 comprises oscillator management circuitry wherein a phase detector is shared among a plurality of oscillators (e.g., the oscillator management circuitry 100 of Figure 1). For example, the multi-antenna system controller 300 may comprise a PLL arrangement wherein a TDC is shared among a plurality of oscillators (e.g., the PLL arrangement 200 of Figure 2).

Figure 4 illustrates an example method 400 according to some embodiments. The method 400 is an oscillator management method for providing time-sharing of a phase detector among a plurality of oscillators. For example, the method 400 may be performed by the controlling circuitry 130 of Figure 1 and/or by the DSP 230 of Figure 2.

The phase detector is configured to determine a difference (e.g., a difference in time and/or phase) between a first periodic signal and a second periodic signal (compare with the first periodic signal 102, 202 and the second periodic signal 103, 203 of Figures 1 and 2). In an initial optional step 410, the method 400 may comprise determining calibration values for each of the oscillators during a calibration procedure (e.g., as exemplified in connection with Figures 1 and 2).

In step 420, the method 400 comprises selecting an oscillator among the plurality of oscillators, as illustrated by sub-step 424.

In step 430, the method 400 comprises feeding an output signal of a phase detector to the selected oscillator, as illustrated by sub-step 434 (compare with the operation of 121, 221 of Figures 1 and 2), and providing a feedback signal from the selected oscillator as the second periodic signal, as illustrated by sub-step 436 (compare with the operation of 122, 222 of Figures 1 and 2).

Optionally, the method 400 may also comprise selecting an input signal instance, as illustrated by sub-step 422 of step 420, and providing the selected input signal instance as the first periodic signal, as illustrated by sub-step 432 of step 430 (compare with the operation of 123, 223 of Figures 1 and 2).

Alternatively or additionally, the method 400 may optionally comprise applying compensation to the output of the phase detector, as illustrated by sub-step 438 of step 430 (compare with the operation of 150, 250 of Figures 1 and 2). The compensation may, for example, relate to a selected instance and/or the calibration value, as exemplified in connection with Figures 1 and 2.

Steps 420 and 430 are iterated, e.g., to select each oscillator once per time-sharing cycle. Thus, it is varied over time which of the plurality of oscillators is selected in sub-step 424, thereby providing time-sharing of the phase detector.

As already exemplified in connection to Figure 1, numerous variations are possible for the selection of oscillator and - when applicable - instance (e.g., regarding the order in which oscillators are selected and - when applicable - which instance selection is combined with which oscillator selection).

The described embodiments and their equivalents may be realized in software or hardware or a combination thereof. The embodiments may be performed by general purpose circuitry. Examples of general purpose circuitry include digital signal processors (DSP), central processing units (CPU), co-processor units, field programmable gate arrays (FPGA) and other programmable hardware. Alternatively or additionally, the embodiments may be performed by specialized circuitry, such as application specific integrated circuits (ASIC). The general purpose circuitry and/or the specialized circuitry may, for example, be used in a device such as a phase- locked loop (PLL) arrangement or a multi-antenna system controller. Alternatively or additionally, the general purpose circuitry and/or the specialized circuitry may, for example, be associated with or comprised in an apparatus such as a communication device (e.g., a radio access node or a user device).

Embodiments may appear within an electronic apparatus (such as a communication device) comprising arrangements, circuitry, and/or logic according to any of the embodiments described herein. Alternatively or additionally, an electronic apparatus (such as a communication device) may be configured to perform method steps according to any of the embodiments described herein.

Generally, all terms used herein are to be interpreted according to their ordinary meaning in the relevant technical field, unless a different meaning is clearly given and/or is implied from the context in which it is used.

Reference has been made herein to various embodiments. However, a person skilled in the art would recognize numerous variations to the described embodiments that would still fall within the scope of the claims.

For example, the method embodiments described herein discloses example methods through steps being performed in a certain order. However, it is recognized that these sequences of events may take place in another order without departing from the scope of the claims. Furthermore, some method steps may be performed in parallel even though they have been described as being performed in sequence. Thus, the steps of any methods disclosed herein do not have to be performed in the exact order disclosed, unless a step is explicitly described as following or preceding another step and/or where it is implicit that a step must follow or precede another step.

In the same manner, it should be noted that in the description of embodiments, the partition of functional blocks into particular units is by no means intended as limiting. Contrarily, these partitions are merely examples. Functional blocks described herein as one unit may be split into two or more units. Furthermore, functional blocks described herein as being implemented as two or more units may be merged into fewer (e.g. a single) unit.

Any feature of any of the embodiments disclosed herein may be applied to any other embodiment, wherever suitable. Likewise, any advantage of any of the embodiments may apply to any other embodiments, and vice versa.

Hence, it should be understood that the details of the described embodiments are merely examples brought forward for illustrative purposes, and that all variations that fall within the scope of the claims are intended to be embraced therein.