Title:
OVERLAY MARK, OVERLAY MEASUREMENT METHOD USING SAME, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2017/007072
Kind Code:
A1
Abstract:
The present invention relates to an overlay mark, an overlay measurement method using the same, and a method for manufacturing a semiconductor device. The present invention provides an overlay mark, which determines the relative stagger of two patterns formed on two successive pattern layers or separately formed on one pattern layer, the overlay mark comprising: a first overlay structure in the shape of a square; and a second overlay structure having four overlay patterns respectively placed on the upper and lower and left and right sides of the first overlay structure, each of the four overlay patterns having a plurality of bars parallel to each other. The overlay mark according to the present invention may be used as a mark for confirming whether pattern layers are accurately aligned in a semiconductor manufacturing process, and also may be used as a mark for confirming whether a plurality of patterns on one layer are accurately aligned.
Inventors:
CHANG MYUNG SHIK (KR)
LEE JUN WOO (KR)
CHANG HYUN JIN (KR)
KIM SE WOONG (KR)
LEE GHIL SOO (KR)
LEE JUN WOO (KR)
CHANG HYUN JIN (KR)
KIM SE WOONG (KR)
LEE GHIL SOO (KR)
Application Number:
PCT/KR2015/011610
Publication Date:
January 12, 2017
Filing Date:
November 02, 2015
Export Citation:
Assignee:
AUROS TECH INC (KR)
International Classes:
H01L23/544; H01L21/027; H01L21/66; H01L21/67
Foreign References:
| KR100800783B1 | 2008-02-01 | |||
| KR20100009207A | 2010-01-27 | |||
| KR20080085543A | 2008-09-24 | |||
| KR20050111821A | 2005-11-29 | |||
| KR20040045690A | 2004-06-02 |
Attorney, Agent or Firm:
DYNE PATENT & LAW FIRM (KR)
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