HIGH DATA RATE

REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of U.S. Provisional Application No.

62/316,073 filed March 31 , 2016, entitled "PDCP CONCATENATION FOR HIGH DATA RATE", the contents of which are herein incorporated by reference in their entirety.

FIELD

[0002] The present disclosure relates to wireless technology, and more specifically to techniques for improving the data rate of a packet data convergence protocol (PDCP) layer.

BACKGROUND

[0003] Cellular data rates and data rate demands on wireless networks are increasing every year. With fifth generation (5G) radio access technologies (RATs), the data rate will increase further, with expected target throughputs of 10Gbps or possibly higher. In conventional Long Term Evolution (LTE) systems, the user plane comprises the MAC (Medium Access Control), RLC (Radio Link Control), PDCP (Packet Data Convergence Protocol) layers. For PDCP as defined in conventional LTE systems, each IP (Internet Protocol) packet is processed (sequence numbering, window handling, ciphering, etc.) by itself in PDCP, and the output is PDCP PDU per IP packets.

BRIEF DESCRIPTION OF THE DRAWINGS

[0004] FIG. 1 is a block diagram illustrating an example user equipment (UE) useable in connection with various aspects described herein.

[0005] FIG. 2 is a diagram illustrating a functional view of the PDCP (Packet Data

Convergence Protocol) layer at a UE in connection with various aspects described herein.

[0006] FIG. 3 is a diagram illustrating an example PDCP header supporting concatenation in connection with various aspects described herein.

[0007] FIG. 4 is a block diagram illustrating a system that facilitates a PDCP layer supporting concatenation at a UE or at a base station, according to various aspects described herein. [0008] FIG. 5 is a flow diagram illustrating a method that facilitates generation of a PDCP PDU (Packet Data Unit) with a concatenated data field from one or more IP packets by a UE or base station according to various aspects described herein.

[0009] FIG. 6 is a flow diagram illustrating a method that facilitates reconstruction of one or more IP (Internet Protocol) packets from a PDCP PDU (Packet Data Unit) with a concatenated data field by a UE or base station according to various aspects described herein.

DETAILED DESCRIPTION

[0010] The present disclosure will now be described with reference to the attached drawing figures, wherein like reference numerals are used to refer to like elements throughout, and wherein the illustrated structures and devices are not necessarily drawn to scale. As utilized herein, terms "component," "system," "interface," and the like are intended to refer to a computer-related entity, hardware, software (e.g., in execution), and/or firmware. For example, a component can be a processor (e.g., a microprocessor, a controller, or other processing device), a process running on a processor, a controller, an object, an executable, a program, a storage device, a computer, a tablet PC and/or a user equipment (e.g., mobile phone, etc.) with a processing device. By way of illustration, an application running on a server and the server can also be a component. One or more components can reside within a process, and a component can be localized on one computer and/or distributed between two or more computers. A set of elements or a set of other components can be described herein, in which the term "set" can be interpreted as "one or more."

[0011] Further, these components can execute from various computer readable storage media having various data structures stored thereon such as with a module, for example. The components can communicate via local and/or remote processes such as in accordance with a signal having one or more data packets (e.g., data from one component interacting with another component in a local system, distributed system, and/or across a network, such as, the Internet, a local area network, a wide area network, or similar network with other systems via the signal).

[0012] As another example, a component can be an apparatus with specific functionality provided by mechanical parts operated by electric or electronic circuitry, in which the electric or electronic circuitry can be operated by a software application or a firmware application executed by one or more processors. The one or more processors can be internal or external to the apparatus and can execute at least a part of the software or firmware application. As yet another example, a component can be an apparatus that provides specific functionality through electronic components without mechanical parts; the electronic components can include one or more processors therein to execute software and/or firmware that confer(s), at least in part, the functionality of the electronic components.

[0013] Use of the word exemplary is intended to present concepts in a concrete fashion. As used in this application, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or". That is, unless specified otherwise, or clear from context, "X employs A or B" is intended to mean any of the natural inclusive permutations. That is, if X employs A; X employs B; or X employs both A and B, then "X employs A or B" is satisfied under any of the foregoing instances. In addition, the articles "a" and "an" as used in this application and the appended claims should generally be construed to mean "one or more" unless specified otherwise or clear from context to be directed to a singular form. Furthermore, to the extent that the terms "including", "includes", "having", "has", "with", or variants thereof are used in either the detailed description and the claims, such terms are intended to be inclusive in a manner similar to the term

"comprising."

[0014] As used herein, the term "circuitry" may refer to, be part of, or include an Application Specific Integrated Circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group), and/or memory (shared, dedicated, or group) that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable hardware components that provide the described functionality. In some embodiments, the circuitry may be implemented in, or functions associated with the circuitry may be implemented by, one or more software or firmware modules. In some embodiments, circuitry may include logic, at least partially operable in hardware.

[0015] Embodiments described herein may be implemented into a system using any suitably configured hardware and/or software. FIG. 1 illustrates, for one embodiment, example components of a User Equipment (UE) device 100. In some embodiments, the UE device 100 may include application circuitry 102, baseband circuitry 104, Radio Frequency (RF) circuitry 106, front-end module (FEM) circuitry 108 and one or more antennas 1 10, coupled together at least as shown.

[0016] The application circuitry 102 may include one or more application processors. For example, the application circuitry 102 may include circuitry such as, but not limited to, one or more single-core or multi-core processors. The processor(s) may include any combination of general-purpose processors and dedicated processors (e.g., graphics processors, application processors, etc.). The processors may be coupled with and/or may include memory/storage and may be configured to execute instructions stored in the memory/storage to enable various applications and/or operating systems to run on the system.

[0017] The baseband circuitry 104 may include circuitry such as, but not limited to, one or more single-core or multi-core processors. The baseband circuitry 1 04 may include one or more baseband processors and/or control logic to process baseband signals received from a receive signal path of the RF circuitry 106 and to generate baseband signals for a transmit signal path of the RF circuitry 106. Baseband processing circuity 104 may interface with the application circuitry 102 for generation and processing of the baseband signals and for controlling operations of the RF circuitry 106. For example, in some embodiments, the baseband circuitry 104 may include a second generation (2G) baseband processor 104a, third generation (3G) baseband processor 104b, fourth generation (4G) baseband processor 104c, and/or other baseband processor(s) 104d for other existing generations, generations in development or to be developed in the future (e.g., fifth generation (5G), 6G, etc.). The baseband circuitry 104 (e.g., one or more of baseband processors 104a-d) may handle various radio control functions that enable communication with one or more radio networks via the RF circuitry 106. The radio control functions may include, but are not limited to, signal modulation/demodulation, encoding/decoding, radio frequency shifting, etc. In some embodiments, modulation/demodulation circuitry of the baseband circuitry 104 may include Fast-Fourier Transform (FFT), precoding, and/or constellation

mapping/demapping functionality. In some embodiments, encoding/decoding circuitry of the baseband circuitry 104 may include convolution, tail-biting convolution, turbo, Viterbi, and/or Low Density Parity Check (LDPC) encoder/decoder functionality.

Embodiments of modulation/demodulation and encoder/decoder functionality are not limited to these examples and may include other suitable functionality in other embodiments.

[0018] In some embodiments, the baseband circuitry 104 may include elements of a protocol stack such as, for example, elements of an evolved universal terrestrial radio access network (EUTRAN) protocol including, for example, physical (PHY), media access control (MAC), radio link control (RLC), packet data convergence protocol (PDCP), and/or radio resource control (RRC) elements. A central processing unit (CPU) 104e of the baseband circuitry 104 may be configured to run elements of the protocol stack for signaling of the PHY, MAC, RLC, PDCP and/or RRC layers. In some embodiments, the baseband circuitry may include one or more audio digital signal processor(s) (DSP) 104f. The audio DSP(s) 104f may be include elements for compression/decompression and echo cancellation and may include other suitable processing elements in other embodiments. Components of the baseband circuitry may be suitably combined in a single chip, a single chipset, or disposed on a same circuit board in some embodiments. In some embodiments, some or all of the constituent components of the baseband circuitry 104 and the application circuitry 102 may be implemented together such as, for example, on a system on a chip (SOC).

[0019] In some embodiments, the baseband circuitry 104 may provide for communication compatible with one or more radio technologies. For example, in some embodiments, the baseband circuitry 104 may support communication with an evolved universal terrestrial radio access network (EUTRAN) and/or other wireless metropolitan area networks (WMAN), a wireless local area network (WLAN), a wireless personal area network (WPAN). Embodiments in which the baseband circuitry 104 is configured to support radio communications of more than one wireless protocol may be referred to as multi-mode baseband circuitry.

[0020] RF circuitry 106 may enable communication with wireless networks using modulated electromagnetic radiation through a non-solid medium. In various embodiments, the RF circuitry 106 may include switches, filters, amplifiers, etc. to facilitate the communication with the wireless network. RF circuitry 106 may include a receive signal path which may include circuitry to down-convert RF signals received from the FEM circuitry 108 and provide baseband signals to the baseband circuitry 104. RF circuitry 106 may also include a transmit signal path which may include circuitry to up-convert baseband signals provided by the baseband circuitry 1 04 and provide RF output signals to the FEM circuitry 108 for transmission.

[0021] In some embodiments, the RF circuitry 106 may include a receive signal path and a transmit signal path. The receive signal path of the RF circuitry 106 may include mixer circuitry 1 06a, amplifier circuitry 106b and filter circuitry 106c. The transmit signal path of the RF circuitry 106 may include filter circuitry 106c and mixer circuitry 106a. RF circuitry 106 may also include synthesizer circuitry 106d for synthesizing a frequency for use by the mixer circuitry 106a of the receive signal path and the transmit signal path. In some embodiments, the mixer circuitry 106a of the receive signal path may be configured to down-convert RF signals received from the FEM circuitry 108 based on the synthesized frequency provided by synthesizer circuitry 106d. The amplifier circuitry 106b may be configured to amplify the down-converted signals and the filter circuitry 106c may be a low-pass filter (LPF) or band-pass filter (BPF) configured to remove unwanted signals from the down-converted signals to generate output baseband signals. Output baseband signals may be provided to the baseband circuitry 104 for further processing. In some embodiments, the output baseband signals may be zero- frequency baseband signals, although this is not a requirement. In some embodiments, mixer circuitry 1 06a of the receive signal path may comprise passive mixers, although the scope of the embodiments is not limited in this respect.

[0022] In some embodiments, the mixer circuitry 106a of the transmit signal path may be configured to up-convert input baseband signals based on the synthesized frequency provided by the synthesizer circuitry 106d to generate RF output signals for the FEM circuitry 108. The baseband signals may be provided by the baseband circuitry 104 and may be filtered by filter circuitry 1 06c. The filter circuitry 1 06c may include a low-pass filter (LPF), although the scope of the embodiments is not limited in this respect.

[0023] In some embodiments, the mixer circuitry 106a of the receive signal path and the mixer circuitry 106a of the transmit signal path may include two or more mixers and may be arranged for quadrature downconversion and/or upconversion respectively. In some embodiments, the mixer circuitry 106a of the receive signal path and the mixer circuitry 106a of the transmit signal path may include two or more mixers and may be arranged for image rejection (e.g., Hartley image rejection). In some embodiments, the mixer circuitry 1 06a of the receive signal path and the mixer circuitry 106a may be arranged for direct downconversion and/or direct upconversion, respectively. In some embodiments, the mixer circuitry 106a of the receive signal path and the mixer circuitry 106a of the transmit signal path may be configured for super-heterodyne operation.

[0024] In some embodiments, the output baseband signals and the input baseband signals may be analog baseband signals, although the scope of the embodiments is not limited in this respect. In some alternate embodiments, the output baseband signals and the input baseband signals may be digital baseband signals. In these alternate embodiments, the RF circuitry 106 may include analog-to-digital converter (ADC) and digital-to-analog converter (DAC) circuitry and the baseband circuitry 104 may include a digital baseband interface to communicate with the RF circuitry 106.

[0025] In some dual-mode embodiments, a separate radio IC circuitry may be provided for processing signals for each spectrum, although the scope of the

embodiments is not limited in this respect.

[0026] In some embodiments, the synthesizer circuitry 106d may be a fractional-N synthesizer or a fractional N/N+1 synthesizer, although the scope of the embodiments is not limited in this respect as other types of frequency synthesizers may be suitable. For example, synthesizer circuitry 106d may be a delta-sigma synthesizer, a frequency multiplier, or a synthesizer comprising a phase-locked loop with a frequency divider.

[0027] The synthesizer circuitry 106d may be configured to synthesize an output frequency for use by the mixer circuitry 106a of the RF circuitry 1 06 based on a frequency input and a divider control input. In some embodiments, the synthesizer circuitry 106d may be a fractional N/N+1 synthesizer.

[0028] In some embodiments, frequency input may be provided by a voltage controlled oscillator (VCO), although that is not a requirement. Divider control input may be provided by either the baseband circuitry 104 or the applications processor 1 02 depending on the desired output frequency. In some embodiments, a divider control input (e.g., N) may be determined from a look-up table based on a channel indicated by the applications processor 1 02.

[0029] Synthesizer circuitry 1 06d of the RF circuitry 106 may include a divider, a delay-locked loop (DLL), a multiplexer and a phase accumulator. In some embodiments, the divider may be a dual modulus divider (DMD) and the phase accumulator may be a digital phase accumulator (DPA). In some embodiments, the DMD may be configured to divide the input signal by either N or N+1 (e.g., based on a carry out) to provide a fractional division ratio. In some example embodiments, the DLL may include a set of cascaded, tunable, delay elements, a phase detector, a charge pump and a D-type flip- flop. In these embodiments, the delay elements may be configured to break a VCO period up into Nd equal packets of phase, where Nd is the number of delay elements in the delay line. In this way, the DLL provides negative feedback to help ensure that the total delay through the delay line is one VCO cycle.

[0030] In some embodiments, synthesizer circuitry 1 06d may be configured to generate a carrier frequency as the output frequency, while in other embodiments, the output frequency may be a multiple of the carrier frequency (e.g., twice the carrier frequency, four times the carrier frequency) and used in conjunction with quadrature generator and divider circuitry to generate multiple signals at the carrier frequency with multiple different phases with respect to each other. In some embodiments, the output frequency may be a LO frequency (fLO). In some embodiments, the RF circuitry 106 may include an IQ/polar converter.

[0031] FEM circuitry 108 may include a receive signal path which may include circuitry configured to operate on RF signals received from one or more antennas 1 10, amplify the received signals and provide the amplified versions of the received signals to the RF circuitry 106 for further processing. FEM circuitry 108 may also include a transmit signal path which may include circuitry configured to amplify signals for transmission provided by the RF circuitry 106 for transmission by one or more of the one or more antennas 1 1 0.

[0032] In some embodiments, the FEM circuitry 108 may include a TX/RX switch to switch between transmit mode and receive mode operation. The FEM circuitry may include a receive signal path and a transmit signal path. The receive signal path of the FEM circuitry may include a low-noise amplifier (LNA) to amplify received RF signals and provide the amplified received RF signals as an output (e.g., to the RF circuitry 106). The transmit signal path of the FEM circuitry 108 may include a power amplifier (PA) to amplify input RF signals (e.g., provided by RF circuitry 106), and one or more filters to generate RF signals for subsequent transmission (e.g., by one or more of the one or more antennas 1 1 0.

[0033] In some embodiments, the UE device 100 may include additional elements such as, for example, memory/storage, display, camera, sensor, and/or input/output (I/O) interface.

[0034] Additionally, although the above example discussion of device 100 is in the context of a UE device, in various aspects, a similar device can be employed in connection with a base station (BS) such as an Evolved NodeB (eNB), etc.

[0035] Future developments in RATs (Radio Access Technologies) such as LTE and 5G will provide increased data rates. These increased data rates are relevant to multiple different RAT features, such as an increased number of component carriers for carrier aggregation (e.g., up to 32 carriers), LAA (License Assisted Access), Dual connectivity and LWA (LTE WLAN (Wireless Local Access Network) Aggregation) features. Each of the listed features employ PDCP as part of the LTE user plane, and 5G RATs that employ the same or a similar user plane architecture will also employ PDCP as part of the user plane.

[0036] The increasing demands for higher data rate generate an increasing numbers of packets (e.g., IP packets) to be processed by the UE. Since UE processing power is often proportional not to the throughput, but to the number of packets/headers, the concept of processing packet by packet increases the CPU load and uses more CPU computing power at both the eNB (Evolved NodeB) and UE. Since the UE is limited in its CPU capabilities and limited in power/battery, processing a larger number of packets/headers can become an acute problem on the UE side.

[0037] Various aspects discussed herein facilitate a PDCP layer that supports concatenation of data fields of one or more IP packets. By concatenating IP fields of data packets in the PDCP layer, a higher data rate can be provided, with reduced power consumption. Techniques discussed herein can facilitate a PDCP layer allowing concatenation of multiple SDUs (Service Data Units, e.g., IP packets) into a single PDCP PDU (Packet Data Unit). In various aspects described herein, the maximum concatenated PDU size can be changed dynamically or can be fixed (e.g., predefined) size. In the former case, the maximum size of the concatenated PDU can be

determined by the transmitting device (e.g., eNB (evolved NodeB) or UE). Alternatively, the maximum size can be configured by the eNB for the UE (e.g., in the uplink), or can be negotiated between the eNB and the UE (e.g., based on a UE capability exchange or other method).

[0038] PDCP concatenation techniques discussed herein can allow both the UE and the eNB to perform PDCP processing more efficiently, reducing CPU processing load and releasing bottlenecks in the data path. At the UE in particular, the reduced processing load can reduce power consumption, leading to longer battery life.

[0039] Although the LTE PDCP layer is discussed as an example embodiment herein, the proposed method is also applicable to a 5G protocol stack. For a 5G protocol stack having a PDCP layer with similar functionality to this of LTE, the techniques discussed in connection with a LTE PDCP layer can be applied to the 5G PDCP layer. For a 5G protocol stack design differing from the LTE protocol stack, the techniques discussed herein can be applied to a layer of the 5G protocol stack having similar functionality to that of the PDCP layer of the LTE protocol stack.

[0040] In various aspects, embodiments described herein can employ a PDCP layer differing from a conventional PDCP layer in multiple aspects. [0041] First, a PDCP concatenation function can be employed (e.g., by UEs on the UL (uplink) path and/or by eNBs on the DL (downlink) path) that can facilitate

concatenation of one or more PDCP SDUs (e.g., IP packets) into a single PDCP PDU. In some aspects, the concatenated PDU size can be varied and decided dynamically, for example, based on the UL grant for a UE, or the size can be predefined to be a fixed size.

[0042] Second, a reassembly function can be employed (e.g., by UEs on the DL path and/or by eNBs on the UL path) that can facilitate reassembly of a PDCP PDU into one or more PDCP SDUs (e.g., IP packets), and can facilitate delivery of the one or more PDCP SDUs in order.

[0043] Third, a new PDCP header format can be employed, which can provide support for concatenation operations. In one example embodiment, a maximum IP packet size of 2048 bytes can be employed, and an 18 bit PDCP SN (sequence number) can be employed.

[0044] Referring to FIG. 2, illustrated is a diagram of a functional view of the PDCP (Packet Data Convergence Protocol) layer at a UE in connection with various aspects described herein, showing both the UE DL process (reassembling one or more PDCP SDUs from a PDCP PDU, corresponding to the eNB UL process), and the UE UL process (concatenating one or more PDCP SDUs (e.g., IP packets) into a single PDCP PDU, corresponding to the eNB DL process).

[0045] Referring to FIG. 3, illustrated is a diagram showing an example PDCP header that supports concatenation in connection with various aspects described herein. In the example header of FIG. 3 or in other PDCP headers supporting concatenation, one or more of the following parameters can be included: (a) a field (e.g., "D/C") that indicates whether the PDCP PDU is a data PDU or a control PDU, which can have a length of 1 bit (e.g., with 0 = data PDU and 1 = control PDU, or vice versa); (b) a reserved field ("R"), which can have a length of 1 or more bits (e.g., the 4 consecutive 1 bit R fields in the example PDCP header of FIG. 3); (c) a PDCP SN, which can have a length longer than conventional PDCP SNs (e.g., greater than 12 bits, such as the 18 bits of the example PDCP header of FIG. 3, etc.); (d) n (e.g., one or more) extension or continuation fields ("E") that indicate whether an associated data field element (e.g., from an IP packet) is a final data field element of the concatenation (e.g., of the PDU data field) or whether the header and PDU data field are extended as a result of additional concatenation, which can have a length of 1 bit; and (e) n length indication fields ("LI") that indicate a length of an associated data field element of the concatenation, which can have a length associated with a maximum size of an IP packet that can be concatenated (e.g., 1 1 bits provides for a size of up to 2048 bytes, although larger or smaller sizes can be employed, etc.).

[0046] The E field can indicate whether the PDCP data field follows or a set of E field and LI field follows. In the example header of FIG. 3, the interpretation of the E field can be provided by Table 1 and Table 2 below:

Table 1 - E field interpretation (for E field in the fixed part of the header)

[0047] The LI field can indicate the length in bytes of the corresponding data field element present in the PDCP data PDU delivered to or received from the next lowest layer (RLC in conventional LTE, MAC in embodiments described herein that merge the PDCP and RLC layers, a layer with corresponding functions in 5G, etc.). The n LI fields can correspond, in order, to the n data field elements concatenated in the PDU data field (e.g., the first LI present in the PDCP data PDU header can correspond to the first data field element present in the data field of the PDCP data PDU, the second LI present in the PDCP data PDU header can correspond to the second data field element present in the data field of the PDU (e.g., depending on the embodiment, PDCP PDU, RLC PDU, PDU of a 5G layer with similar functions to the PDCP layer, etc.), etc., through the nth LI of the PDCP data PDU header, which can correspond to the nth data field element present in the data field of the PDU. The value 0 can be reserved.

[0048] Referring to FIG. 4, illustrated is a block diagram of a system 400 that facilitates a PDCP layer supporting concatenation at a UE or at a base station, according to various aspects described herein. System 400 can include one or more processors 41 0 (e.g., one or more baseband processors such as one or more of the baseband processors discussed in connection with FIG. 1 ), transceiver circuitry 420 (e.g., comprising one or more of transmitter circuitry or receiver circuitry, which can employ common circuit elements, distinct circuit elements, or a combination thereof), and a memory 430 (which can comprise any of a variety of storage mediums and can store instructions and/or data associated with one or more of processor(s) 410 or transceiver circuitry 420). As described in greater detail below, system 400 can facilitate generating PDCP PDUs that concatenate one or more PDCP SDUs (e.g., IP packets), or reassembly and in-order delivery of one or more PDCP SDUs from a single PDCP PDU with a concatenated data field.

[0049] In some aspects, system 400 can be included within a user equipment (UE). In other aspects, system 400 can be included within an Evolved Universal Terrestrial Radio Access Network (E-UTRAN) Node B (Evolved Node B, eNodeB, or eNB) or other base station in a wireless communications network. In some base station aspects, the processor(s) 410, transceiver circuitry 420, and the memory 430 can be included in a single device, while in other such aspects, they can be included in different devices, such as part of a distributed architecture.

[0050] Processor 410 can provide the functionality of a PDCP layer employing concatenation in connection with a user plane of a wireless communication network. In a first scenario, in connection with a downlink (DL) at an eNB or with an uplink (UL) at a UE, processor 410 can generate a PDU (e.g., PDCP PDU, RLC PDU, PDU of a 5G layer with functionality similar to the PDCP layer of LTE, etc.) that comprises a data field that is a concatenation of one or more PDCP SDUs (e.g., IP packets). In a second scenario, in connection with an UL at an eNB or with a DL at a UE, processor 410 can reassemble one or more PDCP SDUs (e.g., IP packets) from a single PDCP PDU and can deliver the one or more PDCP SDUs in order.

[0051] In the first scenario, processor 41 0 can determine a set of PDCP SDUs such as IP packets (each of which can comprise an IP packet header and an IP packet data field) to be provided via a PDU to be generated by processor 410. The set of IP packets can be a next n IP packets to be provided, where processor 410 can select the value of n based on the size of the next n IP packets and a maximum size of the PDU (e.g., which can be statically determined, or configured dynamically, such as based on the UL grant in an associated downlink control information (DCI) message, based on UE capabilities for embodiments of system 400 employed at a UE, etc.). Processor 410 can construct a PDCP header Processor 410 can concatenate the n IP packets (e.g., in order) to generate a PDCP data field comprising n data field elements, each of which corresponds to one of the n IP packets. Processor 410 can generate a PDCP sequence number (SN) for the PDU (e.g., having more than 1 2 bits, for example, 18 bits), and can apply ciphering to the PDCP data field.

[0052] Based on the n IP packets (e.g., the sizes of each of the n IP packets and the number of IP packets, n, etc.), processor 410 can generate a PDCP header that indicates the PDCP SN, the value of n (the number of concatenated data field elements in the PDU data field), and a size of each of the n IP packets. For example, the PDCP header can comprise n pairs of indicators, each of which can be associated with a distinct data field element (e.g., IP packet) of the concatenation. Each pair of indicators can comprise an extension field (e.g., the example "E" field discussed in connection with FIG. 3, or another continuation or extension field that can indicate whether that pair of indicators is a final pair of indicators or followed by one or more pairs of indicators) and a length indicator field (e.g., the example "LI" field discussed in connection with FIG. 3, or another field that can indicate a size of the associated IP data field element (e.g., in bytes, etc.)). In various aspects, the n pairs of indicators and the n concatenated IP packets can both be ordered based on the original ordering of the n IP packets, which can facilitate subsequent in-order delivery of the n IP packets. Processor 410 can attach the generated PDCP header to the PDU data field to generate the PDU.

[0053] In connection with the second scenario (reassembly of one or more PDCP SDUs from a single PDU), processor 410 can separate a PDCP header from a PDCP data field by removing the PDCP header. Processor 410 can decipher the PDCP data field to generate a deciphered PDCP data field that is a concatenation of n (e.g., 1 or more) data field elements, each of which can be an IP packet. Processor 410 can analyze the PDCP header to determine the number (n) of concatenated data field elements, the size(s) of the n concatenated data field elements, and the order of the n concatenated data field elements. For example, in addition to a PDCP SN, the PDCP header can comprise a pair of parameters or indicators associated with each of the n concatenated data field elements (e.g., IP packets), wherein one of the indicators (e.g., "E" in connection with FIG. 3, etc.) can indicate if one or more additional data field elements follow the associated data field element, and another of the indicators (e.g., "LI" in connection with FIG. 3, etc.) can indicate a size of the associated data field element. The n pairs of indicators can have a common ordering with the n concatenated data field elements, which can correspond to an ordering of the n IP packets

concatenated in the PDCP PDU data field.

[0054] Based on the determined number (n) of data field elements, sizes of the n data field elements, and ordering of the n data field elements, processor 410 can deliver the n PDCP SDUs (e.g., IP packets) that form the concatenated PDCP PDU data field (e.g., IP data fields) to an IP layer. Processor 410 can deliver the n PDCP PDUs in order to the IP layer, as the ordering of the IP packets can be determined from the order of the concatenation and/or the order of the associated indicators.

[0055] In various aspects, Transceiver circuitry 420 can receive and/or transmit data and/or control messages over an air interface (e.g., LTE, 5G, etc.) that comprise PDCP PDUs employing concatenation techniques described herein.

[0056] In aspects, a UE and/or an eNB employing system 400 can communicate via one or more wireless links that comprise radio bearers (e.g., signal radio bearers, data radio bearers, etc.) employing PDCP concatenation as described herein. Additionally, in some aspects, an eNB employing system 400 can configure (or a UE employing system 400 can be configured by an eNB) with one or more radio bearers employing

concatenated PDCP as described herein. A UE and/or an eNB comprising system 400 can employ PDCP concatenation as described herein can, in various aspects, generate PDCP PDUs that correspond to a maximum concatenated size for the PDU data field (or as close as possible given the sizes of IP packets to be communicated), which can minimize the number of PDUs involved and thus the associated processing load.

Additionally, as described herein, a UE and/or an eNB comprising system 400 can reassemble received concatenated PDCP PDUs to deliver, in order, the corresponding IP packets to the IP layer.

[0057] Referring to FIG. 5, illustrated is a flow diagram of a method 500 that facilitates generation of a PDCP PDU (Packet Data Unit) with a concatenated data field comprising one or more IP packets by a UE or base station according to various aspects described herein. In some aspects, method 500 can be performed at a UE or an eNB. In other aspects, a machine readable medium can store instructions associated with method 500 that, when executed, can cause a UE or an eNB to perform the acts of method 500.

[0058] At 510, a PDCP header can be constructed, based at least in part on a set of n PDCP SDUs (e.g., IP packets). [0059] At 520, a PDCP PDU data field can be generated by concatenating the

SDUs, and extending the PDCP header to include parameters indicating the lengths, number, and ordering of each of the n concatenated PDCP SDUs.

[0060] At 530, a sequence number (SN) can be determined that is associated with the PDCP PDU data field that comprises the concatenated n PDCP SDUs (e.g., IP packets).

[0061] At 540, the PDCP PDU data field can be ciphered.

[0062] At 550, the PDCP header can be attached to the ciphered PDCP data field to generate a PDCP PDU, wherein the PDCP header can be a PDCP header that supports concatenation, such as the headers discussed herein.

[0063] Referring to FIG. 6, illustrated is a flow diagram of a method 600 that facilitates reconstruction of one or more PDCP SDUs (e.g., IP packets) from a PDCP PDU (Packet Data Unit) with a concatenated data field by a UE or base station according to various aspects described herein. In some aspects, method 600 can be performed at a UE or an eNB. In other aspects, a machine readable medium can store instructions associated with method 600 that, when executed, can cause a UE or an eNB to perform the acts of method 600.

[0064] At 610, a PDCP header can be separated from a PDCP data field of a PDU (e.g., PDCP PDU, RLC PDU, PDU of a 5G layer corresponding to the PDCP layer, etc.).

[0065] At 620, the PDCP data field can be deciphered to obtain a deciphered PDCP data field comprising n concatenated IP packets.

[0066] At 630, the PDCP header can be analyzed to identify characteristics of the n concatenated IP packets (e.g., to identify the value of n, the lengths of the n IP packets, the order of the n IP pacekts).

[0067] At 640, an ordered set of n IP packets can be reconstructed from the n concatenated IP packets.

[0068] Examples herein can include subject matter such as a method, means for performing acts or blocks of the method, at least one machine-readable medium including executable instructions that, when performed by a machine (e.g., a processor with memory, an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), or the like) cause the machine to perform acts of the method or of an apparatus or system for concurrent communication using multiple communication technologies according to embodiments and examples described. [0069] Example 1 is an apparatus configured to be employed within a User

Equipment (UE), comprising one or more processors configured to: generate a packet data convergence protocol (PDCP) data field comprising a concatenation of each IP packet of a set of IP packets, wherein the set of IP packets comprises n IP packets; determine a PDCP sequence number (SN) associated with the PDCP data field; apply ciphering to the PDCP data field; and attach a PDCP header to the PDCP data field to generate a packet data unit (PDU), wherein the PDCP header indicates the PDCP SN, the value of n, and a size of each IP packet of the set of IP packets.

[0070] Example 2 comprises the subject matter of any variation of example 1 , wherein the PDCP header comprises n pairs of indicators, wherein each pair of indicators is associated with a distinct IP packet of the concatenation of the IP packets.

[0071] Example 3 comprises the subject matter of any variation of example 2, wherein each pair of indicators comprises a continuation indicator that indicates whether the associated distinct IP packet is a final IP packet of the concatenation.

[0072] Example 4 comprises the subject matter of any variation of example 2, wherein each pair of indicators comprises a length indicator that indicates the size of the associated distinct IP packet in bytes.

[0073] Example 5 comprises the subject matter of any variation of any of examples 1 -4, wherein the PDU is a PDCP PDU.

[0074] Example 6 comprises the subject matter of any variation of any of examples 1 -4, wherein the PDU is a radio link control (RLC) PDU.

[0075] Example 7 comprises the subject matter of any variation of any of examples

1 -4, wherein the PDCP data field has a maximum size that is static.

[0076] Example 8 comprises the subject matter of any variation of any of examples

1 - 4, wherein the PDCP data field has a maximum size that is configured dynamically.

[0077] Example 9 comprises the subject matter of any variation of example 8, wherein the maximum size is indicated via one or more downlink (DL) control information (DCI) messages.

[0078] Example 10 comprises the subject matter of any variation of example 8, wherein the maximum size is based at least in part on one or more capabilities of the UE.

[0079] Example 1 1 comprises the subject matter of any variation of any of examples

2- 3, wherein each pair of indicators comprises a length indicator that indicates the size of the associated distinct IP packet in bytes. [0080] Example 12 comprises the subject matter of any variation of any of examples 1 -3 or 1 1 , wherein the PDU is a PDCP PDU.

[0081] Example 13 comprises the subject matter of any variation of any of examples 1 -3 or 1 1 , wherein the PDU is a radio link control (RLC) PDU.

[0082] Example 14 comprises the subject matter of any variation of any of examples 1 -3 or 1 1 -13, wherein the PDCP data field has a maximum size that is static.

[0083] Example 15 comprises the subject matter of any variation of any of examples 1 -3 or 1 1 -13, wherein the PDCP data field has a maximum size that is configured dynamically.

[0084] Example 16 comprises the subject matter of any variation of example 15, wherein the maximum size is indicated via one or more downlink (DL) control information (DCI) messages.

[0085] Example 17 comprises the subject matter of any variation of any of examples 15-1 6, wherein the maximum size is based at least in part on one or more capabilities of the UE.

[0086] Example 18 comprises the subject matter of any variation of example 1 , wherein the PDU is a PDCP PDU.

[0087] Example 19 comprises the subject matter of any variation of example 1 , wherein the PDU is a radio link control (RLC) PDU.

[0088] Example 20 comprises the subject matter of any variation of example 1 , wherein the PDCP data field has a maximum size that is static.

[0089] Example 21 comprises the subject matter of any variation of example 1 , wherein the PDCP data field has a maximum size that is configured dynamically.

[0090] Example 22 is a machine readable medium comprising instructions that, when executed, cause a User Equipment (UE) to: separate a packet data convergence protocol (PDCP) header from a PDCP data field of a PDCP packet data unit (PDU); perform deciphering on the PDCP data field, wherein the PDCP data field comprises n concatenated PDCP service data units (SDUs); analyze the PDCP header to determine the value of n and a length of each of the n concatenated PDCP SDUs; and construct n distinct PDCP SDUs based at least in part on the n concatenated PDCP SDUs and the length of each of the n concatenated PDCP SDUs.

[0091] Example 23 comprises the subject matter of any variation of example 22, wherein the PDCP header comprises a PDCP sequence number (SN) and n pairs of indicators, wherein each pair of indicators is associated with a distinct PDCP SDU of the n concatenated PDCP SDUs.

[0092] Example 24 comprises the subject matter of any variation of example 23, wherein each pair of indicators comprises a continuation indicator that indicates whether the associated distinct PDCP SDU is a final PDCP SDU of the concatenation.

[0093] Example 25 comprises the subject matter of any variation of example 24, wherein each continuation indicator comprises a single bit.

[0094] Example 26 comprises the subject matter of any variation of any of examples 23-25, wherein each pair of indicators comprises a length indicator that indicates the size of the associated distinct PDCP SDU in bytes.

[0095] Example 27 comprises the subject matter of any variation of example 26, wherein each length indicator comprises 1 1 bits.

[0096] Example 28 comprises the subject matter of any variation of example 23, wherein each pair of indicators comprises a length indicator that indicates the size of the associated distinct PDCP SDU in bytes.

[0097] Example 29 is an apparatus configured to be employed within an Evolved NodeB (eNB), comprising one or more processors configured to: remove a packet data convergence protocol (PDCP) header from a PDCP data field of a PDCP packet data unit (PDU); decipher the PDCP data field to generate a deciphered PDCP data field comprising a concatenation of n Internet Protocol (IP) packets; determine, based on the PDCP header, the value of n and an ordering associated with the n IP packets; and construct an ordered set of the n IP packets based at least in part on the concatenation of the n IP packets and the ordering.

[0098] Example 30 comprises the subject matter of any variation of example 29, wherein the concatenation of the n IP packets is ordered based on the ordering.

[0099] Example 31 comprises the subject matter of any variation of example 29, wherein the PDCP header comprises n sets of indicators that are ordered based on the ordering, wherein each of the n sets of indicators is associated with a distinct IP packet of the n IP packets.

[00100] Example 32 comprises the subject matter of any variation of example 31 , wherein each set of indicators of the n sets of indicators comprises a continuation bit that indicates if the distinct IP packet associated with that set of indicators is followed by at least one distinct IP packet. [00101 ] Example 33 comprises the subject matter of any variation of example 31 , wherein each set of indicators of the n sets of indicators comprises a length indicator that indicates a length of the distinct IP packet associated with that set of indicators.

[00102] Example 34 comprises the subject matter of any variation of any of examples 29-33, wherein the PDCP header comprises a PDCP sequence number (SN).

[00103] Example 35 comprises the subject matter of any variation of example 34, wherein the PDCP SN comprises 18 bits.

[00104] Example 36 comprises the subject matter of any variation of example 29, wherein the PDCP header comprises a PDCP sequence number (SN).

[00105] Example 37 is a machine readable medium comprising instructions that, when executed, cause an Evolved NodeB (eNB) to: concatenate each PDCP SDU of the plurality of PDCP SDUs to generate a PDCP data field; determine a PDCP sequence number (SN) associated with the PDCP data field; cipher the PDCP data field to generate a ciphered PDCP data field; and append the ciphered PDCP data field to a PDCP header to generate a packet data unit (PDU), wherein the PDCP header indicates the PDCP SN.

[00106] Example 38 comprises the subject matter of any variation of example 37, wherein the PDCP header indicates an ordering of the PDCP SDUs concatenated to generate the PDCP data field.

[00107] Example 39 comprises the subject matter of any variation of example 37, wherein the PDCP header indicates a number of PDCP SDUs concatenated to generate the PDCP data field.

[00108] Example 40 comprises the subject matter of any variation of example 37, wherein the PDCP header indicates a length of each of the PDCP SDUs concatenated to generate the PDCP data field.

[00109] Example 41 comprises the subject matter of any variation of any of examples 37-40, wherein the PDCP SN comprises more than 1 2 bits.

[00110] Example 42 comprises the subject matter of any variation of example 41 , wherein the PDCP SN comprises 18 bits.

[00111 ] Example 43 comprises the subject matter of any variation of example 37, wherein the PDCP SN comprises more than 1 2 bits.

[00112] Example 44 is an apparatus configured to be employed within a User Equipment (UE), comprising one or more means for processing configured to: separate a packet data convergence protocol (PDCP) header from a PDCP data field of a PDCP packet data unit (PDU); perform deciphering on the PDCP data field, wherein the PDCP data field comprises n concatenated PDCP service data units (SDUs); analyze the PDCP header to determine the value of n and a length of each of the n concatenated PDCP SDUs; and construct n distinct PDCP SDUs based at least in part on the n concatenated PDCP SDUs and the length of each of the n concatenated PDCP SDUs.

[00113] Example 45 comprises the subject matter of any variation of example 44, wherein the PDCP header comprises a PDCP sequence number (SN) and n pairs of indicators, wherein each pair of indicators is associated with a distinct PDCP SDU of the n concatenated PDCP SDUs.

[00114] Example 46 comprises the subject matter of any variation of example 45, wherein each pair of indicators comprises a continuation indicator that indicates whether the associated distinct PDCP SDU is a final PDCP SDU of the concatenation.

[00115] Example 47 comprises the subject matter of any variation of example 46, wherein each continuation indicator comprises a single bit.

[00116] Example 48 comprises the subject matter of any variation of any of examples 45-47, wherein each pair of indicators comprises a length indicator that indicates the size of the associated distinct PDCP SDU in bytes.

[00117] Example 49 comprises the subject matter of any variation of example 48, wherein each length indicator comprises 1 1 bits.

[00118] Example 50 is an apparatus configured to be employed within an Evolved NodeB (eNB), comprising one or more means for processing configured to: concatenate each PDCP SDU of the plurality of PDCP SDUs to generate a PDCP data field;

determine a PDCP sequence number (SN) associated with the PDCP data field; cipher the PDCP data field to generate a ciphered PDCP data field; and append the ciphered PDCP data field to a PDCP header to generate a packet data unit (PDU), wherein the PDCP header indicates the PDCP SN.

[00119] Example 51 comprises the subject matter of any variation of example 50, wherein the PDCP header indicates an ordering of the PDCP SDUs concatenated to generate the PDCP data field.

[00120] Example 52 comprises the subject matter of any variation of example 50, wherein the PDCP header indicates a number of PDCP SDUs concatenated to generate the PDCP data field. [00121 ] Example 53 comprises the subject matter of any variation of example 50, wherein the PDCP header indicates a length of each of the PDCP SDUs concatenated to generate the PDCP data field.

[00122] Example 54 comprises the subject matter of any variation of any of examples 50-53, wherein the PDCP SN comprises more than 1 2 bits.

[00123] Example 55 comprises the subject matter of any variation of example 54, wherein the PDCP SN comprises 18 bits.

[00124] The above description of illustrated embodiments of the subject disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosed embodiments to the precise forms disclosed. While specific embodiments and examples are described herein for illustrative purposes, various modifications are possible that are considered within the scope of such embodiments and examples, as those skilled in the relevant art can recognize.

[00125] In this regard, while the disclosed subject matter has been described in connection with various embodiments and corresponding Figures, where applicable, it is to be understood that other similar embodiments can be used or modifications and additions can be made to the described embodiments for performing the same, similar, alternative, or substitute function of the disclosed subject matter without deviating therefrom. Therefore, the disclosed subject matter should not be limited to any single embodiment described herein, but rather should be construed in breadth and scope in accordance with the appended claims below.

[00126] In particular regard to the various functions performed by the above described components or structures (assemblies, devices, circuits, systems, etc.), the terms (including a reference to a "means") used to describe such components are intended to correspond, unless otherwise indicated, to any component or structure which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations. In addition, while a particular feature may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application.