Title:
PACKET PROCESSING DEVICE, AND PACKET PROCESSING METHOD
Document Type and Number:
WIPO Patent Application WO/2020/217968
Kind Code:
A1
Abstract:
The objective of the present invention is to reduce the scale of hardware required for processing to restore a data block to an original plurality of items of data, and to achieve high reception performance. This packet processing device is provided with: a packet processing unit 114 which performs processing of a packet received from a communication line, and outputs processing result data; a data joining unit 120 which concatenates a plurality of items of data output from the packet processing unit 114 to generate a data block; and a joined data transferring unit 121 which performs direct memory access (DMA) transfer of the data block generated by the data joining unit 120 to data memory 115. The joined data transferring unit 121 writes information relating to the address, in the data memory 115, of the beginning of each item of data in the data block to a descriptor 1210, which is a predetermined data area in the memory.
Inventors:
KAWAMURA TOMOAKI (JP)
OTERU SHOKO (JP)
UKON YUTA (JP)
YOSHIDA SHUHEI (JP)
OTERU SHOKO (JP)
UKON YUTA (JP)
YOSHIDA SHUHEI (JP)
Application Number:
PCT/JP2020/015639
Publication Date:
October 29, 2020
Filing Date:
April 07, 2020
Export Citation:
Assignee:
NIPPON TELEGRAPH & TELEPHONE (JP)
International Classes:
H04L47/43; G06F13/28
Foreign References:
| JP2006302246A | 2006-11-02 | |||
| JP2010004262A | 2010-01-07 |
Other References:
OHTERU, SHOKO: "Improvement on DMA Transfer Efficiency by Packet Concatenation", IEICE TECHNICAL REPORT, vol. 118, no. 457, 20 February 2019 (2019-02-20), pages 79 - 84, XP009524559
Attorney, Agent or Firm:
YAMAKAWA, Shigeki et al. (JP)
Download PDF: