Title:
A PARALLEL COUNTER AND A LOGIC CIRCUIT FOR PERFORMING MULTIPLICATION
Document Type and Number:
WIPO Patent Application WO2002012995
Kind Code:
A3
Abstract:
A logic circuit such as a parallel counter comprises logic for generating output bits as elementary symmetric functions of the input bits. The parallel counter can be used in a multiplication circuit. A multiplication circuit is also provided in which an array of combinations of each bit of a binary number with each other bit of another binary number is generated having a reduced form in order to reduce the steps required in array reduction.
Inventors:
MEULEMANS PETER (GB)
RUMYNIN DMITRIY (RU)
TALWAR SUNIL (GB)
RUMYNIN DMITRIY (RU)
TALWAR SUNIL (GB)
Application Number:
PCT/GB2001/003415
Publication Date:
March 13, 2003
Filing Date:
July 27, 2001
Export Citation:
Assignee:
AUTOMATIC PARALLEL DESIGNS LTD (GB)
MEULEMANS PETER (GB)
RUMYNIN DMITRIY (RU)
TALWAR SUNIL (GB)
MEULEMANS PETER (GB)
RUMYNIN DMITRIY (RU)
TALWAR SUNIL (GB)
International Classes:
G06F7/53; G06F7/52; G06F7/60; (IPC1-7): G06F7/60; G06F7/50; G06F7/52; G06F17/50
Foreign References:
| US3757098A | 1973-09-04 | |||
| US5175862A | 1992-12-29 | |||
| US3634658A | 1972-01-11 | |||
| US5524082A | 1996-06-04 | |||
| EP0168650A2 | 1986-01-22 | |||
| US6023566A | 2000-02-08 | |||
| EP0309292A2 | 1989-03-29 |
Other References:
DRECHSLER R ET AL: "Sympathy: fast exact minimization of fixed polarity Reed-Muller expressions for symmetric functions", IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, JAN. 1997, IEEE, USA, vol. 16, no. 1, pages 1 - 5, XP002217407, ISSN: 0278-0070
DEBNATH D ET AL: "MINIMIZATION OF AND-OR-EXOR THREE-LEVEL NETWORKS WITH AND GATE SHARING", IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, INSTITUTE OF ELECTRONICS INFORMATION AND COMM. ENG. TOKYO, JP, vol. E80-D, no. 10, 1 October 1997 (1997-10-01), pages 1001 - 1008, XP000730839, ISSN: 0916-8532
DRECHSLER R ET AL: "Sympathy: fast exact minimization of fixed polarity Reed-Muller expressions for symmetric functions", EUROPEAN DESIGN AND TEST CONFERENCE, 1995. ED&TC 1995, PROCEEDINGS. PARIS, FRANCE 6-9 MARCH 1995, LOS ALAMITOS, CA, USA,IEEE COMPUT. SOC, US, 6 March 1995 (1995-03-06), pages 91 - 97, XP010148035, ISBN: 0-8186-7039-8
NIENHAUS H A: "Efficient multiplexer realizations of symmetric functions", IEEE SOUTHEASTCON 1981 CONFERENCE PROCEEDINGS, HUNTSVILLE, AL, USA, 5-8 APRIL 1981, 1981, New York, NY, USA, IEEE, USA, pages 522 - 525, XP010277476
CHAKRABORTY S ET AL: "Synthesis of symmetric functions for path-delay fault testability", VLSI DESIGN, 1999. PROCEEDINGS. TWELFTH INTERNATIONAL CONFERENCE ON GOA, INDIA 7-10 JAN. 1999, LOS ALAMITOS, CA, USA,IEEE COMPUT. SOC, US, 7 January 1999 (1999-01-07), pages 512 - 517, XP010320035, ISBN: 0-7695-0013-7
DEBNATH D ET AL: "MINIMIZATION OF AND-OR-EXOR THREE-LEVEL NETWORKS WITH AND GATE SHARING", IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, INSTITUTE OF ELECTRONICS INFORMATION AND COMM. ENG. TOKYO, JP, vol. E80-D, no. 10, 1 October 1997 (1997-10-01), pages 1001 - 1008, XP000730839, ISSN: 0916-8532
DRECHSLER R ET AL: "Sympathy: fast exact minimization of fixed polarity Reed-Muller expressions for symmetric functions", EUROPEAN DESIGN AND TEST CONFERENCE, 1995. ED&TC 1995, PROCEEDINGS. PARIS, FRANCE 6-9 MARCH 1995, LOS ALAMITOS, CA, USA,IEEE COMPUT. SOC, US, 6 March 1995 (1995-03-06), pages 91 - 97, XP010148035, ISBN: 0-8186-7039-8
NIENHAUS H A: "Efficient multiplexer realizations of symmetric functions", IEEE SOUTHEASTCON 1981 CONFERENCE PROCEEDINGS, HUNTSVILLE, AL, USA, 5-8 APRIL 1981, 1981, New York, NY, USA, IEEE, USA, pages 522 - 525, XP010277476
CHAKRABORTY S ET AL: "Synthesis of symmetric functions for path-delay fault testability", VLSI DESIGN, 1999. PROCEEDINGS. TWELFTH INTERNATIONAL CONFERENCE ON GOA, INDIA 7-10 JAN. 1999, LOS ALAMITOS, CA, USA,IEEE COMPUT. SOC, US, 7 January 1999 (1999-01-07), pages 512 - 517, XP010320035, ISBN: 0-7695-0013-7
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