TECHNICAL FIELD

[0001] The aspects of the disclosed embodiments relate generally to analog to digital converters and more particularly to amplifier circuits used therein.

BACKGROUND

[0002] Switched capacitor residue amplifiers, also referred to as switched capacitor amplifiers (SCA), are key building blocks used to create popular types of analog to digital converters (ADC), such as pipeline analog to digital converters. The use of nano-scaled complementary metal-oxide-semiconductor (CMOS) technologies has introduced new challenges into the design of high performance SCA. Decreased voltage headroom and the intrinsic gain of transistors in nano-scaled CMOS technologies have made it difficult to achieve the large open-loop gain necessary to provide the desired closed-loop gain accuracy. Nanoscaled CMOS technologies also make it difficult to achieve high output swings necessary for supporting larger load currents used to decrease Johnson-Nyquist or KT/C noise. Therefore, it has become difficult to use conventional operational amplifier topologies in nano-scaled CMOS technologies.

[0003] Thus, there is a need for improved switched capacitor amplifier topologies that can provide high gain, linearity, and accuracy while also providing rapid settling times. Accordingly, it would be desirable to provide an apparatus that addresses at least some of the problems described above.

SUMMARY

[0004] The aspects of the disclosed embodiments are directed to a parallel path switched capacitor amplifier apparatus employing a switched capacitor amplifier coupled in parallel with a feed-forward circuit configured to provide additional current to the output node. The aspects of the disclosed embodiments provide improved settling times allowing for a shorter conversion phase. This and other objectives are addressed by the subject matter of the independent claims. Further advantageous modifications can be found in the dependent claims.

[0005] According to a first aspect, the above and further objectives and advantages are obtained by an apparatus. In one embodiment, the apparatus includes a switched capacitor amplifier coupled between an input voltage and an output voltage, and a feed-forward circuit coupled between the input voltage and the output voltage, where the feed-forward circuit is coupled in parallel with the switched capacitor amplifier. The switched capacitor amplifier includes: a first capacitor; a second capacitor; and a linear amplifier. The linear amplifier is configured to receive a summing node voltage from a summing node and produce the output voltage at an output node. During a conversion phase the switched capacitor amplifier is configured to couple the first capacitor between a common voltage and the summing node and couple the second capacitor between the summing node and the output node. The feed-forward circuit is configured to receive the input voltage and the summing node voltage, and deliver a current to the output node.

[0006] In a possible implementation form of the apparatus, during the conversion phase, the feed-forward circuit is configured to generate a high signal and a low signal based on the input voltage. When the summing node voltage is greater than the high signal, or the summing node voltage is less than the low signal, the feed-forward circuit delivers the current to the output node. When the summing node voltage is less than or equal to the high signal, and greater than or equal to the low signal, the feed-forward circuit does not deliver current to the output node. Settling time is improved by having the feed-forward circuit deliver current to the output node when the summing node voltage is outside a central operating region, such as between the high signal and the low signal.

[0007] In a possible implementation form of the apparatus, during a sampling phase, the switched capacitor amplifier is configured to couple the first capacitor and the second capacitor in parallel between the input voltage and a common voltage. Charging both the first capacitor and the second capacitor to the input voltage facilitates settling of the output voltage during the conversion phase.

[0008] In a possible implementation form of the apparatus, the feed-forward circuit includes a hysteresis circuit configured to receive the input voltage and produce the high signal and the low signal; a quantization circuit configured to receive the high signal, the low signal and the summing node voltage, and produce an up signal and a down signal; and a current pump circuit configured to receive the up signal and the down signal, and deliver the current to the output node based on the up signal and the down signal. A feed-forward circuit constructed of a hysteresis circuit, quantizer, and current pump provides a simple and reliable implementation form.

[0009] In a possible implementation form of the apparatus, when the delivered current is positive, the current pump circuit sources current to the output node, and when the delivered current is negative, the current pump circuit sinks current from the output node. Providing a bidirectional current to the output node aids symmetric bi-polar operation of the SCA.

[0010] In a possible implementation form of the apparatus, the linear amplifier includes an operational amplifier. An operational amplifier is a simple and well understood type of linear amplifier thereby simplifying design of the SCA.

[0011] In a possible implementation form of the apparatus, the high signal and the low signal are generated by level shifting the input voltage. Level shifting the input voltage is a reliable and easily implemented approach to generating the high signal and the low signal.

[0012] According to a second aspect, the above and further advantages are obtained by a method. In one embodiment the method includes operating a parallel path switched capacitor amplifier, wherein the parallel path switched capacitor amplifier includes a switched capacitor amplifier coupled in parallel with a feed-forward circuit. The switched capacitor amplifier includes a first capacitor, a second capacitor and a linear amplifier, where the linear amplifier is configured to receive a summing node voltage at a summing node and produce an output voltage at an output node. The method includes, during a conversion phase, coupling the first capacitor and the second capacitor in series between a common voltage and the output voltage thereby forming the summing node between the first capacitor and the second capacitor; operating the linear amplifier to adjust the output voltage and force the summing node voltage to the common voltage; and deliver a current, using a feed-forward circuit, to the output voltage.

[0013] In a possible implementation form of the method, the method further includes generating a high signal and a low signal based on the input voltage. When the summing node voltage is greater than the high signal or the summing node voltage is less than the low signal, the feed-forward circuit is used to deliver the current to the output voltage, and when the summing node voltage is between the high voltage and the low voltage, current is not delivered to the output voltage. Delivering current when the summing node voltage is outside the region defined by the high signal and the low signal reduces the settling time of the output voltage. Not delivering current when the summing node voltage is close to its final value allows the linear amplifier to generate an accurate output voltage.

[0014] In a possible implementation form of the method, the method further includes, during a sampling phase, charging the first capacitor and the second capacitor to the input voltage. Charging the capacitors to the input voltage during the sampling phase allows the linear amplifier to use the stored charge during the conversion phase to determine the output voltage.

[0015] In a possible implementation form of the method, when the delivered current is positive, the feed forward circuit sources current to the output voltage, and when the delivered current is negative, the feed forward circuit sinks current from the output voltage. Providing a bi-directional current to the output voltage aids symmetric bi-polar operation of the SCA.

[0016] In a possible implementation form of the method, the method further includes generating the high signal and the low signal by level shifting the input voltage. Level shifting the input voltage provides a simple and reliable method for determining appropriate values for the high signal and the low signal.

[0017] These and other aspects, implementation forms, and advantages of the exemplary embodiments will become apparent from the embodiments described herein considered in conjunction with the accompanying drawings. It is to be understood, however, that the description and drawings are designed solely for purposes of illustration and not as a definition of the limits of the disclosed invention, for which reference should be made to the appended claims. Additional aspects and advantages of the invention will be set forth in the description that follows, and in part will be obvious from the description, or may be learned by practice of the invention. Moreover, the aspects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In the following detailed portion of the present disclosure, the aspects of the disclosed embodiments will be explained in more detail with reference to the example embodiments shown in the drawings, in which like references indicate like elements and:

[0019] Figure 1 illustrates a block diagram showing a conversion phase configuration of an exemplary parallel path switched capacitor amplifier incorporating aspects of the disclosed embodiments;

[0020] Figure 2 illustrates a schematic diagram showing a sampling phase capacitor configuration of an exemplary parallel path switched capacitor amplifier incorporating aspects of the disclosed embodiments;

[0021] Figure 3 illustrates a schematic diagram of an exemplary parallel path switched capacitor amplifier incorporating aspects of the disclosed embodiments;

[0022] Figure 4 illustrates a graph showing an exemplary output voltage waveform of a parallel path switched capacitor amplifier incorporating aspects of the disclosed embodiments;

[0023] Figure 5 illustrates a graph showing an exemplary summing node voltage waveform of a parallel path switched capacitor amplifier incorporating aspects of the disclosed embodiments; and

[0024] Figure 6 illustrates a flow chart depicting an exemplary method for operating a parallel path switched capacitor amplifier incorporating aspects of the disclosed embodiments.

DETAILED DESCRIPTION OF THE DISCLOSED EMBODIMENTS

[0025] Referring to Figure 1, a block diagram of a conversion phase configuration of an exemplary parallel path switched capacitor amplifier apparatus 100 is illustrated. The apparatus 100 of the disclosed embodiments is directed to an improved parallel path switched capacitor amplifier incorporating a feed-forward path 104 coupled in parallel with a switched capacitor amplifier (SCA) 102. The feed forward path 104 is configured to provide a suitably large current i ₀ to the output node 116 during periods in which the summing node voltage IF is outside a central operating region. The apparatus 100 is appropriate for use in various types of analog to digital converters and can improve conversion times by reducing settling time of the Output Voltage Pout-

[0026] In one embodiment, the apparatus 100 includes a switched capacitor amplifier 102 coupled between an input voltage Pin and an output voltage Pout. The exemplary switched capacitor amplifier 102 includes a first capacitor Ci, a second capacitor C2, and a linear amplifier 112. In the illustrated embodiment the linear amplifier 112 employs an operational amplifier having its non-inverting input 122 connected to the common voltage VCM. The inverting input 118 of the linear amplifier 112 is connected to a summing node 114. The linear amplifier 112 is configured to receive the summing node voltage FF from the summing node 114, and produce the output voltage Pout at the output node 116.

[0027] As an aid to understanding, the schematic diagram of apparatus 100 illustrated in Figure 1 has been simplified. Switching devices used to re-configure the apparatus 100 during a sampling phase and a conversion phase are not shown in the apparatus 100 and the apparatus 100 is depicted in a conversion phase configuration. As will be discussed further below, during a sampling phase the first capacitor Ci is coupled to the input voltage Fin, thereby charging the first capacitor Ci to the input voltage Pin. During a conversion phase, the first capacitor Ci is coupled between the summing node 114 and the common voltage VCM thereby allowing charge stored on the first capacitor Ci to be used by the linear amplifier 112. The node denoted as Pin/ VCM may be viewed as being coupled to the input voltage Pin during the sampling phase and to the common voltage VCM during the conversion phase.

[0028] During a conversion phase the switched capacitor amplifier 102 is configured to couple the first capacitor Ci between the common voltage VCM and the summing node 114 and couple the second capacitor C2 between the summing node 114 and the output node 116.

[0029] Nano-scaled CMOS technologies impose challenges making it difficult to create switched capacitor amplifiers having a large open-loop gains necessary to achieve desired closed-loop gain accuracy. These technologies also make it difficult to achieve the high output swings necessary for supporting larger load currents used to decrease Johnson-Nyquist or KT/C noise. To help mitigate these problems, in one embodiment, the switched capacitor amplifier 102 is coupled in parallel with a feed-forward circuit 104. The feed-forward circuit 104 is configured to receive input voltage Fin, summing node voltage FF, and deliver current i ₀ to the output node 116. The current i ₀ may be any suitably large current as needed to help adjust the output voltage Pout in a way that drives the summing node voltage FF toward its final value, which in the illustrated embodiment will be the common voltage VCM. The additional current helps the linear amplifier 112 drive the summing node voltage FF to its final value thereby reducing the settling time of the switched capacitor amplifier.

[0030] The delivered current i ₀ may be either a positive current or a negative current, as needed to help drive the output voltage Pout toward its desired final value. When the delivered current i ₀ is positive (+) the current pump 110 acts as a current source, pumping current into the output node 116. When the delivered current i ₀ is negative (-) the current pump 110 acts as a current sink, pulling current away from the output node 116.

[0031] As will be discussed further below, the parallel path switched capacitor amplifier apparatus 100 employs switches, such as semiconductor switching devices, to reconfigure the circuit topology of the parallel path switched capacitor amplifier apparatus 100 thereby periodically alternating between a sampling phase topology and a conversion phase topology. During the sampling phase, the switched capacitor amplifier apparatus 100 is configured to sample an input voltage Fin and charge the capacitors Ci and C2 to a desired initial value based on the input voltage Fin. During the conversion phase, the apparatus 100 is configured as a parallel path switched capacitor amplifier, such as the parallel path switched capacitor amplifier illustrated in Figure 1. The switched capacitor amplifier 102 is configured to adjust the output voltage Fout until the summing node voltage FF is equal to the common voltage VCM. Also, during the conversion phase, the feed-forward circuit 104 is configured to deliver a current i ₀ to the output node 116 while the summing node voltage FF is outside a central operating region.

[0032] During the conversion phase the exemplary switched capacitor amplifier 102 employs an operational amplifier 112 configured in an inverting amplifier topology. The summing node 114 is connected to a first capacitor Ci and to an inverting input 118 of the operational amplifier 112. The non-inverting input 122 of the operation amplifier 112 is connected to a common voltage VCM, and the second capacitor C2 is connected between the summing node and an output node 116. The output 120 of the operational amplifier 112 is connected to the output node 116 of the parallel path switched capacitor amplifier apparatus 100. With this configuration the operational amplifier 112 adjusts the output voltage Fout to force the summing node voltage FF equal to the common voltage VCM. [0033] The feed-forward circuit 104 is configured to deliver a current i ₀ to the output node 116 during a conversion phase based on the input voltage Fin and the summing node voltage FF. In the exemplary feed-forward circuit 104, a hysteresis circuit 106 is configured to receive the input voltage Fin and generate a high signal VH and a low signal VL. In one embodiment, the high signal VH and low signal VL are generated by level shifting the input voltage Fin. The high signal VH and low signal VL define three operating regions used to determine when the current i ₀ should be delivered to the output node 116.

[0034] When the summing node voltage is greater than the high signal, FF >VH, or the summing node voltage is less than the low signal, FF < VL, the feed-forward circuit 104 delivers the current i ₀ to the output node 116. The operating region where the summing node voltage is less than or equal to the high signal and greater than or equal to the low signal, VL < FF < VH, is referred to herein as the central operating region. While the summing node voltage is within the central operating region VL < FF < VH, the feed-forward circuit does not deliver current i ₀ to the output node 116. The use of a feed-forward circuit 104 to deliver additional current to the output node 116 while the summing node voltage FF is outside the central operating region, improves the settling time of the amplifier 102 and the output voltage Pout settles to its desired final value more quickly than is achievable with the switched capacitor amplifier 102 alone. Those skilled in the art will readily recognize that the greater than > comparison operation may be swapped with a greater than or equal to comparison operation and the less than < comparison operation may be swapped with a less than or equal to < comparison operation without straying from the spirit and scope of the present disclosure.

[0035] The exemplary feed-forward circuit 104 employs a quantizer 108 to generate an up signal UP and a down DN signal based on the operating regions described above. The up signal UP and the down signal DN may, for example, be logic signals having an active or activated state and an inactive or deactivated state. When the summing node voltage is greater than the high signal, FF >VH, the up signal UP may be activated, and when the summing node voltage is less than the low signal, FF <VL, the down DN signal may be activated.

[0036] The up signal UP and the down signal DN are provided as inputs to a current pump 110 configured to source or sink the current i ₀ to the output node 116 based on activation of the up signal UP or the down DN signal. The current i ₀ delivered to the output node 116 by the current pump 110 may be any desired amount of current configured to reduce the settling time of the output voltage FOUL [0037] Figure 2 illustrates a schematic diagram showing the sampling phase capacitor configuration 200 of an exemplary parallel path switched capacitor amplifier apparatus 100 incorporating aspects of the disclosed embodiments. The capacitor configuration 200 depicts how the first capacitor Ci and the second capacitor C2 of the parallel path switched capacitor amplifier apparatus 100 may be configured during a sampling phase of operation. The capacitors Ci and C2 illustrated in Figure 2 are similar to the capacitors Ci and C2 illustrated in Figure 1, where like references indicate like elements. The capacitor configuration 200 of the exemplary switched capacitor amplifier apparatus 100 is directed to a sampling phase capacitor configuration configured to charge the amplifier capacitors Ci, C2 to the input voltage Fin while the parallel path switched capacitor amplifier apparatus 100 is operating in a sampling phase.

[0038] As will be discussed further below, switches or switching devices are employed in the parallel path switched capacitor amplifier apparatus 100. This allows the circuit elements to be alternately reconfigured between a sampling phase configuration where the first capacitor Ci and the second capacitor C2 are charged to the input voltage Fin, and a conversion phase configuration, as shown in Figure 1 above, where the output voltage Fout is controlled by the linear amplifier 112 based on charge stored on the first capacitor Ci, and the second capacitor C2 during the sampling phase.

[0039] Figure 3 illustrates a schematic diagram of an exemplary parallel path switched capacitor amplifier apparatus 300 incorporating aspects of the disclosed embodiments. The exemplary apparatus 300 of the disclosed embodiments is configured during a conversion phase as a parallel path switched capacitor amplifier apparatus , such as the parallel path SCA apparatus 100 described above and with reference to Figure 1, and to be configured during a sampling phase to charge the first and second capacitors C301, C302 to the input voltage Fin as described above and with reference to Figure 2.

[0040] The exemplary apparatus 300 includes two sets of switches (p _s , (p _c configured to charge a first capacitor C301 and a second capacitor C302 to the input voltage Fin during a sampling phase, and to configure the apparatus 300 as a parallel path switched capacitor amplifier during a conversion phase. In the exemplary apparatus 300 the two sets of switches cps, <Pc may be any suitable switching device such as semiconductor switching devices. Alternatively, any appropriate type of switching device capable of efficiently configuring the apparatus 300 for sampling phase operation and conversion phase operation may be advantageously employed. [0041] Turning the first set of switches (p _s on and the second set of switches (p _c off configures the apparatus 300 for sampling phase operation. As used herein a switch is referred to as "on" or "turned on" when it is conducting electric current, and a switch is referred to as "off ¹ or "turned off' when it is not conducting electric current. During the sampling phase or sampling phase operation, the first capacitor C301 and the second capacitor C302 are charged along with a hysteresis zone capacitor CH to the input voltage Fin. Also, during the sampling phase, a load capacitor CL is charged to the common voltage VCM. Circuit ground is depicted in Figure 3 as an unshaded and inverted triangle symbol 318.

[0042] When the sampling phase is complete, the apparatus 300 is configured for conversion phase operation by turning off the first set of switches (p _s and turning on the second set of switches (p _c . During the conversion phase or conversion phase operation, the apparatus 300 is configured as a parallel path switched capacitor amplifier, similar to the parallel path switched capacitor amplifier apparatus 100 described above and with reference to Figure 1. When configured as a parallel path switched capacitor amplifier, the exemplary apparatus 300 includes a switched capacitor amplifier 302 coupled in parallel with a feed-forward circuit 304 between the input voltage Fin and the output voltage FOUL

[0043] During the conversion phase, the exemplary apparatus 300 includes an amplifier 302 based on an operational amplifier 312 configured as inverting amplifier. The first capacitor C301 is coupled between the common voltage VCM and the summing node 314, and the second capacitor C302 is connected between the summing node 314 and the output voltage FOUL During the conversion phase, the input voltage Fin is provided to the switched capacitor amplifier 302 by the charge stored on the first capacitor C301 during the sampling phase. The summing node 314 is formed between the first capacitor C301 and the second capacitor C302 and is connected to an inverting input of the operational amplifier 312. The operational amplifier 312 is configured to adjust the output voltage Fout until the summing node voltage FF is substantially equal to the common voltage VCM.

[0044] A feed-forward circuit 304 is coupled in parallel with the linear amplifier 302 and configured to provide additional current Ip, IN to the output node 316 to improve amplifier response time and reduce the conversion phase. The feed-forward circuit 304 will sink or source a suitably large current to the output node 316 as necessary to adjust the output voltage Fout toward to a desired final output value. [0045] In the exemplary feed-forward circuit 304, a hysteresis zone 306 receives the input voltage Pin and produces a high signal VH and a low signal VL. The hysteresis zone 306 charges a hysteresis capacitor CH to the input voltage Pin during the sampling phase, and uses the voltage on the hysteresis capacitor CH during the conversion phase. In one embodiment, the hysteresis zone 306 level shifts the input voltage Pin, which is stored in the hysteresis capacitor CH, to product the high signal VH and the low signal VL.

[0046] A quantizer 308 receives the high signal VH and the low signal VL produced by the hysteresis zone 306 and compares these signals to a summing node voltage PF to produce a pair of logic signals UP, DN used to drive current pumps 310. When the summing node voltage is greater than the high signal PF > VH, the quantizer 308 activates the down logic signal DN, and when the summing node voltage is less than the low signal PF < VL the quantizer 308 activates the up logic signal UP. When the summing node voltage is between the high signal and the low signal, VL < PF < VH, the quantizer 308 deactivates both the up logic signal UP and the down logic signal DN.

[0047] In the exemplary feed-forward circuit 304 illustrated in Figure 3, the up and down logic signals UP, DN are received by a current pump 310 and used to control injection of current into the output node 316. The current pump 310 is configured to inject a suitably large current IP, IN into the output node 316 where the injected current IP, IN is configured to move the output voltage Pout toward its final value. Applying additional current IP, IN with the current pump 310 changes the output voltage Pout more quickly than the operational amplifier 312 could achieve on its own.

[0048] The current pump 310 may be configured to produce any suitably large current IP, IN. Current produced by the current pump 310 does not need to be dynamically adjusted during the conversion phase so there is no need to include complex feedback logic as is the case with conventional linear amplifier topologies. By appropriate selection of high signal VH and low signal VL, dynamic control of current being pumped into the output node 316 by the current pump 310 can be avoided thereby simplifying design of the current pump 310.

[0049] Figure 4 illustrates graph 400 depicting an output voltage waveform 406 of an exemplary parallel path switched capacitor amplifier apparatus incorporating aspects of the disclosed embodiments. The output voltage waveform 406 is produced during a conversion phase of a parallel path switched capacitor amplifier apparatus , such as the exemplary switched capacitor amplifier apparatus 100 described above. For comparison purposes, the output voltage waveform of a conventional switched capacitor amplifier apparatus is shown as a dashed line indicated by numeral 408. In the graph400, time is depicted along a horizontal axis 404 increasing to the right, and voltage is depicted along a vertical axis 402 with magnitude increasing upwards. The beginning of the conversion phase is marked on the horizontal axis as time to. At time to the sampling phase ends and the conversion phase begins. The conversion phase continues to the right of time to.

[0050] Comparison of the output voltage 406 produced by a parallel path switched capacitor amplifier apparatus, such as the parallel path switched capacitor amplifier apparatus 100 or 300 described above, with the output voltage 408 of a conventional switched capacitor amplifier apparatus shows that the output voltage 406 of an exemplary parallel path switched capacitor amplifier apparatus rises toward its final value Vs much more quickly than the output voltage 408 of a conventional switched capacitor amplifier apparatus. The performance improvement illustrated in graph 400 is achieved through the use of a novel feed forward circuit 104 to provide additional current to the output voltage 406.

[0051] Figure 5 illustrates graph 500 depicting a summing node voltage waveform 508 of an exemplary parallel path switched capacitor amplifier apparatus incorporating aspects of the disclosed embodiments. The summing node voltage waveform 506 is produced during a conversion phase of a parallel path switched capacitor amplifier apparatus , such as the exemplary parallel path switched capacitor amplifier apparatus 100 described above and with refence to Figure 1. For comparison purposes, the summing node voltage waveform of a conventional switched capacitor amplifier apparatus is shown as a dashed line indicated by numeral 508. In graph 500, time is depicted along a horizontal axis 504 increasing to the right, and voltage is depicted along a vertical axis 502 with magnitude increasing upwards. The beginning of the conversion phase is marked on the horizontal axis as time to. At time to the sampling phase ends and the conversion phase begins. The conversion phase continues to the right of time to.

[0052] Some relevant operating voltages are marked along the vertical axis 502 of the graph 500. Vto is the initial summing node voltage present at the beginning of the conversion phase, VCM is the common voltage and final value of the summing node voltage F, VL is the low signal produced the hysteresis zone 306, and VH is the high signal produced by the hysteresis zone 306. [0053] Operating regions 510, 512, 514 of the feed-forward circuit 104 are shown along the right side of the graph 500. A central operating region 512 is defined by a summing node voltage that is between the high signal and the low signal, VL < PF < VH. While the summing node voltage 506 is within the central operating region 512, no current is produced by the feedforward circuit 104 and the output voltage is controlled by the switched capacitor amplifier 102. While the summing node voltage 506 is above the high signal VH, an operating region indicated by numeral 510, the feed-forward circuit 102 produces a current that reduces the summing node voltage 506, and while the summing node voltage 506 is below the low signal VL, an operating region indicated by numeral 514, the feed-forward circuit produces a current that increases the summing node voltage. The graph 508 shows how production of additional current by the feedforward circuit 104 while the summing node voltage is in operating region 514 reduces settling time as compared to a conventional switched capacitor amplifier.

[0054] Figure 6 illustrates a flow chart depicting an exemplary method 600 for operating a parallel path switched capacitor amplifier apparatus incorporating aspects of the disclosed embodiments. The exemplary method 600 is appropriate for operating a parallel path switched capacitor amplifier apparatus, such as the apparatus 100 described above. As an aid to understanding the exemplary method 600 will be described with reference to the exemplary apparatus 100 described above and with reference to Figure 1.

[0055] In one embodiment the method 600 is configured to operate a parallel path SCA, such as the parallel path SCA apparatus 100, which includes a first capacitor Ci, a second capacitor C2, and a linear amplifier. The linear amplifier is configured to receive a summing node voltage PF at a summing node and produce an output voltage Pout at an output node. In one embodiment the parallel path switched capacitor amplifier includes a feed-forward circuit configured to provide a current i ₀ to the output voltage Pout based on the input voltage Pin and the summing node voltage PF. The method 600 includes different operating steps for different operating phases of the parallel path SCA apparatus, and begins 622 by selecting 602 the desired operating steps based on an operating phase of the apparatus 100.

[0056] During a conversion phase 628, the method 600 is configured to couple 606 the first capacitor Ci and the second capacitor C2 in series between the common voltage VCM and the output voltage Pout thereby forming the summing node 114 between the first capacitor Ci and the second capacitor C2. The linear amplifier 112 of Figure 1 is operated 608 to adjust the output voltage Pout to force the summing node voltage PF to the common voltage VCM. The feed-forward circuit 104 of Figure 1, which is coupled in parallel with the switched capacitor amplifier 102 between the input voltage Fin and the output voltage Fout, is configured to receive the input voltage Fin and the summing node voltage FF, and deliver 616 a current i ₀ to the output node voltage Four In one embodiment a hysteresis capacitor CH is charged to the input voltage Fin during a sampling phase. The charge on the hysteresis capacitor CH is applied to the feed forward circuit 104 of Figure 1 during the conversion phase.

[0057] The current i ₀ applied to the output voltage Fout may be a positive current or a negative current as required to force the summing node voltage FF toward the common voltage VCM. When a positive current i ₀ is indicated, the feed forward circuit 104 operates as a current source to deliver current i ₀ to the output voltage Fout, and when a negative current i ₀ is indicated, the feed forward circuit 104 operates as a current sink to remove current i ₀ from the output voltage Fout.

[0058] The exemplary method 600 determines 612 whether to deliver 618 current i ₀ to the output node or not deliver 620 current i ₀ to the output node based on an operating region of the switched capacitor amplifier 102. The method 600 generates 610 a high signal VH and a low signal VL based on the input voltage. In one embodiment, the high signal VH and low signal VL may be generated by level shifting the input voltage Fin.

[0059] The method 600 determines 612 whether to deliver current i ₀ to the output node by comparing the summing node voltage FF to the high signal VH and the low signal VL. AS discussed above, the high signal VH and the low signal VL define a central operating region about the common voltage VCM. When the summing node voltage FF is within this central operating region the feed-forward circuit 104 of Figure 1 is configured to not deliver 614 current to the output node 116. When the summing node voltage is outside the central operating region, the feed-forward circuit 104 of Figure 1 is configured to deliver 616 current to the output node 116 of Figure 1. As used herein the term delivering current to the output node 116 is used interchangeably with the term delivering current to the output voltage FOUL In one embodiment, the central operating region is defined as the region where the summing node voltage is less than or equal to the high signal VH and greater than or equal to the low signal VL.

[0060] The operating regions are presented as an aid to understanding only. Alternatively, the feed-forward circuit logic may be described relative to the high signal VH, the low signal VL, and the summing node voltage FF. When the summing node voltage is between the high voltage and the low voltage (VL < PF < VH), the exemplary method 600 does not deliver 614 current to the output voltage Pout. When the summing node voltage is greater than the high signal (PF > VH) or the summing node voltage is less than the low signal (PF < VL), current is delivered 616 to the output voltage Pout. As described above, the central operating region may be defined by either an open interval or a closed interval without straying from the spirit and scope of the present disclosure.

[0061] During a sampling phase 626, the exemplary method 600 charges the first capacitor Ci and the second capacitor C2 to the input voltage Pin. This charge is then used during the conversion phase 628 to determine the output voltage Pout.

[0062] When an operating phase is complete the method 600 exits 624 and begins 622 again at the start of the next operating phase.

[0063] Thus, while there have been shown, described and pointed out, fundamental novel features of the invention as applied to the exemplary embodiments thereof, it will be understood that various omissions, substitutions and changes in the form and details of devices and methods illustrated, and in their operation, may be made by those skilled in the art without departing from the spirit and scope of the presently disclosed invention. Further, it is expressly intended that all combinations of those elements, which perform substantially the same function in substantially the same way to achieve the same results, are within the scope of the invention. Moreover, it should be recognized that structures and/or elements shown and/or described in connection with any disclosed form or embodiment of the invention may be incorporated in any other disclosed or described or suggested form or embodiment as a general matter of design choice. It is the intention, therefore, to be limited only as indicated by the scope of the claims appended hereto.