Title:
PARASITIC PARAMETER ACQUISITION METHOD, AND DEVICE
Document Type and Number:
WIPO Patent Application WO/2023/130565
Kind Code:
A1
Abstract:
A parasitic parameter acquisition method, and a device. The method comprises: acquiring, from a circuit schematic diagram, the position of a target circuit signal line in a target circuit module (S101); determining a target layout signal line according to the position of the target circuit signal line in the target circuit module and a layout that corresponds to the circuit schematic diagram (S102); extracting, from a parasitic netlist of a locally stored layout, structure information of a parasitic resistor and/or capacitance network of the target layout signal line (S103); and determining a parasitic parameter of the target circuit signal line according to the structure information of the parasitic resistor and/or capacitance network of the target layout signal line (S104). By means of the method, a parasitic parameter can be automatically acquired, such that the efficiency is higher, the accuracy is higher, and the calculation process is simpler.
Inventors:
YOU SHAO (CN)
TANG PEIPEI (CN)
TANG PEIPEI (CN)
Application Number:
PCT/CN2022/079774
Publication Date:
July 13, 2023
Filing Date:
March 08, 2022
Export Citation:
Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
G06F30/39; G06F9/30; G06F115/12
Foreign References:
| CN107195563A | 2017-09-22 | |||
| CN112131830A | 2020-12-25 | |||
| CN103793548A | 2014-05-14 | |||
| CN107679311A | 2018-02-09 | |||
| CN102508975A | 2012-06-20 | |||
| CN112784520A | 2021-05-11 | |||
| US6363516B1 | 2002-03-26 |
Attorney, Agent or Firm:
LEADER PATENT & TRADEMARK FIRM (CN)
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