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Title:
PATTERN FOR INSPECTION AND INTEGRATED SEMICONDUCTOR CIRCUIT EQUIPPED THEREWITH
Document Type and Number:
WIPO Patent Application WO/2024/023969
Kind Code:
A1
Abstract:
A pattern for inspection is provided with which it is possible to conduct a wafer-level automatic inspection using a cantilever probe card. A pattern for inspection according to an embodiment of the present disclosure comprises a Cu pillar pad formed on a semiconductor substrate, a Cu pillar formed on the Cu pillar pad, and an inspection pad formed on the semiconductor substrate. The inspection pad is contiguous or adjacent to the Cu pillar pad and electrically connected thereto, and provides an area with which a cantilever probe comes into contact when a wafer-level automatic inspection is made.

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Inventors:
TAKAHASHI MASAYUKI (JP)
NASU YUSUKE (JP)
IKUMA YUICHIRO (JP)
TSUZUKI KEN (JP)
HINAKURA YOSUKE (JP)
Application Number:
PCT/JP2022/028926
Publication Date:
February 01, 2024
Filing Date:
July 27, 2022
Export Citation:
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Assignee:
NIPPON TELEGRAPH & TELEPHONE (JP)
International Classes:
H01L21/66; H01L21/60
Domestic Patent References:
WO2022024276A12022-02-03
Foreign References:
JP2015046569A2015-03-12
JP2011103334A2011-05-26
JP2018189699A2018-11-29
JP2012023065A2012-02-02
JP2014164272A2014-09-08
JP2018163216A2018-10-18
JP2014229632A2014-12-08
JP2003249534A2003-09-05
JP2005308558A2005-11-04
JP2004020708A2004-01-22
Attorney, Agent or Firm:
TANI & ABE, P.C. (JP)
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